2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
28 #ifdef HAVE_SYS_PARAM_H
29 #include <sys/param.h>
34 #include "gdb/sim-h8300.h"
36 #include "sys/types.h"
37 #include "sim-options.h"
45 host_callback *sim_callback;
47 static SIM_OPEN_KIND sim_kind;
50 /* FIXME: Needs to live in header file.
51 This header should also include the things in remote-sim.h.
52 One could move this to remote-sim.h but this function isn't needed
54 static void set_simcache_size (SIM_DESC, int);
56 #define X(op, size) (op * 4 + size)
58 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
60 #define h8_opcodes ops
62 #include "opcode/h8300.h"
64 /* CPU data object: */
67 sim_state_initialize (SIM_DESC sd, sim_cpu *cpu)
69 /* FIXME: not really necessary, since sim_cpu_alloc calls zalloc. */
71 memset (&cpu->regs, 0, sizeof(cpu->regs));
72 cpu->regs[SBR_REGNUM] = 0xFFFFFF00;
74 cpu->delayed_branch = 0;
79 /* Initialize local simulator state. */
81 sd->sim_cache_size = 0;
87 memset (&cpu->stats, 0, sizeof (cpu->stats));
93 h8_get_pc (SIM_DESC sd)
95 return (STATE_CPU (sd, 0)) -> pc;
99 h8_set_pc (SIM_DESC sd, unsigned int val)
101 (STATE_CPU (sd, 0)) -> pc = val;
105 h8_get_ccr (SIM_DESC sd)
107 return (STATE_CPU (sd, 0)) -> regs[CCR_REGNUM];
111 h8_set_ccr (SIM_DESC sd, unsigned int val)
113 (STATE_CPU (sd, 0)) -> regs[CCR_REGNUM] = val;
117 h8_get_exr (SIM_DESC sd)
119 return (STATE_CPU (sd, 0)) -> regs[EXR_REGNUM];
123 h8_set_exr (SIM_DESC sd, unsigned int val)
125 (STATE_CPU (sd, 0)) -> regs[EXR_REGNUM] = val;
129 h8_get_sbr (SIM_DESC sd)
131 return (STATE_CPU (sd, 0)) -> regs[SBR_REGNUM];
135 h8_set_sbr (SIM_DESC sd, int val)
137 (STATE_CPU (sd, 0)) -> regs[SBR_REGNUM] = val;
141 h8_get_vbr (SIM_DESC sd)
143 return (STATE_CPU (sd, 0)) -> regs[VBR_REGNUM];
147 h8_set_vbr (SIM_DESC sd, int val)
149 (STATE_CPU (sd, 0)) -> regs[VBR_REGNUM] = val;
153 h8_get_cache_top (SIM_DESC sd)
155 return sd -> cache_top;
159 h8_set_cache_top (SIM_DESC sd, int val)
161 sd -> cache_top = val;
165 h8_get_mask (SIM_DESC sd)
167 return (STATE_CPU (sd, 0)) -> mask;
171 h8_set_mask (SIM_DESC sd, int val)
173 (STATE_CPU (sd, 0)) -> mask = val;
177 h8_get_exception (SIM_DESC sd)
179 return (STATE_CPU (sd, 0)) -> exception;
183 h8_set_exception (SIM_DESC sd, int val)
185 (STATE_CPU (sd, 0)) -> exception = val;
188 static enum h8300_sim_state
189 h8_get_state (SIM_DESC sd)
195 h8_set_state (SIM_DESC sd, enum h8300_sim_state val)
201 h8_get_cycles (SIM_DESC sd)
203 return (STATE_CPU (sd, 0)) -> regs[CYCLE_REGNUM];
207 h8_set_cycles (SIM_DESC sd, unsigned int val)
209 (STATE_CPU (sd, 0)) -> regs[CYCLE_REGNUM] = val;
213 h8_get_insts (SIM_DESC sd)
215 return (STATE_CPU (sd, 0)) -> regs[INST_REGNUM];
219 h8_set_insts (SIM_DESC sd, unsigned int val)
221 (STATE_CPU (sd, 0)) -> regs[INST_REGNUM] = val;
225 h8_get_ticks (SIM_DESC sd)
227 return (STATE_CPU (sd, 0)) -> regs[TICK_REGNUM];
231 h8_set_ticks (SIM_DESC sd, unsigned int val)
233 (STATE_CPU (sd, 0)) -> regs[TICK_REGNUM] = val;
237 h8_get_mach (SIM_DESC sd)
239 return (STATE_CPU (sd, 0)) -> regs[MACH_REGNUM];
243 h8_set_mach (SIM_DESC sd, unsigned int val)
245 (STATE_CPU (sd, 0)) -> regs[MACH_REGNUM] = val;
249 h8_get_macl (SIM_DESC sd)
251 return (STATE_CPU (sd, 0)) -> regs[MACL_REGNUM];
255 h8_set_macl (SIM_DESC sd, unsigned int val)
257 (STATE_CPU (sd, 0)) -> regs[MACL_REGNUM] = val;
261 h8_get_compiles (SIM_DESC sd)
263 return sd -> compiles;
267 h8_increment_compiles (SIM_DESC sd)
272 static unsigned int *
273 h8_get_reg_buf (SIM_DESC sd)
275 return &(((STATE_CPU (sd, 0)) -> regs)[0]);
279 h8_get_reg (SIM_DESC sd, int regnum)
281 return (STATE_CPU (sd, 0)) -> regs[regnum];
285 h8_set_reg (SIM_DESC sd, int regnum, int val)
287 (STATE_CPU (sd, 0)) -> regs[regnum] = val;
292 h8_get_stats (SIM_DESC sd, int idx)
294 return sd -> stats[idx];
298 h8_increment_stats (SIM_DESC sd, int idx)
304 static unsigned short *
305 h8_get_cache_idx_buf (SIM_DESC sd)
307 return sd -> cache_idx;
311 h8_set_cache_idx_buf (SIM_DESC sd, unsigned short *ptr)
313 sd -> cache_idx = ptr;
316 static unsigned short
317 h8_get_cache_idx (SIM_DESC sd, unsigned int idx)
319 if (idx > sd->memory_size)
320 return (unsigned short) -1;
321 return sd -> cache_idx[idx];
325 h8_set_cache_idx (SIM_DESC sd, int idx, unsigned int val)
327 sd -> cache_idx[idx] = (unsigned short) val;
330 static unsigned char *
331 h8_get_memory_buf (SIM_DESC sd)
333 return (STATE_CPU (sd, 0)) -> memory;
337 h8_set_memory_buf (SIM_DESC sd, unsigned char *ptr)
339 (STATE_CPU (sd, 0)) -> memory = ptr;
343 h8_get_memory (SIM_DESC sd, int idx)
345 return (STATE_CPU (sd, 0)) -> memory[idx];
349 h8_set_memory (SIM_DESC sd, int idx, unsigned int val)
351 (STATE_CPU (sd, 0)) -> memory[idx] = (unsigned char) val;
354 static unsigned char *
355 h8_get_eightbit_buf (SIM_DESC sd)
357 return (STATE_CPU (sd, 0)) -> eightbit;
361 h8_set_eightbit_buf (SIM_DESC sd, unsigned char *ptr)
363 (STATE_CPU (sd, 0)) -> eightbit = ptr;
367 h8_get_eightbit (SIM_DESC sd, int idx)
369 return (STATE_CPU (sd, 0)) -> eightbit[idx];
373 h8_set_eightbit (SIM_DESC sd, int idx, unsigned int val)
375 (STATE_CPU (sd, 0)) -> eightbit[idx] = (unsigned char) val;
379 h8_get_delayed_branch (SIM_DESC sd)
381 return (STATE_CPU (sd, 0)) -> delayed_branch;
385 h8_set_delayed_branch (SIM_DESC sd, unsigned int dest)
387 (STATE_CPU (sd, 0)) -> delayed_branch = dest;
391 h8_get_command_line (SIM_DESC sd)
393 return (STATE_CPU (sd, 0)) -> command_line;
397 h8_set_command_line (SIM_DESC sd, char ** val)
399 (STATE_CPU (sd, 0)) -> command_line = val;
403 h8_get_cmdline_arg (SIM_DESC sd, int index)
405 return (STATE_CPU (sd, 0)) -> command_line[index];
409 h8_set_cmdline_arg (SIM_DESC sd, int index, char * val)
411 (STATE_CPU (sd, 0)) -> command_line[index] = val;
414 /* MAC Saturation Mode */
416 h8_get_macS (SIM_DESC sd)
418 return (STATE_CPU (sd, 0)) -> macS;
422 h8_set_macS (SIM_DESC sd, int val)
424 (STATE_CPU (sd, 0)) -> macS = (val != 0);
429 h8_get_macZ (SIM_DESC sd)
431 return (STATE_CPU (sd, 0)) -> macZ;
435 h8_set_macZ (SIM_DESC sd, int val)
437 (STATE_CPU (sd, 0)) -> macZ = (val != 0);
440 /* MAC Negative Flag */
442 h8_get_macN (SIM_DESC sd)
444 return (STATE_CPU (sd, 0)) -> macN;
448 h8_set_macN (SIM_DESC sd, int val)
450 (STATE_CPU (sd, 0)) -> macN = (val != 0);
453 /* MAC Overflow Flag */
455 h8_get_macV (SIM_DESC sd)
457 return (STATE_CPU (sd, 0)) -> macV;
461 h8_set_macV (SIM_DESC sd, int val)
463 (STATE_CPU (sd, 0)) -> macV = (val != 0);
466 /* End CPU data object. */
468 /* The rate at which to call the host's poll_quit callback. */
470 enum { POLL_QUIT_INTERVAL = 0x80000 };
472 #define LOW_BYTE(x) ((x) & 0xff)
473 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
474 #define P(X, Y) ((X << 8) | Y)
483 #define I (intMaskBit != 0)
485 #define BUILDSR(SD) \
486 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
487 | (N << 3) | (Z << 2) | (V << 1) | C)
490 /* Get Status Register (flags). */ \
491 c = (h8_get_ccr (sd) >> 0) & 1; \
492 v = (h8_get_ccr (sd) >> 1) & 1; \
493 nz = !((h8_get_ccr (sd) >> 2) & 1); \
494 n = (h8_get_ccr (sd) >> 3) & 1; \
495 u = (h8_get_ccr (sd) >> 4) & 1; \
496 h = (h8_get_ccr (sd) >> 5) & 1; \
497 ui = ((h8_get_ccr (sd) >> 6) & 1); \
498 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
501 #ifdef __CHAR_IS_SIGNED__
502 #define SEXTCHAR(x) ((char) (x))
506 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
509 #define UEXTCHAR(x) ((x) & 0xff)
510 #define UEXTSHORT(x) ((x) & 0xffff)
511 #define SEXTSHORT(x) ((short) (x))
515 int h8300_normal_mode = 0;
518 static int memory_size;
523 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
545 return (h8300hmode && !h8300_normal_mode)? SL : SW;
550 /* Simulate an indirection / dereference.
551 return 0 for success, -1 for failure.
555 lvalue (SIM_DESC sd, int x, int rn, unsigned int *val)
557 if (val == NULL) /* Paranoia. */
563 if (rn == ZERO_REGNUM)
564 *val = X (OP_IMM, SP);
566 *val = X (OP_REG, SP);
569 *val = X (OP_MEM, SP);
572 sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
581 if (h8300smode && !h8300_normal_mode)
583 else if (h8300hmode && !h8300_normal_mode)
590 decode (SIM_DESC sd, int addr, unsigned char *data, decoded_inst *dst)
592 int cst[3] = {0, 0, 0};
593 int reg[3] = {0, 0, 0};
594 int rdisp[3] = {0, 0, 0};
596 const struct h8_opcode *q;
601 /* Find the exact opcode/arg combo. */
602 for (q = h8_opcodes; q->name; q++)
604 const op_type *nib = q->data.nib;
605 unsigned int len = 0;
607 if ((q->available == AV_H8SX && !h8300sxmode) ||
608 (q->available == AV_H8S && !h8300smode) ||
609 (q->available == AV_H8H && !h8300hmode))
612 cst[0] = cst[1] = cst[2] = 0;
613 reg[0] = reg[1] = reg[2] = 0;
614 rdisp[0] = rdisp[1] = rdisp[2] = 0;
618 op_type looking_for = *nib;
619 int thisnib = data[len / 2];
621 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
622 opnum = ((looking_for & OP3) ? 2 :
623 (looking_for & DST) ? 1 : 0);
625 if (looking_for < 16 && looking_for >= 0)
627 if (looking_for != thisnib)
632 if (looking_for & B31)
634 if (!((thisnib & 0x8) != 0))
637 looking_for = (op_type) (looking_for & ~B31);
640 else if (looking_for & B30)
642 if (!((thisnib & 0x8) == 0))
645 looking_for = (op_type) (looking_for & ~B30);
648 if (looking_for & B21)
650 if (!((thisnib & 0x4) != 0))
653 looking_for = (op_type) (looking_for & ~B21);
656 else if (looking_for & B20)
658 if (!((thisnib & 0x4) == 0))
661 looking_for = (op_type) (looking_for & ~B20);
664 if (looking_for & B11)
666 if (!((thisnib & 0x2) != 0))
669 looking_for = (op_type) (looking_for & ~B11);
672 else if (looking_for & B10)
674 if (!((thisnib & 0x2) == 0))
677 looking_for = (op_type) (looking_for & ~B10);
680 if (looking_for & B01)
682 if (!((thisnib & 0x1) != 0))
685 looking_for = (op_type) (looking_for & ~B01);
688 else if (looking_for & B00)
690 if (!((thisnib & 0x1) == 0))
693 looking_for = (op_type) (looking_for & ~B00);
696 if (looking_for & IGNORE)
698 /* Hitachi has declared that IGNORE must be zero. */
702 else if ((looking_for & MODE) == DATA)
704 ; /* Skip embedded data. */
706 else if ((looking_for & MODE) == DBIT)
708 /* Exclude adds/subs by looking at bit 0 and 2, and
709 make sure the operand size, either w or l,
710 matches by looking at bit 1. */
711 if ((looking_for & 7) != (thisnib & 7))
714 cst[opnum] = (thisnib & 0x8) ? 2 : 1;
716 else if ((looking_for & MODE) == REG ||
717 (looking_for & MODE) == LOWREG ||
718 (looking_for & MODE) == IND ||
719 (looking_for & MODE) == PREINC ||
720 (looking_for & MODE) == POSTINC ||
721 (looking_for & MODE) == PREDEC ||
722 (looking_for & MODE) == POSTDEC)
724 reg[opnum] = thisnib;
726 else if (looking_for & CTRL)
729 if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) ||
730 ((looking_for & MODE) == EXR && (thisnib != C_EXR)) ||
731 ((looking_for & MODE) == MACH && (thisnib != C_MACH)) ||
732 ((looking_for & MODE) == MACL && (thisnib != C_MACL)) ||
733 ((looking_for & MODE) == VBR && (thisnib != C_VBR)) ||
734 ((looking_for & MODE) == SBR && (thisnib != C_SBR)))
736 if (((looking_for & MODE) == CCR_EXR &&
737 (thisnib != C_CCR && thisnib != C_EXR)) ||
738 ((looking_for & MODE) == VBR_SBR &&
739 (thisnib != C_VBR && thisnib != C_SBR)) ||
740 ((looking_for & MODE) == MACREG &&
741 (thisnib != C_MACH && thisnib != C_MACL)))
743 if (((looking_for & MODE) == CC_EX_VB_SB &&
744 (thisnib != C_CCR && thisnib != C_EXR &&
745 thisnib != C_VBR && thisnib != C_SBR)))
748 reg[opnum] = thisnib;
750 else if ((looking_for & MODE) == ABS)
752 /* Absolute addresses are unsigned. */
753 switch (looking_for & SIZE)
756 cst[opnum] = UEXTCHAR (data[len / 2]);
760 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
764 (data[len / 2 + 0] << 24) +
765 (data[len / 2 + 1] << 16) +
766 (data[len / 2 + 2] << 8) +
770 printf ("decode: bad size ABS: %d\n",
771 (looking_for & SIZE));
775 else if ((looking_for & MODE) == DISP ||
776 (looking_for & MODE) == PCREL ||
777 (looking_for & MODE) == INDEXB ||
778 (looking_for & MODE) == INDEXW ||
779 (looking_for & MODE) == INDEXL)
781 switch (looking_for & SIZE)
784 cst[opnum] = thisnib & 3;
787 cst[opnum] = SEXTCHAR (data[len / 2]);
790 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
791 cst[opnum] = (short) cst[opnum]; /* Sign extend. */
794 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
798 (data[len / 2 + 0] << 24) +
799 (data[len / 2 + 1] << 16) +
800 (data[len / 2 + 2] << 8) +
804 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
805 (looking_for & SIZE));
809 else if ((looking_for & SIZE) == L_16 ||
810 (looking_for & SIZE) == L_16U)
812 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
813 /* Immediates are always unsigned. */
814 if ((looking_for & SIZE) != L_16U &&
815 (looking_for & MODE) != IMM)
816 cst[opnum] = (short) cst[opnum]; /* Sign extend. */
818 else if (looking_for & ABSJMP)
820 switch (looking_for & SIZE) {
822 cst[opnum] = (data[1] << 16) | (data[2] << 8) | (data[3]);
826 (data[len / 2 + 0] << 24) +
827 (data[len / 2 + 1] << 16) +
828 (data[len / 2 + 2] << 8) +
832 printf ("decode: bad size ABSJMP: %d\n",
833 (looking_for & SIZE));
837 else if ((looking_for & MODE) == MEMIND)
839 cst[opnum] = data[1];
841 else if ((looking_for & MODE) == VECIND)
843 if(h8300_normal_mode)
844 cst[opnum] = ((data[1] & 0x7f) + 0x80) * 2;
846 cst[opnum] = ((data[1] & 0x7f) + 0x80) * 4;
847 cst[opnum] += h8_get_vbr (sd); /* Add vector base reg. */
849 else if ((looking_for & SIZE) == L_32)
854 (data[i + 0] << 24) |
855 (data[i + 1] << 16) |
859 else if ((looking_for & SIZE) == L_24)
864 (data[i + 0] << 16) |
868 else if (looking_for & DISPREG)
870 rdisp[opnum] = thisnib & 0x7;
872 else if ((looking_for & MODE) == KBIT)
889 else if ((looking_for & SIZE) == L_8)
891 if ((looking_for & MODE) == ABS)
893 /* Will be combined with contents of SBR_REGNUM
894 by fetch (). For all modes except h8sx, this
895 will always contain the value 0xFFFFFF00. */
896 cst[opnum] = data[len / 2] & 0xff;
900 cst[opnum] = data[len / 2] & 0xff;
903 else if ((looking_for & SIZE) == L_2)
905 cst[opnum] = thisnib & 3;
907 else if ((looking_for & SIZE) == L_3 ||
908 (looking_for & SIZE) == L_3NZ)
910 cst[opnum] = thisnib & 7;
911 if (cst[opnum] == 0 && (looking_for & SIZE) == L_3NZ)
914 else if ((looking_for & SIZE) == L_4)
916 cst[opnum] = thisnib & 15;
918 else if ((looking_for & SIZE) == L_5)
920 cst[opnum] = data[len / 2] & 0x1f;
922 else if (looking_for == E)
927 /* Fill in the args. */
929 const op_type *args = q->args.nib;
934 nargs < 3 && *args != E;
940 opnum = ((x & OP3) ? 2 :
949 if ((x & MODE) == IMM ||
950 (x & MODE) == KBIT ||
953 /* Use the instruction to determine
955 p->type = X (OP_IMM, OP_SIZE (q->how));
956 p->literal = cst[opnum];
958 else if ((x & MODE) == CONST_2 ||
959 (x & MODE) == CONST_4 ||
960 (x & MODE) == CONST_8 ||
961 (x & MODE) == CONST_16)
963 /* Use the instruction to determine
965 p->type = X (OP_IMM, OP_SIZE (q->how));
967 case CONST_2: p->literal = 2; break;
968 case CONST_4: p->literal = 4; break;
969 case CONST_8: p->literal = 8; break;
970 case CONST_16: p->literal = 16; break;
973 else if ((x & MODE) == REG)
975 p->type = X (OP_REG, bitfrom (x));
978 else if ((x & MODE) == LOWREG)
980 p->type = X (OP_LOWREG, bitfrom (x));
983 else if ((x & MODE) == PREINC)
985 /* Use the instruction to determine
987 p->type = X (OP_PREINC, OP_SIZE (q->how));
988 p->reg = reg[opnum] & 0x7;
990 else if ((x & MODE) == POSTINC)
992 /* Use the instruction to determine
994 p->type = X (OP_POSTINC, OP_SIZE (q->how));
995 p->reg = reg[opnum] & 0x7;
997 else if ((x & MODE) == PREDEC)
999 /* Use the instruction to determine
1000 the operand size. */
1001 p->type = X (OP_PREDEC, OP_SIZE (q->how));
1002 p->reg = reg[opnum] & 0x7;
1004 else if ((x & MODE) == POSTDEC)
1006 /* Use the instruction to determine
1007 the operand size. */
1008 p->type = X (OP_POSTDEC, OP_SIZE (q->how));
1009 p->reg = reg[opnum] & 0x7;
1011 else if ((x & MODE) == IND)
1013 /* Note: an indirect is transformed into
1014 a displacement of zero.
1016 /* Use the instruction to determine
1017 the operand size. */
1018 p->type = X (OP_DISP, OP_SIZE (q->how));
1019 p->reg = reg[opnum] & 0x7;
1021 if (OP_KIND (q->how) == O_JSR ||
1022 OP_KIND (q->how) == O_JMP)
1023 if (lvalue (sd, p->type, p->reg, (unsigned int *)&p->type))
1026 else if ((x & MODE) == ABS)
1028 /* Note: a 16 or 32 bit ABS is transformed into a
1029 displacement from pseudo-register ZERO_REGNUM,
1030 which is always zero. An 8 bit ABS becomes
1031 a displacement from SBR_REGNUM.
1033 /* Use the instruction to determine
1034 the operand size. */
1035 p->type = X (OP_DISP, OP_SIZE (q->how));
1036 p->literal = cst[opnum];
1038 /* 8-bit ABS is displacement from SBR.
1039 16 and 32-bit ABS are displacement from ZERO.
1040 (SBR will always be zero except for h8/sx)
1042 if ((x & SIZE) == L_8)
1043 p->reg = SBR_REGNUM;
1045 p->reg = ZERO_REGNUM;;
1047 else if ((x & MODE) == MEMIND ||
1048 (x & MODE) == VECIND)
1050 /* Size doesn't matter. */
1051 p->type = X (OP_MEM, SB);
1052 p->literal = cst[opnum];
1053 if (OP_KIND (q->how) == O_JSR ||
1054 OP_KIND (q->how) == O_JMP)
1055 if (lvalue (sd, p->type, p->reg, (unsigned int *)&p->type))
1058 else if ((x & MODE) == PCREL)
1060 /* Size doesn't matter. */
1061 p->type = X (OP_PCREL, SB);
1062 p->literal = cst[opnum];
1064 else if (x & ABSJMP)
1066 p->type = X (OP_IMM, SP);
1067 p->literal = cst[opnum];
1069 else if ((x & MODE) == INDEXB)
1071 p->type = X (OP_INDEXB, OP_SIZE (q->how));
1072 p->literal = cst[opnum];
1073 p->reg = rdisp[opnum];
1075 else if ((x & MODE) == INDEXW)
1077 p->type = X (OP_INDEXW, OP_SIZE (q->how));
1078 p->literal = cst[opnum];
1079 p->reg = rdisp[opnum];
1081 else if ((x & MODE) == INDEXL)
1083 p->type = X (OP_INDEXL, OP_SIZE (q->how));
1084 p->literal = cst[opnum];
1085 p->reg = rdisp[opnum];
1087 else if ((x & MODE) == DISP)
1089 /* Yuck -- special for mova args. */
1090 if (strncmp (q->name, "mova", 4) == 0 &&
1093 /* Mova can have a DISP2 dest, with an
1094 INDEXB or INDEXW src. The multiplier
1095 for the displacement value is determined
1096 by the src operand, not by the insn. */
1098 switch (OP_KIND (dst->src.type))
1101 p->type = X (OP_DISP, SB);
1102 p->literal = cst[opnum];
1105 p->type = X (OP_DISP, SW);
1106 p->literal = cst[opnum] * 2;
1114 p->type = X (OP_DISP, OP_SIZE (q->how));
1115 p->literal = cst[opnum];
1116 /* DISP2 is special. */
1117 if ((x & SIZE) == L_2)
1118 switch (OP_SIZE (q->how))
1121 case SW: p->literal *= 2; break;
1122 case SL: p->literal *= 4; break;
1125 p->reg = rdisp[opnum];
1132 p->type = X (OP_CCR, SB);
1135 p->type = X (OP_EXR, SB);
1138 p->type = X (OP_MACH, SL);
1141 p->type = X (OP_MACL, SL);
1144 p->type = X (OP_VBR, SL);
1147 p->type = X (OP_SBR, SL);
1151 else if ((x & MODE) == CCR)
1155 else if ((x & MODE) == EXR)
1160 printf ("Hmmmm 0x%x...\n", x);
1166 /* Unary operators: treat src and dst as equivalent. */
1167 if (dst->dst.type == -1)
1168 dst->dst = dst->src;
1169 if (dst->src.type == -1)
1170 dst->src = dst->dst;
1172 dst->opcode = q->how;
1173 dst->cycles = q->time;
1175 /* And jsr's to these locations are turned into
1178 if (OP_KIND (dst->opcode) == O_JSR)
1180 switch (dst->src.literal)
1183 dst->opcode = O (O_SYS_OPEN, SB);
1186 dst->opcode = O (O_SYS_READ, SB);
1189 dst->opcode = O (O_SYS_WRITE, SB);
1192 dst->opcode = O (O_SYS_LSEEK, SB);
1195 dst->opcode = O (O_SYS_CLOSE, SB);
1198 dst->opcode = O (O_SYS_STAT, SB);
1201 dst->opcode = O (O_SYS_FSTAT, SB);
1204 dst->opcode = O (O_SYS_CMDLINE, SB);
1207 /* End of Processing for system calls. */
1210 dst->next_pc = addr + len / 2;
1214 printf ("Don't understand 0x%x \n", looking_for);
1225 /* Fell off the end. */
1226 dst->opcode = O (O_ILL, SB);
1230 compile (SIM_DESC sd, int pc)
1234 /* Find the next cache entry to use. */
1235 idx = h8_get_cache_top (sd) + 1;
1236 h8_increment_compiles (sd);
1237 if (idx >= sd->sim_cache_size)
1241 h8_set_cache_top (sd, idx);
1243 /* Throw away its old meaning. */
1244 h8_set_cache_idx (sd, sd->sim_cache[idx].oldpc, 0);
1246 /* Set to new address. */
1247 sd->sim_cache[idx].oldpc = pc;
1249 /* Fill in instruction info. */
1250 decode (sd, pc, h8_get_memory_buf (sd) + pc, sd->sim_cache + idx);
1252 /* Point to new cache entry. */
1253 h8_set_cache_idx (sd, pc, idx);
1257 static unsigned char *breg[32];
1258 static unsigned short *wreg[16];
1259 static unsigned int *lreg[18];
1261 #define GET_B_REG(X) *(breg[X])
1262 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1263 #define GET_W_REG(X) *(wreg[X])
1264 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1265 #define GET_L_REG(X) h8_get_reg (sd, X)
1266 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1268 #define GET_MEMORY_L(X) \
1269 ((X) < memory_size \
1270 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1271 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1272 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 24) \
1273 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 16) \
1274 | (h8_get_eightbit (sd, ((X)+2) & 0xff) << 8) \
1275 | (h8_get_eightbit (sd, ((X)+3) & 0xff) << 0)))
1277 #define GET_MEMORY_W(X) \
1278 ((X) < memory_size \
1279 ? ((h8_get_memory (sd, (X)+0) << 8) \
1280 | (h8_get_memory (sd, (X)+1) << 0)) \
1281 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 8) \
1282 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 0)))
1285 #define GET_MEMORY_B(X) \
1286 ((X) < memory_size ? (h8_get_memory (sd, (X))) \
1287 : (h8_get_eightbit (sd, (X) & 0xff)))
1289 #define SET_MEMORY_L(X, Y) \
1290 { register unsigned char *_p; register int __y = (Y); \
1291 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1292 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1293 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1294 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1297 #define SET_MEMORY_W(X, Y) \
1298 { register unsigned char *_p; register int __y = (Y); \
1299 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1300 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1301 _p[0] = __y >> 8; _p[1] = __y; \
1304 #define SET_MEMORY_B(X, Y) \
1305 ((X) < memory_size ? (h8_set_memory (sd, (X), (Y))) \
1306 : (h8_set_eightbit (sd, (X) & 0xff, (Y))))
1308 /* Simulate a memory fetch.
1309 Return 0 for success, -1 for failure.
1313 fetch_1 (SIM_DESC sd, ea_type *arg, int *val, int twice)
1316 int abs = arg->literal;
1321 return -1; /* Paranoia. */
1325 /* Indexed register plus displacement mode:
1327 This new family of addressing modes are similar to OP_DISP
1328 (register plus displacement), with two differences:
1329 1) INDEXB uses only the least significant byte of the register,
1330 INDEXW uses only the least significant word, and
1331 INDEXL uses the entire register (just like OP_DISP).
1333 2) The displacement value in abs is multiplied by two
1334 for SW-sized operations, and by four for SL-size.
1336 This gives nine possible variations.
1339 case X (OP_INDEXB, SB):
1340 case X (OP_INDEXB, SW):
1341 case X (OP_INDEXB, SL):
1342 case X (OP_INDEXW, SB):
1343 case X (OP_INDEXW, SW):
1344 case X (OP_INDEXW, SL):
1345 case X (OP_INDEXL, SB):
1346 case X (OP_INDEXL, SW):
1347 case X (OP_INDEXL, SL):
1349 switch (OP_KIND (arg->type)) {
1350 case OP_INDEXB: t &= 0xff; break;
1351 case OP_INDEXW: t &= 0xffff; break;
1355 switch (OP_SIZE (arg->type)) {
1357 *val = GET_MEMORY_B ((t * 1 + abs) & h8_get_mask (sd));
1360 *val = GET_MEMORY_W ((t * 2 + abs) & h8_get_mask (sd));
1363 *val = GET_MEMORY_L ((t * 4 + abs) & h8_get_mask (sd));
1368 case X (OP_LOWREG, SB):
1369 *val = GET_L_REG (rn) & 0xff;
1371 case X (OP_LOWREG, SW):
1372 *val = GET_L_REG (rn) & 0xffff;
1375 case X (OP_REG, SB): /* Register direct, byte. */
1376 *val = GET_B_REG (rn);
1378 case X (OP_REG, SW): /* Register direct, word. */
1379 *val = GET_W_REG (rn);
1381 case X (OP_REG, SL): /* Register direct, long. */
1382 *val = GET_L_REG (rn);
1384 case X (OP_IMM, SB): /* Immediate, byte. */
1385 case X (OP_IMM, SW): /* Immediate, word. */
1386 case X (OP_IMM, SL): /* Immediate, long. */
1389 case X (OP_POSTINC, SB): /* Register indirect w/post-incr: byte. */
1391 r = GET_MEMORY_B (t & h8_get_mask (sd));
1397 case X (OP_POSTINC, SW): /* Register indirect w/post-incr: word. */
1399 r = GET_MEMORY_W (t & h8_get_mask (sd));
1405 case X (OP_POSTINC, SL): /* Register indirect w/post-incr: long. */
1407 r = GET_MEMORY_L (t & h8_get_mask (sd));
1414 case X (OP_POSTDEC, SB): /* Register indirect w/post-decr: byte. */
1416 r = GET_MEMORY_B (t & h8_get_mask (sd));
1422 case X (OP_POSTDEC, SW): /* Register indirect w/post-decr: word. */
1424 r = GET_MEMORY_W (t & h8_get_mask (sd));
1430 case X (OP_POSTDEC, SL): /* Register indirect w/post-decr: long. */
1432 r = GET_MEMORY_L (t & h8_get_mask (sd));
1439 case X (OP_PREDEC, SB): /* Register indirect w/pre-decr: byte. */
1440 t = GET_L_REG (rn) - 1;
1442 t &= h8_get_mask (sd);
1443 *val = GET_MEMORY_B (t);
1446 case X (OP_PREDEC, SW): /* Register indirect w/pre-decr: word. */
1447 t = GET_L_REG (rn) - 2;
1449 t &= h8_get_mask (sd);
1450 *val = GET_MEMORY_W (t);
1453 case X (OP_PREDEC, SL): /* Register indirect w/pre-decr: long. */
1454 t = GET_L_REG (rn) - 4;
1456 t &= h8_get_mask (sd);
1457 *val = GET_MEMORY_L (t);
1460 case X (OP_PREINC, SB): /* Register indirect w/pre-incr: byte. */
1461 t = GET_L_REG (rn) + 1;
1463 t &= h8_get_mask (sd);
1464 *val = GET_MEMORY_B (t);
1467 case X (OP_PREINC, SW): /* Register indirect w/pre-incr: long. */
1468 t = GET_L_REG (rn) + 2;
1470 t &= h8_get_mask (sd);
1471 *val = GET_MEMORY_W (t);
1474 case X (OP_PREINC, SL): /* Register indirect w/pre-incr: long. */
1475 t = GET_L_REG (rn) + 4;
1477 t &= h8_get_mask (sd);
1478 *val = GET_MEMORY_L (t);
1481 case X (OP_DISP, SB): /* Register indirect w/displacement: byte. */
1482 t = GET_L_REG (rn) + abs;
1483 t &= h8_get_mask (sd);
1484 *val = GET_MEMORY_B (t);
1487 case X (OP_DISP, SW): /* Register indirect w/displacement: word. */
1488 t = GET_L_REG (rn) + abs;
1489 t &= h8_get_mask (sd);
1490 *val = GET_MEMORY_W (t);
1493 case X (OP_DISP, SL): /* Register indirect w/displacement: long. */
1494 t = GET_L_REG (rn) + abs;
1495 t &= h8_get_mask (sd);
1496 *val =GET_MEMORY_L (t);
1499 case X (OP_MEM, SL): /* Absolute memory address, long. */
1500 t = GET_MEMORY_L (abs);
1501 t &= h8_get_mask (sd);
1505 case X (OP_MEM, SW): /* Absolute memory address, word. */
1506 t = GET_MEMORY_W (abs);
1507 t &= h8_get_mask (sd);
1511 case X (OP_PCREL, SB): /* PC relative (for jump, branch etc). */
1512 case X (OP_PCREL, SW):
1513 case X (OP_PCREL, SL):
1514 case X (OP_PCREL, SN):
1518 case X (OP_MEM, SB): /* Why isn't this implemented? */
1520 sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
1523 return 0; /* Success. */
1529 fetch (SIM_DESC sd, ea_type *arg, int *val)
1531 return fetch_1 (sd, arg, val, 0);
1534 /* Fetch which will be followed by a store to the same location.
1535 The difference being that we don't want to do a post-increment
1536 or post-decrement at this time: we'll do it when we store. */
1539 fetch2 (SIM_DESC sd, ea_type *arg, int *val)
1541 return fetch_1 (sd, arg, val, 1);
1544 /* Simulate a memory store.
1545 Return 0 for success, -1 for failure.
1549 store_1 (SIM_DESC sd, ea_type *arg, int n, int twice)
1552 int abs = arg->literal;
1557 /* Indexed register plus displacement mode:
1559 This new family of addressing modes are similar to OP_DISP
1560 (register plus displacement), with two differences:
1561 1) INDEXB uses only the least significant byte of the register,
1562 INDEXW uses only the least significant word, and
1563 INDEXL uses the entire register (just like OP_DISP).
1565 2) The displacement value in abs is multiplied by two
1566 for SW-sized operations, and by four for SL-size.
1568 This gives nine possible variations.
1571 case X (OP_INDEXB, SB):
1572 case X (OP_INDEXB, SW):
1573 case X (OP_INDEXB, SL):
1574 case X (OP_INDEXW, SB):
1575 case X (OP_INDEXW, SW):
1576 case X (OP_INDEXW, SL):
1577 case X (OP_INDEXL, SB):
1578 case X (OP_INDEXL, SW):
1579 case X (OP_INDEXL, SL):
1581 switch (OP_KIND (arg->type)) {
1582 case OP_INDEXB: t &= 0xff; break;
1583 case OP_INDEXW: t &= 0xffff; break;
1587 switch (OP_SIZE (arg->type)) {
1589 SET_MEMORY_B ((t * 1 + abs) & h8_get_mask (sd), n);
1592 SET_MEMORY_W ((t * 2 + abs) & h8_get_mask (sd), n);
1595 SET_MEMORY_L ((t * 4 + abs) & h8_get_mask (sd), n);
1600 case X (OP_REG, SB): /* Register direct, byte. */
1603 case X (OP_REG, SW): /* Register direct, word. */
1606 case X (OP_REG, SL): /* Register direct, long. */
1610 case X (OP_PREDEC, SB): /* Register indirect w/pre-decr, byte. */
1615 t &= h8_get_mask (sd);
1616 SET_MEMORY_B (t, n);
1619 case X (OP_PREDEC, SW): /* Register indirect w/pre-decr, word. */
1624 t &= h8_get_mask (sd);
1625 SET_MEMORY_W (t, n);
1628 case X (OP_PREDEC, SL): /* Register indirect w/pre-decr, long. */
1633 t &= h8_get_mask (sd);
1634 SET_MEMORY_L (t, n);
1637 case X (OP_PREINC, SB): /* Register indirect w/pre-incr, byte. */
1642 t &= h8_get_mask (sd);
1643 SET_MEMORY_B (t, n);
1646 case X (OP_PREINC, SW): /* Register indirect w/pre-incr, word. */
1651 t &= h8_get_mask (sd);
1652 SET_MEMORY_W (t, n);
1655 case X (OP_PREINC, SL): /* Register indirect w/pre-incr, long. */
1660 t &= h8_get_mask (sd);
1661 SET_MEMORY_L (t, n);
1664 case X (OP_POSTDEC, SB): /* Register indirect w/post-decr, byte. */
1666 SET_L_REG (rn, t - 1);
1667 t &= h8_get_mask (sd);
1668 SET_MEMORY_B (t, n);
1671 case X (OP_POSTDEC, SW): /* Register indirect w/post-decr, word. */
1673 SET_L_REG (rn, t - 2);
1674 t &= h8_get_mask (sd);
1675 SET_MEMORY_W (t, n);
1678 case X (OP_POSTDEC, SL): /* Register indirect w/post-decr, long. */
1680 SET_L_REG (rn, t - 4);
1681 t &= h8_get_mask (sd);
1682 SET_MEMORY_L (t, n);
1685 case X (OP_POSTINC, SB): /* Register indirect w/post-incr, byte. */
1687 SET_L_REG (rn, t + 1);
1688 t &= h8_get_mask (sd);
1689 SET_MEMORY_B (t, n);
1692 case X (OP_POSTINC, SW): /* Register indirect w/post-incr, word. */
1694 SET_L_REG (rn, t + 2);
1695 t &= h8_get_mask (sd);
1696 SET_MEMORY_W (t, n);
1699 case X (OP_POSTINC, SL): /* Register indirect w/post-incr, long. */
1701 SET_L_REG (rn, t + 4);
1702 t &= h8_get_mask (sd);
1703 SET_MEMORY_L (t, n);
1706 case X (OP_DISP, SB): /* Register indirect w/displacement, byte. */
1707 t = GET_L_REG (rn) + abs;
1708 t &= h8_get_mask (sd);
1709 SET_MEMORY_B (t, n);
1712 case X (OP_DISP, SW): /* Register indirect w/displacement, word. */
1713 t = GET_L_REG (rn) + abs;
1714 t &= h8_get_mask (sd);
1715 SET_MEMORY_W (t, n);
1718 case X (OP_DISP, SL): /* Register indirect w/displacement, long. */
1719 t = GET_L_REG (rn) + abs;
1720 t &= h8_get_mask (sd);
1721 SET_MEMORY_L (t, n);
1725 case X (OP_MEM, SB): /* Why isn't this implemented? */
1726 case X (OP_MEM, SW): /* Why isn't this implemented? */
1727 case X (OP_MEM, SL): /* Why isn't this implemented? */
1729 sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
1738 store (SIM_DESC sd, ea_type *arg, int n)
1740 return store_1 (sd, arg, n, 0);
1743 /* Store which follows a fetch from the same location.
1744 The difference being that we don't want to do a pre-increment
1745 or pre-decrement at this time: it was already done when we fetched. */
1748 store2 (SIM_DESC sd, ea_type *arg, int n)
1750 return store_1 (sd, arg, n, 1);
1764 /* Flag to be set whenever a new SIM_DESC object is created. */
1765 static int init_pointers_needed = 1;
1768 init_pointers (SIM_DESC sd)
1770 if (init_pointers_needed)
1776 if (h8300smode && !h8300_normal_mode)
1777 memory_size = H8300S_MSIZE;
1778 else if (h8300hmode && !h8300_normal_mode)
1779 memory_size = H8300H_MSIZE;
1781 memory_size = H8300_MSIZE;
1782 /* `msize' must be a power of two. */
1783 if ((memory_size & (memory_size - 1)) != 0)
1785 (*sim_callback->printf_filtered)
1787 "init_pointers: bad memory size %d, defaulting to %d.\n",
1788 memory_size, memory_size = H8300S_MSIZE);
1791 if (h8_get_memory_buf (sd))
1792 free (h8_get_memory_buf (sd));
1793 if (h8_get_cache_idx_buf (sd))
1794 free (h8_get_cache_idx_buf (sd));
1795 if (h8_get_eightbit_buf (sd))
1796 free (h8_get_eightbit_buf (sd));
1798 h8_set_memory_buf (sd, (unsigned char *)
1799 calloc (sizeof (char), memory_size));
1800 h8_set_cache_idx_buf (sd, (unsigned short *)
1801 calloc (sizeof (short), memory_size));
1802 sd->memory_size = memory_size;
1803 h8_set_eightbit_buf (sd, (unsigned char *) calloc (sizeof (char), 256));
1805 h8_set_mask (sd, memory_size - 1);
1807 memset (h8_get_reg_buf (sd), 0, sizeof (((STATE_CPU (sd, 0))->regs)));
1809 for (i = 0; i < 8; i++)
1811 /* FIXME: rewrite using local buffer. */
1812 unsigned char *p = (unsigned char *) (h8_get_reg_buf (sd) + i);
1813 unsigned char *e = (unsigned char *) (h8_get_reg_buf (sd) + i + 1);
1814 unsigned short *q = (unsigned short *) (h8_get_reg_buf (sd) + i);
1815 unsigned short *u = (unsigned short *) (h8_get_reg_buf (sd) + i + 1);
1816 h8_set_reg (sd, i, 0x00112233);
1831 wreg[i] = wreg[i + 8] = 0;
1845 if (wreg[i] == 0 || wreg[i + 8] == 0)
1846 (*sim_callback->printf_filtered) (sim_callback,
1847 "init_pointers: internal error.\n");
1849 h8_set_reg (sd, i, 0);
1850 lreg[i] = h8_get_reg_buf (sd) + i;
1853 /* Note: sim uses pseudo-register ZERO as a zero register. */
1854 lreg[ZERO_REGNUM] = h8_get_reg_buf (sd) + ZERO_REGNUM;
1855 init_pointers_needed = 0;
1857 /* Initialize the seg registers. */
1859 set_simcache_size (sd, CSIZE);
1864 sim_stop (SIM_DESC sd)
1866 /* FIXME: use a real signal value. */
1867 sim_engine_set_run_state (sd, sim_stopped, SIGINT);
1871 #define OBITOP(name, f, s, op) \
1872 case O (name, SB): \
1877 if (fetch (sd, &code->dst, &ea)) \
1879 if (fetch (sd, &code->src, &tmp)) \
1881 m = 1 << (tmp & 7); \
1884 if (store (sd, &code->dst,ea)) \
1890 sim_resume (SIM_DESC sd, int step, int siggnal)
1895 int tick_start = get_now ();
1903 int c, nz, v, n, u, h, ui, intMaskBit;
1906 enum sim_stop reason;
1913 sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
1917 sim_engine_set_run_state (sd, sim_running, 0);
1920 pc = h8_get_pc (sd);
1922 /* The PC should never be odd. */
1925 sim_engine_set_run_state (sd, sim_stopped, SIGBUS);
1929 /* Get Status Register (flags). */
1932 if (h8300smode) /* Get exr. */
1934 trace = (h8_get_exr (sd) >> 7) & 1;
1935 intMask = h8_get_exr (sd) & 7;
1938 oldmask = h8_get_mask (sd);
1939 if (!h8300hmode || h8300_normal_mode)
1940 h8_set_mask (sd, 0xffff);
1943 unsigned short cidx;
1947 cidx = h8_get_cache_idx (sd, pc);
1948 if (cidx == (unsigned short) -1 ||
1949 cidx >= sd->sim_cache_size)
1952 code = sd->sim_cache + cidx;
1957 printf ("%x %d %s\n", pc, code->opcode,
1958 code->op ? code->op->name : "**");
1960 h8_increment_stats (sd, code->opcode);
1965 cycles += code->cycles;
1969 switch (code->opcode)
1973 * This opcode is a fake for when we get to an
1974 * instruction which hasnt been compiled
1980 case O (O_MOVAB, SL):
1981 case O (O_MOVAW, SL):
1982 case O (O_MOVAL, SL):
1983 /* 1) Evaluate 2nd argument (dst).
1984 2) Mask / zero extend according to whether 1st argument (src)
1985 is INDEXB, INDEXW, or INDEXL.
1986 3) Left-shift the result by 0, 1 or 2, according to size of mova
1987 (mova/b, mova/w, mova/l).
1988 4) Add literal value of 1st argument (src).
1989 5) Store result in 3rd argument (op3).
1992 /* Alas, since this is the only instruction with 3 arguments,
1993 decode doesn't handle them very well. Some fix-up is required.
1995 a) The size of dst is determined by whether src is
1996 INDEXB or INDEXW. */
1998 if (OP_KIND (code->src.type) == OP_INDEXB)
1999 code->dst.type = X (OP_KIND (code->dst.type), SB);
2000 else if (OP_KIND (code->src.type) == OP_INDEXW)
2001 code->dst.type = X (OP_KIND (code->dst.type), SW);
2003 /* b) If op3 == null, then this is the short form of the insn.
2004 Dst is the dispreg of src, and op3 is the 32-bit form
2005 of the same register.
2008 if (code->op3.type == 0)
2010 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
2011 We get to compose dst and op3 as follows:
2013 op3 is a 32-bit register, ID == src.reg.
2014 dst is the same register, but 8 or 16 bits
2015 depending on whether src is INDEXB or INDEXW.
2018 code->op3.type = X (OP_REG, SL);
2019 code->op3.reg = code->src.reg;
2020 code->op3.literal = 0;
2022 if (OP_KIND (code->src.type) == OP_INDEXB)
2024 code->dst.type = X (OP_REG, SB);
2025 code->dst.reg = code->op3.reg + 8;
2028 code->dst.type = X (OP_REG, SW);
2031 if (fetch (sd, &code->dst, &ea))
2034 switch (OP_KIND (code->src.type)) {
2035 case OP_INDEXB: ea = ea & 0xff; break;
2036 case OP_INDEXW: ea = ea & 0xffff; break;
2037 case OP_INDEXL: break;
2038 default: goto illegal;
2041 switch (code->opcode) {
2042 case O (O_MOVAB, SL): break;
2043 case O (O_MOVAW, SL): ea = ea << 1; break;
2044 case O (O_MOVAL, SL): ea = ea << 2; break;
2045 default: goto illegal;
2048 ea = ea + code->src.literal;
2050 if (store (sd, &code->op3, ea))
2055 case O (O_SUBX, SB): /* subx, extended sub */
2056 if (fetch2 (sd, &code->dst, &rd))
2058 if (fetch (sd, &code->src, &ea))
2064 case O (O_SUBX, SW): /* subx, extended sub */
2065 if (fetch2 (sd, &code->dst, &rd))
2067 if (fetch (sd, &code->src, &ea))
2073 case O (O_SUBX, SL): /* subx, extended sub */
2074 if (fetch2 (sd, &code->dst, &rd))
2076 if (fetch (sd, &code->src, &ea))
2082 case O (O_ADDX, SB): /* addx, extended add */
2083 if (fetch2 (sd, &code->dst, &rd))
2085 if (fetch (sd, &code->src, &ea))
2091 case O (O_ADDX, SW): /* addx, extended add */
2092 if (fetch2 (sd, &code->dst, &rd))
2094 if (fetch (sd, &code->src, &ea))
2100 case O (O_ADDX, SL): /* addx, extended add */
2101 if (fetch2 (sd, &code->dst, &rd))
2103 if (fetch (sd, &code->src, &ea))
2109 case O (O_SUB, SB): /* sub.b */
2110 /* Fetch rd and ea. */
2111 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2117 case O (O_SUB, SW): /* sub.w */
2118 /* Fetch rd and ea. */
2119 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2125 case O (O_SUB, SL): /* sub.l */
2126 /* Fetch rd and ea. */
2127 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2133 case O (O_NEG, SB): /* neg.b */
2135 if (fetch2 (sd, &code->src, &ea))
2142 case O (O_NEG, SW): /* neg.w */
2144 if (fetch2 (sd, &code->src, &ea))
2151 case O (O_NEG, SL): /* neg.l */
2153 if (fetch2 (sd, &code->src, &ea))
2160 case O (O_ADD, SB): /* add.b */
2161 if (fetch2 (sd, &code->dst, &rd))
2163 if (fetch (sd, &code->src, &ea))
2168 case O (O_ADD, SW): /* add.w */
2169 if (fetch2 (sd, &code->dst, &rd))
2171 if (fetch (sd, &code->src, &ea))
2176 case O (O_ADD, SL): /* add.l */
2177 if (fetch2 (sd, &code->dst, &rd))
2179 if (fetch (sd, &code->src, &ea))
2184 case O (O_AND, SB): /* and.b */
2185 /* Fetch rd and ea. */
2186 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2191 case O (O_AND, SW): /* and.w */
2192 /* Fetch rd and ea. */
2193 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2198 case O (O_AND, SL): /* and.l */
2199 /* Fetch rd and ea. */
2200 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2205 case O (O_OR, SB): /* or.b */
2206 /* Fetch rd and ea. */
2207 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2212 case O (O_OR, SW): /* or.w */
2213 /* Fetch rd and ea. */
2214 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2219 case O (O_OR, SL): /* or.l */
2220 /* Fetch rd and ea. */
2221 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2226 case O (O_XOR, SB): /* xor.b */
2227 /* Fetch rd and ea. */
2228 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2233 case O (O_XOR, SW): /* xor.w */
2234 /* Fetch rd and ea. */
2235 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2240 case O (O_XOR, SL): /* xor.l */
2241 /* Fetch rd and ea. */
2242 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2248 if (fetch (sd, &code->src, &res))
2250 if (store (sd, &code->dst, res))
2252 goto just_flags_log8;
2254 if (fetch (sd, &code->src, &res))
2256 if (store (sd, &code->dst, res))
2258 goto just_flags_log16;
2260 if (fetch (sd, &code->src, &res))
2262 if (store (sd, &code->dst, res))
2264 goto just_flags_log32;
2266 case O (O_MOVMD, SB): /* movmd.b */
2273 rd = GET_MEMORY_B (GET_L_REG (5));
2274 SET_MEMORY_B (GET_L_REG (6), rd);
2275 SET_L_REG (5, GET_L_REG (5) + 1);
2276 SET_L_REG (6, GET_L_REG (6) + 1);
2281 case O (O_MOVMD, SW): /* movmd.w */
2288 rd = GET_MEMORY_W (GET_L_REG (5));
2289 SET_MEMORY_W (GET_L_REG (6), rd);
2290 SET_L_REG (5, GET_L_REG (5) + 2);
2291 SET_L_REG (6, GET_L_REG (6) + 2);
2296 case O (O_MOVMD, SL): /* movmd.l */
2303 rd = GET_MEMORY_L (GET_L_REG (5));
2304 SET_MEMORY_L (GET_L_REG (6), rd);
2305 SET_L_REG (5, GET_L_REG (5) + 4);
2306 SET_L_REG (6, GET_L_REG (6) + 4);
2311 case O (O_MOVSD, SB): /* movsd.b */
2312 /* This instruction implements strncpy, with a conditional branch.
2313 r4 contains n, r5 contains src, and r6 contains dst.
2314 The 16-bit displacement operand is added to the pc
2315 if and only if the end of string is reached before
2316 n bytes are transferred. */
2318 ea = GET_L_REG (4) & 0xffff;
2324 rd = GET_MEMORY_B (GET_L_REG (5));
2325 SET_MEMORY_B (GET_L_REG (6), rd);
2326 SET_L_REG (5, GET_L_REG (5) + 1);
2327 SET_L_REG (6, GET_L_REG (6) + 1);
2334 case O (O_EEPMOV, SB): /* eepmov.b */
2335 case O (O_EEPMOV, SW): /* eepmov.w */
2336 if (h8300hmode || h8300smode)
2338 register unsigned char *_src, *_dst;
2339 unsigned int count = ((code->opcode == O (O_EEPMOV, SW))
2340 ? h8_get_reg (sd, R4_REGNUM) & 0xffff
2341 : h8_get_reg (sd, R4_REGNUM) & 0xff);
2343 _src = (h8_get_reg (sd, R5_REGNUM) < memory_size
2344 ? h8_get_memory_buf (sd) + h8_get_reg (sd, R5_REGNUM)
2345 : h8_get_eightbit_buf (sd) +
2346 (h8_get_reg (sd, R5_REGNUM) & 0xff));
2347 if ((_src + count) >= (h8_get_memory_buf (sd) + memory_size))
2349 if ((_src + count) >= (h8_get_eightbit_buf (sd) + 0x100))
2352 _dst = (h8_get_reg (sd, R6_REGNUM) < memory_size
2353 ? h8_get_memory_buf (sd) + h8_get_reg (sd, R6_REGNUM)
2354 : h8_get_eightbit_buf (sd) +
2355 (h8_get_reg (sd, R6_REGNUM) & 0xff));
2357 if ((_dst + count) >= (h8_get_memory_buf (sd) + memory_size))
2359 if ((_dst + count) >= (h8_get_eightbit_buf (sd) + 0x100))
2362 memcpy (_dst, _src, count);
2364 h8_set_reg (sd, R5_REGNUM, h8_get_reg (sd, R5_REGNUM) + count);
2365 h8_set_reg (sd, R6_REGNUM, h8_get_reg (sd, R6_REGNUM) + count);
2366 h8_set_reg (sd, R4_REGNUM, h8_get_reg (sd, R4_REGNUM) &
2367 ((code->opcode == O (O_EEPMOV, SW))
2368 ? (~0xffff) : (~0xff)));
2369 cycles += 2 * count;
2374 case O (O_ADDS, SL): /* adds (.l) */
2376 * This insn only uses register operands, but still
2377 * it would be cleaner to use fetch and store... */
2378 SET_L_REG (code->dst.reg,
2379 GET_L_REG (code->dst.reg)
2380 + code->src.literal);
2384 case O (O_SUBS, SL): /* subs (.l) */
2386 * This insn only uses register operands, but still
2387 * it would be cleaner to use fetch and store... */
2388 SET_L_REG (code->dst.reg,
2389 GET_L_REG (code->dst.reg)
2390 - code->src.literal);
2393 case O (O_CMP, SB): /* cmp.b */
2394 if (fetch (sd, &code->dst, &rd))
2396 if (fetch (sd, &code->src, &ea))
2400 goto just_flags_alu8;
2402 case O (O_CMP, SW): /* cmp.w */
2403 if (fetch (sd, &code->dst, &rd))
2405 if (fetch (sd, &code->src, &ea))
2409 goto just_flags_alu16;
2411 case O (O_CMP, SL): /* cmp.l */
2412 if (fetch (sd, &code->dst, &rd))
2414 if (fetch (sd, &code->src, &ea))
2418 goto just_flags_alu32;
2420 case O (O_DEC, SB): /* dec.b */
2422 * This insn only uses register operands, but still
2423 * it would be cleaner to use fetch and store... */
2424 rd = GET_B_REG (code->src.reg);
2427 SET_B_REG (code->src.reg, res);
2428 goto just_flags_inc8;
2430 case O (O_DEC, SW): /* dec.w */
2432 * This insn only uses register operands, but still
2433 * it would be cleaner to use fetch and store... */
2434 rd = GET_W_REG (code->dst.reg);
2435 ea = -code->src.literal;
2437 SET_W_REG (code->dst.reg, res);
2438 goto just_flags_inc16;
2440 case O (O_DEC, SL): /* dec.l */
2442 * This insn only uses register operands, but still
2443 * it would be cleaner to use fetch and store... */
2444 rd = GET_L_REG (code->dst.reg);
2445 ea = -code->src.literal;
2447 SET_L_REG (code->dst.reg, res);
2448 goto just_flags_inc32;
2450 case O (O_INC, SB): /* inc.b */
2452 * This insn only uses register operands, but still
2453 * it would be cleaner to use fetch and store... */
2454 rd = GET_B_REG (code->src.reg);
2457 SET_B_REG (code->src.reg, res);
2458 goto just_flags_inc8;
2460 case O (O_INC, SW): /* inc.w */
2462 * This insn only uses register operands, but still
2463 * it would be cleaner to use fetch and store... */
2464 rd = GET_W_REG (code->dst.reg);
2465 ea = code->src.literal;
2467 SET_W_REG (code->dst.reg, res);
2468 goto just_flags_inc16;
2470 case O (O_INC, SL): /* inc.l */
2472 * This insn only uses register operands, but still
2473 * it would be cleaner to use fetch and store... */
2474 rd = GET_L_REG (code->dst.reg);
2475 ea = code->src.literal;
2477 SET_L_REG (code->dst.reg, res);
2478 goto just_flags_inc32;
2480 case O (O_LDC, SB): /* ldc.b */
2481 if (fetch (sd, &code->src, &res))
2485 case O (O_LDC, SW): /* ldc.w */
2486 if (fetch (sd, &code->src, &res))
2489 /* Word operand, value from MSB, must be shifted. */
2493 case O (O_LDC, SL): /* ldc.l */
2494 if (fetch (sd, &code->src, &res))
2496 switch (code->dst.type) {
2497 case X (OP_SBR, SL):
2498 h8_set_sbr (sd, res);
2500 case X (OP_VBR, SL):
2501 h8_set_vbr (sd, res);
2508 case O (O_STC, SW): /* stc.w */
2509 case O (O_STC, SB): /* stc.b */
2510 if (code->src.type == X (OP_CCR, SB))
2513 res = h8_get_ccr (sd);
2515 else if (code->src.type == X (OP_EXR, SB) && h8300smode)
2518 h8_set_exr (sd, (trace << 7) | intMask);
2519 res = h8_get_exr (sd);
2524 /* Word operand, value to MSB, must be shifted. */
2525 if (code->opcode == X (O_STC, SW))
2527 if (store (sd, &code->dst, res))
2530 case O (O_STC, SL): /* stc.l */
2531 switch (code->src.type) {
2532 case X (OP_SBR, SL):
2533 res = h8_get_sbr (sd);
2535 case X (OP_VBR, SL):
2536 res = h8_get_vbr (sd);
2541 if (store (sd, &code->dst, res))
2545 case O (O_ANDC, SB): /* andc.b */
2546 if (code->dst.type == X (OP_CCR, SB))
2549 rd = h8_get_ccr (sd);
2551 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2554 h8_set_exr (sd, (trace << 7) | intMask);
2555 rd = h8_get_exr (sd);
2559 ea = code->src.literal;
2563 case O (O_ORC, SB): /* orc.b */
2564 if (code->dst.type == X (OP_CCR, SB))
2567 rd = h8_get_ccr (sd);
2569 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2572 h8_set_exr (sd, (trace << 7) | intMask);
2573 rd = h8_get_exr (sd);
2577 ea = code->src.literal;
2581 case O (O_XORC, SB): /* xorc.b */
2582 if (code->dst.type == X (OP_CCR, SB))
2585 rd = h8_get_ccr (sd);
2587 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2590 h8_set_exr (sd, (trace << 7) | intMask);
2591 rd = h8_get_exr (sd);
2595 ea = code->src.literal;
2599 case O (O_BRAS, SB): /* bra/s */
2600 /* This is basically an ordinary branch, with a delay slot. */
2601 if (fetch (sd, &code->src, &res))
2609 /* Execution continues at next instruction, but
2610 delayed_branch is set up for next cycle. */
2611 h8_set_delayed_branch (sd, code->next_pc + res);
2615 case O (O_BRAB, SB): /* bra rd.b */
2616 case O (O_BRAW, SW): /* bra rd.w */
2617 case O (O_BRAL, SL): /* bra erd.l */
2618 if (fetch (sd, &code->src, &rd))
2620 switch (OP_SIZE (code->opcode)) {
2621 case SB: rd &= 0xff; break;
2622 case SW: rd &= 0xffff; break;
2623 case SL: rd &= 0xffffffff; break;
2625 pc = code->next_pc + rd;
2628 case O (O_BRABC, SB): /* bra/bc, branch if bit clear */
2629 case O (O_BRABS, SB): /* bra/bs, branch if bit set */
2630 case O (O_BSRBC, SB): /* bsr/bc, call if bit clear */
2631 case O (O_BSRBS, SB): /* bsr/bs, call if bit set */
2632 if (fetch (sd, &code->dst, &rd) ||
2633 fetch (sd, &code->src, &bit))
2636 if (code->opcode == O (O_BRABC, SB) || /* branch if clear */
2637 code->opcode == O (O_BSRBC, SB)) /* call if clear */
2639 if ((rd & (1 << bit))) /* no branch */
2642 else /* branch/call if set */
2644 if (!(rd & (1 << bit))) /* no branch */
2648 if (fetch (sd, &code->op3, &res)) /* branch */
2650 pc = code->next_pc + res;
2652 if (code->opcode == O (O_BRABC, SB) ||
2653 code->opcode == O (O_BRABS, SB)) /* branch */
2661 case O (O_BRA, SB): /* bra, branch always */
2666 case O (O_BRN, SB): /* brn, ;-/ branch never? */
2671 case O (O_BHI, SB): /* bhi */
2677 case O (O_BLS, SB): /* bls */
2682 case O (O_BCS, SB): /* bcs, branch if carry set */
2687 case O (O_BCC, SB): /* bcc, branch if carry clear */
2692 case O (O_BEQ, SB): /* beq, branch if zero set */
2696 case O (O_BGT, SB): /* bgt */
2697 if (((Z || (N ^ V)) == 0))
2701 case O (O_BLE, SB): /* ble */
2702 if (((Z || (N ^ V)) == 1))
2706 case O (O_BGE, SB): /* bge */
2710 case O (O_BLT, SB): /* blt */
2714 case O (O_BMI, SB): /* bmi */
2718 case O (O_BNE, SB): /* bne, branch if zero clear */
2723 case O (O_BPL, SB): /* bpl */
2727 case O (O_BVC, SB): /* bvc */
2731 case O (O_BVS, SB): /* bvs */
2736 /* Trap for Command Line setup. */
2737 case O (O_SYS_CMDLINE, SB):
2739 int i = 0; /* Loop counter. */
2740 int j = 0; /* Loop counter. */
2741 int ind_arg_len = 0; /* Length of each argument. */
2742 int no_of_args = 0; /* The no. or cmdline args. */
2743 int current_location = 0; /* Location of string. */
2744 int old_sp = 0; /* The Initial Stack Pointer. */
2745 int no_of_slots = 0; /* No. of slots required on the stack
2746 for storing cmdline args. */
2747 int sp_move = 0; /* No. of locations by which the stack needs
2749 int new_sp = 0; /* The final stack pointer location passed
2751 int *argv_ptrs; /* Pointers of argv strings to be stored. */
2752 int argv_ptrs_location = 0; /* Location of pointers to cmdline
2753 args on the stack. */
2754 int char_ptr_size = 0; /* Size of a character pointer on
2756 int addr_cmdline = 0; /* Memory location where cmdline has
2758 int size_cmdline = 0; /* Size of cmdline. */
2760 /* Set the address of 256 free locations where command line is
2762 addr_cmdline = cmdline_location();
2763 h8_set_reg (sd, 0, addr_cmdline);
2765 /* Counting the no. of commandline arguments. */
2766 for (i = 0; h8_get_cmdline_arg (sd, i) != NULL; i++)
2769 /* No. of arguments in the command line. */
2772 /* Current location is just a temporary variable,which we are
2773 setting to the point to the start of our commandline string. */
2774 current_location = addr_cmdline;
2776 /* Allocating space for storing pointers of the command line
2778 argv_ptrs = (int *) malloc (sizeof (int) * no_of_args);
2780 /* Setting char_ptr_size to the sizeof (char *) on the different
2782 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
2791 for (i = 0; i < no_of_args; i++)
2795 /* The size of the commandline argument. */
2796 ind_arg_len = strlen (h8_get_cmdline_arg (sd, i)) + 1;
2798 /* The total size of the command line string. */
2799 size_cmdline += ind_arg_len;
2801 /* As we have only 256 bytes, we need to provide a graceful
2802 exit. Anyways, a program using command line arguments
2803 where we cannot store all the command line arguments
2804 given may behave unpredictably. */
2805 if (size_cmdline >= 256)
2807 h8_set_reg (sd, 0, 0);
2812 /* current_location points to the memory where the next
2813 commandline argument is stored. */
2814 argv_ptrs[i] = current_location;
2815 for (j = 0; j < ind_arg_len; j++)
2817 SET_MEMORY_B ((current_location +
2818 (sizeof (char) * j)),
2819 *(h8_get_cmdline_arg (sd, i) +
2820 sizeof (char) * j));
2823 /* Setting current_location to the starting of next
2825 current_location += ind_arg_len;
2829 /* This is the original position of the stack pointer. */
2830 old_sp = h8_get_reg (sd, SP_REGNUM);
2832 /* We need space from the stack to store the pointers to argvs. */
2833 /* As we will infringe on the stack, we need to shift the stack
2834 pointer so that the data is not overwritten. We calculate how
2835 much space is required. */
2836 sp_move = (no_of_args) * (char_ptr_size);
2838 /* The final position of stack pointer, we have thus taken some
2839 space from the stack. */
2840 new_sp = old_sp - sp_move;
2842 /* Temporary variable holding value where the argv pointers need
2844 argv_ptrs_location = new_sp;
2846 /* The argv pointers are stored at sequential locations. As per
2848 for (i = 0; i < no_of_args; i++)
2850 /* Saving the argv pointer. */
2851 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
2853 SET_MEMORY_L (argv_ptrs_location, argv_ptrs[i]);
2857 SET_MEMORY_W (argv_ptrs_location, argv_ptrs[i]);
2860 /* The next location where the pointer to the next argv
2861 string has to be stored. */
2862 argv_ptrs_location += char_ptr_size;
2865 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2867 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
2869 SET_MEMORY_L (old_sp, 0x0);
2873 SET_MEMORY_W (old_sp, 0x0);
2876 /* Freeing allocated memory. */
2878 for (i = 0; i <= no_of_args; i++)
2880 free (h8_get_cmdline_arg (sd, i));
2882 free (h8_get_command_line (sd));
2884 /* The no. of argv arguments are returned in Reg 0. */
2885 h8_set_reg (sd, 0, no_of_args);
2886 /* The Pointer to argv in Register 1. */
2887 h8_set_reg (sd, 1, new_sp);
2888 /* Setting the stack pointer to the new value. */
2889 h8_set_reg (sd, SP_REGNUM, new_sp);
2893 /* System call processing starts. */
2894 case O (O_SYS_OPEN, SB):
2896 int len = 0; /* Length of filename. */
2897 char *filename; /* Filename would go here. */
2898 char temp_char; /* Temporary character */
2899 int mode = 0; /* Mode bits for the file. */
2900 int open_return; /* Return value of open, file descriptor. */
2901 int i; /* Loop counter */
2902 int filename_ptr; /* Pointer to filename in cpu memory. */
2904 /* Setting filename_ptr to first argument of open, */
2905 /* and trying to get mode. */
2906 if ((h8300sxmode || h8300hmode || h8300smode) && !h8300_normal_mode)
2908 filename_ptr = GET_L_REG (0);
2909 mode = GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM) + 4);
2913 filename_ptr = GET_W_REG (0);
2914 mode = GET_MEMORY_W (h8_get_reg (sd, SP_REGNUM) + 2);
2917 /* Trying to find the length of the filename. */
2918 temp_char = GET_MEMORY_B (h8_get_reg (sd, 0));
2921 while (temp_char != '\0')
2923 temp_char = GET_MEMORY_B (filename_ptr + len);
2927 /* Allocating space for the filename. */
2928 filename = (char *) malloc (sizeof (char) * len);
2930 /* String copying the filename from memory. */
2931 for (i = 0; i < len; i++)
2933 temp_char = GET_MEMORY_B (filename_ptr + i);
2934 filename[i] = temp_char;
2937 /* Callback to open and return the file descriptor. */
2938 open_return = sim_callback->open (sim_callback, filename, mode);
2940 /* Return value in register 0. */
2941 h8_set_reg (sd, 0, open_return);
2943 /* Freeing memory used for filename. */
2948 case O (O_SYS_READ, SB):
2950 char *char_ptr; /* Where characters read would be stored. */
2951 int fd; /* File descriptor */
2952 int buf_size; /* BUF_SIZE parameter in read. */
2953 int i = 0; /* Temporary Loop counter */
2954 int read_return = 0; /* Return value from callback to
2957 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2958 buf_size = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
2960 char_ptr = (char *) malloc (sizeof (char) * buf_size);
2962 /* Callback to read and return the no. of characters read. */
2964 sim_callback->read (sim_callback, fd, char_ptr, buf_size);
2966 /* The characters read are stored in cpu memory. */
2967 for (i = 0; i < buf_size; i++)
2969 SET_MEMORY_B ((h8_get_reg (sd, 1) + (sizeof (char) * i)),
2970 *(char_ptr + (sizeof (char) * i)));
2973 /* Return value in Register 0. */
2974 h8_set_reg (sd, 0, read_return);
2976 /* Freeing memory used as buffer. */
2981 case O (O_SYS_WRITE, SB):
2983 int fd; /* File descriptor */
2984 char temp_char; /* Temporary character */
2985 int len; /* Length of write, Parameter II to write. */
2986 int char_ptr; /* Character Pointer, Parameter I of write. */
2987 char *ptr; /* Where characters to be written are stored.
2989 int write_return; /* Return value from callback to write. */
2990 int i = 0; /* Loop counter */
2992 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2993 char_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
2994 len = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
2996 /* Allocating space for the characters to be written. */
2997 ptr = (char *) malloc (sizeof (char) * len);
2999 /* Fetching the characters from cpu memory. */
3000 for (i = 0; i < len; i++)
3002 temp_char = GET_MEMORY_B (char_ptr + i);
3006 /* Callback write and return the no. of characters written. */
3007 write_return = sim_callback->write (sim_callback, fd, ptr, len);
3009 /* Return value in Register 0. */
3010 h8_set_reg (sd, 0, write_return);
3012 /* Freeing memory used as buffer. */
3017 case O (O_SYS_LSEEK, SB):
3019 int fd; /* File descriptor */
3020 int offset; /* Offset */
3021 int origin; /* Origin */
3022 int lseek_return; /* Return value from callback to lseek. */
3024 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
3025 offset = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
3026 origin = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
3028 /* Callback lseek and return offset. */
3030 sim_callback->lseek (sim_callback, fd, offset, origin);
3032 /* Return value in register 0. */
3033 h8_set_reg (sd, 0, lseek_return);
3037 case O (O_SYS_CLOSE, SB):
3039 int fd; /* File descriptor */
3040 int close_return; /* Return value from callback to close. */
3042 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
3044 /* Callback close and return. */
3045 close_return = sim_callback->close (sim_callback, fd);
3047 /* Return value in register 0. */
3048 h8_set_reg (sd, 0, close_return);
3052 case O (O_SYS_FSTAT, SB):
3054 int fd; /* File descriptor */
3055 struct stat stat_rec; /* Stat record */
3056 int fstat_return; /* Return value from callback to stat. */
3057 int stat_ptr; /* Pointer to stat record. */
3058 char *temp_stat_ptr; /* Temporary stat_rec pointer. */
3060 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
3062 /* Setting stat_ptr to second argument of stat. */
3063 stat_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
3065 /* Callback stat and return. */
3066 fstat_return = sim_callback->to_fstat (sim_callback, fd,
3069 /* Have stat_ptr point to starting of stat_rec. */
3070 temp_stat_ptr = (char *) (&stat_rec);
3072 /* Setting up the stat structure returned. */
3073 SET_MEMORY_W (stat_ptr, stat_rec.st_dev);
3075 SET_MEMORY_W (stat_ptr, stat_rec.st_ino);
3077 SET_MEMORY_L (stat_ptr, stat_rec.st_mode);
3079 SET_MEMORY_W (stat_ptr, stat_rec.st_nlink);
3081 SET_MEMORY_W (stat_ptr, stat_rec.st_uid);
3083 SET_MEMORY_W (stat_ptr, stat_rec.st_gid);
3085 SET_MEMORY_W (stat_ptr, stat_rec.st_rdev);
3087 SET_MEMORY_L (stat_ptr, stat_rec.st_size);
3089 SET_MEMORY_L (stat_ptr, stat_rec.st_atime);
3091 SET_MEMORY_L (stat_ptr, stat_rec.st_mtime);
3093 SET_MEMORY_L (stat_ptr, stat_rec.st_ctime);
3095 /* Return value in register 0. */
3096 h8_set_reg (sd, 0, fstat_return);
3100 case O (O_SYS_STAT, SB):
3102 int len = 0; /* Length of filename. */
3103 char *filename; /* Filename would go here. */
3104 char temp_char; /* Temporary character */
3105 int filename_ptr; /* Pointer to filename in cpu memory. */
3106 struct stat stat_rec; /* Stat record */
3107 int stat_return; /* Return value from callback to stat */
3108 int stat_ptr; /* Pointer to stat record. */
3109 char *temp_stat_ptr; /* Temporary stat_rec pointer. */
3110 int i = 0; /* Loop Counter */
3112 /* Setting filename_ptr to first argument of open. */
3113 filename_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
3115 /* Trying to find the length of the filename. */
3116 temp_char = GET_MEMORY_B (h8_get_reg (sd, 0));
3119 while (temp_char != '\0')
3121 temp_char = GET_MEMORY_B (filename_ptr + len);
3125 /* Allocating space for the filename. */
3126 filename = (char *) malloc (sizeof (char) * len);
3128 /* String copying the filename from memory. */
3129 for (i = 0; i < len; i++)
3131 temp_char = GET_MEMORY_B (filename_ptr + i);
3132 filename[i] = temp_char;
3135 /* Setting stat_ptr to second argument of stat. */
3136 /* stat_ptr = h8_get_reg (sd, 1); */
3137 stat_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
3139 /* Callback stat and return. */
3141 sim_callback->to_stat (sim_callback, filename, &stat_rec);
3143 /* Have stat_ptr point to starting of stat_rec. */
3144 temp_stat_ptr = (char *) (&stat_rec);
3146 /* Freeing memory used for filename. */
3149 /* Setting up the stat structure returned. */
3150 SET_MEMORY_W (stat_ptr, stat_rec.st_dev);
3152 SET_MEMORY_W (stat_ptr, stat_rec.st_ino);
3154 SET_MEMORY_L (stat_ptr, stat_rec.st_mode);
3156 SET_MEMORY_W (stat_ptr, stat_rec.st_nlink);
3158 SET_MEMORY_W (stat_ptr, stat_rec.st_uid);
3160 SET_MEMORY_W (stat_ptr, stat_rec.st_gid);
3162 SET_MEMORY_W (stat_ptr, stat_rec.st_rdev);
3164 SET_MEMORY_L (stat_ptr, stat_rec.st_size);
3166 SET_MEMORY_L (stat_ptr, stat_rec.st_atime);
3168 SET_MEMORY_L (stat_ptr, stat_rec.st_mtime);
3170 SET_MEMORY_L (stat_ptr, stat_rec.st_ctime);
3172 /* Return value in register 0. */
3173 h8_set_reg (sd, 0, stat_return);
3176 /* End of system call processing. */
3178 case O (O_NOT, SB): /* not.b */
3179 if (fetch2 (sd, &code->src, &rd))
3185 case O (O_NOT, SW): /* not.w */
3186 if (fetch2 (sd, &code->src, &rd))
3192 case O (O_NOT, SL): /* not.l */
3193 if (fetch2 (sd, &code->src, &rd))
3199 case O (O_SHLL, SB): /* shll.b */
3200 case O (O_SHLR, SB): /* shlr.b */
3201 if (fetch2 (sd, &code->dst, &rd))
3204 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3205 ea = 1; /* unary op */
3206 else /* binary op */
3207 fetch (sd, &code->src, &ea);
3209 if (code->opcode == O (O_SHLL, SB))
3212 c = rd & (0x80 >> (ea - 1));
3218 c = rd & (1 << (ea - 1));
3219 rd = (unsigned char) rd >> ea;
3223 case O (O_SHLL, SW): /* shll.w */
3224 case O (O_SHLR, SW): /* shlr.w */
3225 if (fetch2 (sd, &code->dst, &rd))
3228 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3229 ea = 1; /* unary op */
3231 fetch (sd, &code->src, &ea);
3233 if (code->opcode == O (O_SHLL, SW))
3236 c = rd & (0x8000 >> (ea - 1));
3242 c = rd & (1 << (ea - 1));
3243 rd = (unsigned short) rd >> ea;
3247 case O (O_SHLL, SL): /* shll.l */
3248 case O (O_SHLR, SL): /* shlr.l */
3249 if (fetch2 (sd, &code->dst, &rd))
3252 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3253 ea = 1; /* unary op */
3255 fetch (sd, &code->src, &ea);
3257 if (code->opcode == O (O_SHLL, SL))
3260 c = rd & (0x80000000 >> (ea - 1));
3266 c = rd & (1 << (ea - 1));
3267 rd = (unsigned int) rd >> ea;
3271 case O (O_SHAL, SB):
3272 case O (O_SHAR, SB):
3273 if (fetch2 (sd, &code->dst, &rd))
3276 if (code->src.type == X (OP_IMM, SB))
3277 fetch (sd, &code->src, &ea);
3281 if (code->opcode == O (O_SHAL, SB))
3283 c = rd & (0x80 >> (ea - 1));
3284 res = rd >> (7 - ea);
3285 v = ((res & 1) && !(res & 2))
3286 || (!(res & 1) && (res & 2));
3291 c = rd & (1 << (ea - 1));
3293 rd = ((signed char) rd) >> ea;
3297 case O (O_SHAL, SW):
3298 case O (O_SHAR, SW):
3299 if (fetch2 (sd, &code->dst, &rd))
3302 if (code->src.type == X (OP_IMM, SW))
3303 fetch (sd, &code->src, &ea);
3307 if (code->opcode == O (O_SHAL, SW))
3309 c = rd & (0x8000 >> (ea - 1));
3310 res = rd >> (15 - ea);
3311 v = ((res & 1) && !(res & 2))
3312 || (!(res & 1) && (res & 2));
3317 c = rd & (1 << (ea - 1));
3319 rd = ((signed short) rd) >> ea;
3323 case O (O_SHAL, SL):
3324 case O (O_SHAR, SL):
3325 if (fetch2 (sd, &code->dst, &rd))
3328 if (code->src.type == X (OP_IMM, SL))
3329 fetch (sd, &code->src, &ea);
3333 if (code->opcode == O (O_SHAL, SL))
3335 c = rd & (0x80000000 >> (ea - 1));
3336 res = rd >> (31 - ea);
3337 v = ((res & 1) && !(res & 2))
3338 || (!(res & 1) && (res & 2));
3343 c = rd & (1 << (ea - 1));
3345 rd = ((signed int) rd) >> ea;
3349 case O (O_ROTL, SB):
3350 case O (O_ROTR, SB):
3351 if (fetch2 (sd, &code->dst, &rd))
3354 if (code->src.type == X (OP_IMM, SB))
3355 fetch (sd, &code->src, &ea);
3360 if (code->opcode == O (O_ROTL, SB))
3370 rd = ((unsigned char) rd) >> 1;
3378 case O (O_ROTL, SW):
3379 case O (O_ROTR, SW):
3380 if (fetch2 (sd, &code->dst, &rd))
3383 if (code->src.type == X (OP_IMM, SW))
3384 fetch (sd, &code->src, &ea);
3389 if (code->opcode == O (O_ROTL, SW))
3399 rd = ((unsigned short) rd) >> 1;
3407 case O (O_ROTL, SL):
3408 case O (O_ROTR, SL):
3409 if (fetch2 (sd, &code->dst, &rd))
3412 if (code->src.type == X (OP_IMM, SL))
3413 fetch (sd, &code->src, &ea);
3418 if (code->opcode == O (O_ROTL, SL))
3420 c = rd & 0x80000000;
3428 rd = ((unsigned int) rd) >> 1;
3436 case O (O_ROTXL, SB):
3437 case O (O_ROTXR, SB):
3438 if (fetch2 (sd, &code->dst, &rd))
3441 if (code->src.type == X (OP_IMM, SB))
3442 fetch (sd, &code->src, &ea);
3447 if (code->opcode == O (O_ROTXL, SB))
3458 rd = ((unsigned char) rd) >> 1;
3467 case O (O_ROTXL, SW):
3468 case O (O_ROTXR, SW):
3469 if (fetch2 (sd, &code->dst, &rd))
3472 if (code->src.type == X (OP_IMM, SW))
3473 fetch (sd, &code->src, &ea);
3478 if (code->opcode == O (O_ROTXL, SW))
3489 rd = ((unsigned short) rd) >> 1;
3498 case O (O_ROTXL, SL):
3499 case O (O_ROTXR, SL):
3500 if (fetch2 (sd, &code->dst, &rd))
3503 if (code->src.type == X (OP_IMM, SL))
3504 fetch (sd, &code->src, &ea);
3509 if (code->opcode == O (O_ROTXL, SL))
3511 res = rd & 0x80000000;
3520 rd = ((unsigned int) rd) >> 1;
3531 case O (O_JMP, SB): /* jmp */
3533 fetch (sd, &code->src, &pc);
3538 case O (O_JSR, SB): /* jsr, jump to subroutine */
3540 if (fetch (sd, &code->src, &pc))
3543 tmp = h8_get_reg (sd, SP_REGNUM);
3545 if (h8300hmode && !h8300_normal_mode)
3548 SET_MEMORY_L (tmp, code->next_pc);
3553 SET_MEMORY_W (tmp, code->next_pc);
3555 h8_set_reg (sd, SP_REGNUM, tmp);
3561 case O (O_BSR, SB): /* bsr, branch to subroutine */
3562 if (fetch (sd, &code->src, &res))
3564 pc = code->next_pc + res;
3567 case O (O_RTE, SN): /* rte, return from exception */
3569 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3570 tmp = h8_get_reg (sd, SP_REGNUM);
3572 if (h8300smode) /* pop exr */
3574 h8_set_exr (sd, GET_MEMORY_L (tmp));
3577 if (h8300hmode && !h8300_normal_mode)
3579 h8_set_ccr (sd, GET_MEMORY_L (tmp));
3581 pc = GET_MEMORY_L (tmp);
3586 h8_set_ccr (sd, GET_MEMORY_W (tmp));
3588 pc = GET_MEMORY_W (tmp);
3593 h8_set_reg (sd, SP_REGNUM, tmp);
3596 case O (O_RTS, SN): /* rts, return from subroutine */
3598 tmp = h8_get_reg (sd, SP_REGNUM);
3600 if (h8300hmode && !h8300_normal_mode)
3602 pc = GET_MEMORY_L (tmp);
3607 pc = GET_MEMORY_W (tmp);
3611 h8_set_reg (sd, SP_REGNUM, tmp);
3614 case O (O_ILL, SB): /* illegal */
3615 sim_engine_set_run_state (sd, sim_stopped, SIGILL);
3618 case O (O_SLEEP, SN): /* sleep */
3619 /* Check for magic numbers in r1 and r2. */
3620 if ((h8_get_reg (sd, R1_REGNUM) & 0xffff) == LIBC_EXIT_MAGIC1 &&
3621 (h8_get_reg (sd, R2_REGNUM) & 0xffff) == LIBC_EXIT_MAGIC2 &&
3622 SIM_WIFEXITED (h8_get_reg (sd, 0)))
3624 /* This trap comes from _exit, not from gdb. */
3625 sim_engine_set_run_state (sd, sim_exited,
3626 SIM_WEXITSTATUS (h8_get_reg (sd, 0)));
3629 /* Unfortunately this won't really work, because
3630 when we take a breakpoint trap, R0 has a "random",
3631 user-defined value. Don't see any immediate solution. */
3632 else if (SIM_WIFSTOPPED (h8_get_reg (sd, 0)))
3634 /* Pass the stop signal up to gdb. */
3635 sim_engine_set_run_state (sd, sim_stopped,
3636 SIM_WSTOPSIG (h8_get_reg (sd, 0)));
3641 /* Treat it as a sigtrap. */
3642 sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
3646 case O (O_TRAPA, SB): /* trapa */
3647 if (fetch (sd, &code->src, &res))
3648 goto end; /* res is vector number. */
3650 tmp = h8_get_reg (sd, SP_REGNUM);
3651 if(h8300_normal_mode)
3654 SET_MEMORY_W (tmp, code->next_pc);
3656 SET_MEMORY_W (tmp, h8_get_ccr (sd));
3661 SET_MEMORY_L (tmp, code->next_pc);
3663 SET_MEMORY_L (tmp, h8_get_ccr (sd));
3671 SET_MEMORY_L (tmp, h8_get_exr (sd));
3674 h8_set_reg (sd, SP_REGNUM, tmp);
3676 if(h8300_normal_mode)
3677 pc = GET_MEMORY_L (0x10 + res * 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3679 pc = GET_MEMORY_L (0x20 + res * 4);
3683 sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
3686 case O (O_BSETEQ, SB):
3691 case O (O_BSETNE, SB):
3696 case O (O_BCLREQ, SB):
3701 case O (O_BCLRNE, SB):
3706 OBITOP (O_BNOT, 1, 1, ea ^= m); /* bnot */
3707 OBITOP (O_BTST, 1, 0, nz = ea & m); /* btst */
3709 OBITOP (O_BSET, 1, 1, ea |= m); /* bset */
3711 OBITOP (O_BCLR, 1, 1, ea &= ~m); /* bclr */
3712 OBITOP (O_BLD, 1, 0, c = ea & m); /* bld */
3713 OBITOP (O_BILD, 1, 0, c = !(ea & m)); /* bild */
3714 OBITOP (O_BST, 1, 1, ea &= ~m;
3715 if (C) ea |= m); /* bst */
3716 OBITOP (O_BIST, 1, 1, ea &= ~m;
3717 if (!C) ea |= m); /* bist */
3718 OBITOP (O_BSTZ, 1, 1, ea &= ~m;
3719 if (Z) ea |= m); /* bstz */
3720 OBITOP (O_BISTZ, 1, 1, ea &= ~m;
3721 if (!Z) ea |= m); /* bistz */
3722 OBITOP (O_BAND, 1, 0, c = (ea & m) && C); /* band */
3723 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); /* biand */
3724 OBITOP (O_BOR, 1, 0, c = (ea & m) || C); /* bor */
3725 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); /* bior */
3726 OBITOP (O_BXOR, 1, 0, c = ((ea & m) != 0)!= C); /* bxor */
3727 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); /* bixor */
3729 case O (O_BFLD, SB): /* bfld */
3732 if (fetch (sd, &code->src, &bit))
3737 if (fetch (sd, &code->dst, &ea))
3747 if (store (sd, &code->op3, ea))
3752 case O(O_BFST, SB): /* bfst */
3753 /* bitfield store */
3754 /* NOTE: the imm8 value is in dst, and the ea value
3755 (which is actually the destination) is in op3.
3756 It has to be that way, to avoid breaking the assembler. */
3758 if (fetch (sd, &code->dst, &bit)) /* imm8 */
3760 if (bit == 0) /* noop -- nothing to do. */
3763 if (fetch (sd, &code->src, &rd)) /* reg8 src */
3766 if (fetch2 (sd, &code->op3, &ea)) /* ea dst */
3769 /* Left-shift the register data into position. */
3770 for (tmp = bit; !(tmp & 1); tmp >>= 1)
3773 /* Combine it with the neighboring bits. */
3774 ea = (ea & ~bit) | (rd & bit);
3777 if (store2 (sd, &code->op3, ea))
3781 case O (O_CLRMAC, SN): /* clrmac */
3782 h8_set_mach (sd, 0);
3783 h8_set_macl (sd, 0);
3784 h8_set_macZ (sd, 1);
3785 h8_set_macV (sd, 0);
3786 h8_set_macN (sd, 0);
3789 case O (O_STMAC, SL): /* stmac, 260 */
3790 switch (code->src.type) {
3791 case X (OP_MACH, SL):
3792 res = h8_get_mach (sd);
3793 if (res & 0x200) /* sign extend */
3796 case X (OP_MACL, SL):
3797 res = h8_get_macl (sd);
3799 default: goto illegal;
3801 nz = !h8_get_macZ (sd);
3802 n = h8_get_macN (sd);
3803 v = h8_get_macV (sd);
3805 if (store (sd, &code->dst, res))
3810 case O (O_LDMAC, SL): /* ldmac, 179 */
3811 if (fetch (sd, &code->src, &rd))
3814 switch (code->dst.type) {
3815 case X (OP_MACH, SL):
3816 rd &= 0x3ff; /* Truncate to 10 bits */
3817 h8_set_mach (sd, rd);
3819 case X (OP_MACL, SL):
3820 h8_set_macl (sd, rd);
3822 default: goto illegal;
3824 h8_set_macV (sd, 0);
3828 if (fetch (sd, &code->src, &rd) ||
3829 fetch (sd, &code->dst, &res))
3832 /* Ye gods, this is non-portable!
3833 However, the existing mul/div code is similar. */
3834 res = SEXTSHORT (res) * SEXTSHORT (rd);
3836 if (h8_get_macS (sd)) /* Saturating mode */
3838 long long mac = h8_get_macl (sd);
3840 if (mac & 0x80000000) /* sign extend */
3841 mac |= 0xffffffff00000000LL;
3844 if (mac > 0x7fffffff || mac < 0xffffffff80000000LL)
3845 h8_set_macV (sd, 1);
3846 h8_set_macZ (sd, (mac == 0));
3847 h8_set_macN (sd, (mac < 0));
3848 h8_set_macl (sd, (int) mac);
3850 else /* "Less Saturating" mode */
3852 long long mac = h8_get_mach (sd);
3854 mac += h8_get_macl (sd);
3856 if (mac & 0x20000000000LL) /* sign extend */
3857 mac |= 0xfffffc0000000000LL;
3860 if (mac > 0x1ffffffffffLL ||
3861 mac < (long long) 0xfffffe0000000000LL)
3862 h8_set_macV (sd, 1);
3863 h8_set_macZ (sd, (mac == 0));
3864 h8_set_macN (sd, (mac < 0));
3865 h8_set_macl (sd, (int) mac);
3867 h8_set_mach (sd, (int) (mac & 0x3ff));
3871 case O (O_MULS, SW): /* muls.w */
3872 if (fetch (sd, &code->src, &ea) ||
3873 fetch (sd, &code->dst, &rd))
3876 ea = SEXTSHORT (ea);
3877 res = SEXTSHORT (ea * SEXTSHORT (rd));
3881 if (store (sd, &code->dst, res))
3886 case O (O_MULS, SL): /* muls.l */
3887 if (fetch (sd, &code->src, &ea) ||
3888 fetch (sd, &code->dst, &rd))
3893 n = res & 0x80000000;
3894 nz = res & 0xffffffff;
3895 if (store (sd, &code->dst, res))
3899 case O (O_MULSU, SL): /* muls/u.l */
3900 if (fetch (sd, &code->src, &ea) ||
3901 fetch (sd, &code->dst, &rd))
3904 /* Compute upper 32 bits of the 64-bit result. */
3905 res = (((long long) ea) * ((long long) rd)) >> 32;
3907 n = res & 0x80000000;
3908 nz = res & 0xffffffff;
3909 if (store (sd, &code->dst, res))
3913 case O (O_MULU, SW): /* mulu.w */
3914 if (fetch (sd, &code->src, &ea) ||
3915 fetch (sd, &code->dst, &rd))
3918 res = UEXTSHORT ((UEXTSHORT (ea) * UEXTSHORT (rd)));
3920 /* Don't set Z or N. */
3921 if (store (sd, &code->dst, res))
3926 case O (O_MULU, SL): /* mulu.l */
3927 if (fetch (sd, &code->src, &ea) ||
3928 fetch (sd, &code->dst, &rd))
3933 /* Don't set Z or N. */
3934 if (store (sd, &code->dst, res))
3939 case O (O_MULUU, SL): /* mulu/u.l */
3940 if (fetch (sd, &code->src, &ea) ||
3941 fetch (sd, &code->dst, &rd))
3944 /* Compute upper 32 bits of the 64-bit result. */
3945 res = (((unsigned long long) (unsigned) ea) *
3946 ((unsigned long long) (unsigned) rd)) >> 32;
3948 /* Don't set Z or N. */
3949 if (store (sd, &code->dst, res))
3954 case O (O_MULXS, SB): /* mulxs.b */
3955 if (fetch (sd, &code->src, &ea) ||
3956 fetch (sd, &code->dst, &rd))
3960 res = ea * SEXTCHAR (rd);
3964 if (store (sd, &code->dst, res))
3969 case O (O_MULXS, SW): /* mulxs.w */
3970 if (fetch (sd, &code->src, &ea) ||
3971 fetch (sd, &code->dst, &rd))
3974 ea = SEXTSHORT (ea);
3975 res = ea * SEXTSHORT (rd & 0xffff);
3977 n = res & 0x80000000;
3978 nz = res & 0xffffffff;
3979 if (store (sd, &code->dst, res))
3984 case O (O_MULXU, SB): /* mulxu.b */
3985 if (fetch (sd, &code->src, &ea) ||
3986 fetch (sd, &code->dst, &rd))
3989 res = UEXTCHAR (ea) * UEXTCHAR (rd);
3991 if (store (sd, &code->dst, res))
3996 case O (O_MULXU, SW): /* mulxu.w */
3997 if (fetch (sd, &code->src, &ea) ||
3998 fetch (sd, &code->dst, &rd))
4001 res = UEXTSHORT (ea) * UEXTSHORT (rd);
4003 if (store (sd, &code->dst, res))
4008 case O (O_TAS, SB): /* tas (test and set) */
4009 if (!h8300sxmode) /* h8sx can use any register. */
4010 switch (code->src.reg)
4021 if (fetch (sd, &code->src, &res))
4023 if (store (sd, &code->src, res | 0x80))
4026 goto just_flags_log8;
4028 case O (O_DIVU, SW): /* divu.w */
4029 if (fetch (sd, &code->src, &ea) ||
4030 fetch (sd, &code->dst, &rd))
4036 res = (unsigned) (UEXTSHORT (rd) / UEXTSHORT (ea));
4040 if (store (sd, &code->dst, res))
4044 case O (O_DIVU, SL): /* divu.l */
4045 if (fetch (sd, &code->src, &ea) ||
4046 fetch (sd, &code->dst, &rd))
4049 n = ea & 0x80000000;
4050 nz = ea & 0xffffffff;
4052 res = (unsigned) rd / ea;
4056 if (store (sd, &code->dst, res))
4060 case O (O_DIVS, SW): /* divs.w */
4061 if (fetch (sd, &code->src, &ea) ||
4062 fetch (sd, &code->dst, &rd))
4067 res = SEXTSHORT (rd) / SEXTSHORT (ea);
4077 if (store (sd, &code->dst, res))
4081 case O (O_DIVS, SL): /* divs.l */
4082 if (fetch (sd, &code->src, &ea) ||
4083 fetch (sd, &code->dst, &rd))
4097 n = res & 0x80000000;
4098 if (store (sd, &code->dst, res))
4102 case O (O_DIVXU, SB): /* divxu.b */
4103 if (fetch (sd, &code->src, &ea) ||
4104 fetch (sd, &code->dst, &rd))
4107 rd = UEXTSHORT (rd);
4114 tmp = (unsigned) rd % ea;
4115 res = (unsigned) rd / ea;
4123 if (store (sd, &code->dst, (res & 0xff) | (tmp << 8)))
4127 case O (O_DIVXU, SW): /* divxu.w */
4128 if (fetch (sd, &code->src, &ea) ||
4129 fetch (sd, &code->dst, &rd))
4132 ea = UEXTSHORT (ea);
4138 tmp = (unsigned) rd % ea;
4139 res = (unsigned) rd / ea;
4147 if (store (sd, &code->dst, (res & 0xffff) | (tmp << 16)))
4151 case O (O_DIVXS, SB): /* divxs.b */
4152 if (fetch (sd, &code->src, &ea) ||
4153 fetch (sd, &code->dst, &rd))
4156 rd = SEXTSHORT (rd);
4161 tmp = (int) rd % (int) ea;
4162 res = (int) rd / (int) ea;
4173 if (store (sd, &code->dst, (res & 0xff) | (tmp << 8)))
4177 case O (O_DIVXS, SW): /* divxs.w */
4178 if (fetch (sd, &code->src, &ea) ||
4179 fetch (sd, &code->dst, &rd))
4182 ea = SEXTSHORT (ea);
4186 tmp = (int) rd % (int) ea;
4187 res = (int) rd / (int) ea;
4197 n = res & 0x80000000;
4198 if (store (sd, &code->dst, (res & 0xffff) | (tmp << 16)))
4202 case O (O_EXTS, SW): /* exts.w, signed extend */
4203 if (fetch2 (sd, &code->dst, &rd))
4205 ea = rd & 0x80 ? -256 : 0;
4206 res = (rd & 0xff) + ea;
4209 case O (O_EXTS, SL): /* exts.l, signed extend */
4210 if (fetch2 (sd, &code->dst, &rd))
4212 if (code->src.type == X (OP_IMM, SL))
4214 if (fetch (sd, &code->src, &ea))
4217 if (ea == 2) /* exts.l #2, nn */
4219 /* Sign-extend from 8-bit to 32-bit. */
4220 ea = rd & 0x80 ? -256 : 0;
4221 res = (rd & 0xff) + ea;
4225 /* Sign-extend from 16-bit to 32-bit. */
4226 ea = rd & 0x8000 ? -65536 : 0;
4227 res = (rd & 0xffff) + ea;
4230 case O (O_EXTU, SW): /* extu.w, unsigned extend */
4231 if (fetch2 (sd, &code->dst, &rd))
4234 res = (rd & 0xff) + ea;
4237 case O (O_EXTU, SL): /* extu.l, unsigned extend */
4238 if (fetch2 (sd, &code->dst, &rd))
4240 if (code->src.type == X (OP_IMM, SL))
4242 if (fetch (sd, &code->src, &ea))
4245 if (ea == 2) /* extu.l #2, nn */
4247 /* Zero-extend from 8-bit to 32-bit. */
4249 res = (rd & 0xff) + ea;
4253 /* Zero-extend from 16-bit to 32-bit. */
4255 res = (rd & 0xffff) + ea;
4258 case O (O_NOP, SN): /* nop */
4261 case O (O_STM, SL): /* stm, store to memory */
4263 int nregs, firstreg, i;
4265 nregs = GET_MEMORY_B (pc + 1);
4268 firstreg = code->src.reg;
4270 for (i = firstreg; i <= firstreg + nregs; i++)
4272 h8_set_reg (sd, SP_REGNUM, h8_get_reg (sd, SP_REGNUM) - 4);
4273 SET_MEMORY_L (h8_get_reg (sd, SP_REGNUM), h8_get_reg (sd, i));
4278 case O (O_LDM, SL): /* ldm, load from memory */
4279 case O (O_RTEL, SN): /* rte/l, ldm plus rte */
4280 case O (O_RTSL, SN): /* rts/l, ldm plus rts */
4282 int nregs, firstreg, i;
4284 nregs = ((GET_MEMORY_B (pc + 1) >> 4) & 0xf);
4285 firstreg = code->dst.reg & 0xf;
4286 for (i = firstreg; i >= firstreg - nregs; i--)
4288 h8_set_reg (sd, i, GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM)));
4289 h8_set_reg (sd, SP_REGNUM, h8_get_reg (sd, SP_REGNUM) + 4);
4292 switch (code->opcode) {
4293 case O (O_RTEL, SN):
4295 case O (O_RTSL, SN):
4304 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4305 res = GET_B_REG (code->src.reg); /* FIXME fetch? */
4306 if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4307 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4308 res = res; /* Value added == 0. */
4309 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) &&
4310 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4311 res = res + 0x6; /* Value added == 6. */
4312 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4313 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4314 res = res + 0x6; /* Value added == 6. */
4315 else if (!c && (10 <= (res >> 4) && (res >> 4) <= 15) &&
4316 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4317 res = res + 0x60; /* Value added == 60. */
4318 else if (!c && (9 <= (res >> 4) && (res >> 4) <= 15) &&
4319 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4320 res = res + 0x66; /* Value added == 66. */
4321 else if (!c && (10 <= (res >> 4) && (res >> 4) <= 15) &&
4322 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4323 res = res + 0x66; /* Value added == 66. */
4324 else if ( c && (1 <= (res >> 4) && (res >> 4) <= 2) &&
4325 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4326 res = res + 0x60; /* Value added == 60. */
4327 else if ( c && (1 <= (res >> 4) && (res >> 4) <= 2) &&
4328 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4329 res = res + 0x66; /* Value added == 66. */
4330 else if (c && (1 <= (res >> 4) && (res >> 4) <= 3) &&
4331 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4332 res = res + 0x66; /* Value added == 66. */
4337 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4338 res = GET_B_REG (code->src.reg); /* FIXME fetch, fetch2... */
4339 if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4340 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4341 res = res; /* Value added == 0. */
4342 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) &&
4343 h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
4344 res = res + 0xfa; /* Value added == 0xfa. */
4345 else if ( c && (7 <= (res >> 4) && (res >> 4) <= 15) &&
4346 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4347 res = res + 0xa0; /* Value added == 0xa0. */
4348 else if (c && (6 <= (res >> 4) && (res >> 4) <= 15) &&
4349 h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
4350 res = res + 0x9a; /* Value added == 0x9a. */
4356 sim_engine_set_run_state (sd, sim_stopped, SIGILL);
4361 (*sim_callback->printf_filtered) (sim_callback,
4362 "sim_resume: internal error.\n");
4363 sim_engine_set_run_state (sd, sim_stopped, SIGILL);
4367 if (code->dst.type == X (OP_CCR, SB) ||
4368 code->dst.type == X (OP_CCR, SW))
4370 h8_set_ccr (sd, res);
4373 else if (h8300smode &&
4374 (code->dst.type == X (OP_EXR, SB) ||
4375 code->dst.type == X (OP_EXR, SW)))
4377 h8_set_exr (sd, res);
4378 if (h8300smode) /* Get exr. */
4380 trace = (h8_get_exr (sd) >> 7) & 1;
4381 intMask = h8_get_exr (sd) & 7;
4390 /* When a branch works */
4391 if (fetch (sd, &code->src, &res))
4393 if (res & 1) /* bad address */
4395 pc = code->next_pc + res;
4398 /* Set the cond codes from res */
4401 /* Set the flags after an 8 bit inc/dec operation */
4405 v = (rd & 0x7f) == 0x7f;
4408 /* Set the flags after an 16 bit inc/dec operation */
4412 v = (rd & 0x7fff) == 0x7fff;
4415 /* Set the flags after an 32 bit inc/dec operation */
4417 n = res & 0x80000000;
4418 nz = res & 0xffffffff;
4419 v = (rd & 0x7fffffff) == 0x7fffffff;
4423 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4426 if (store2 (sd, &code->dst, rd))
4431 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4434 if (store2 (sd, &code->dst, rd))
4439 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4440 n = (rd & 0x80000000);
4441 nz = rd & 0xffffffff;
4442 if (store2 (sd, &code->dst, rd))
4447 if (store2 (sd, &code->dst, res))
4451 /* flags after a 32bit logical operation */
4452 n = res & 0x80000000;
4453 nz = res & 0xffffffff;
4458 if (store2 (sd, &code->dst, res))
4462 /* flags after a 16bit logical operation */
4469 if (store2 (sd, &code->dst, res))
4479 if (store2 (sd, &code->dst, res))
4486 switch (code->opcode / 4)
4490 v = ((rd & 0x80) == (ea & 0x80)
4491 && (rd & 0x80) != (res & 0x80));
4496 v = ((rd & 0x80) != (-ea & 0x80)
4497 && (rd & 0x80) != (res & 0x80));
4504 break; /* No effect on v flag. */
4509 if (store2 (sd, &code->dst, res))
4515 c = (res & 0x10000);
4516 switch (code->opcode / 4)
4520 v = ((rd & 0x8000) == (ea & 0x8000)
4521 && (rd & 0x8000) != (res & 0x8000));
4526 v = ((rd & 0x8000) != (-ea & 0x8000)
4527 && (rd & 0x8000) != (res & 0x8000));
4536 if (store2 (sd, &code->dst, res))
4540 n = res & 0x80000000;
4541 nz = res & 0xffffffff;
4542 switch (code->opcode / 4)
4546 v = ((rd & 0x80000000) == (ea & 0x80000000)
4547 && (rd & 0x80000000) != (res & 0x80000000));
4548 c = ((unsigned) res < (unsigned) rd) ||
4549 ((unsigned) res < (unsigned) ea);
4554 v = ((rd & 0x80000000) != (-ea & 0x80000000)
4555 && (rd & 0x80000000) != (res & 0x80000000));
4556 c = (unsigned) rd < (unsigned) -ea;
4559 v = (rd == 0x80000000);
4566 if ((res = h8_get_delayed_branch (sd)) != 0)
4569 h8_set_delayed_branch (sd, 0);
4576 if (--poll_count < 0)
4578 poll_count = POLL_QUIT_INTERVAL;
4579 if ((*sim_callback->poll_quit) != NULL
4580 && (*sim_callback->poll_quit) (sim_callback))
4581 sim_engine_set_run_state (sd, sim_stopped, SIGINT);
4583 sim_engine_get_run_state (sd, &reason, &sigrc);
4584 } while (reason == sim_running);
4586 h8_set_ticks (sd, h8_get_ticks (sd) + get_now () - tick_start);
4587 h8_set_cycles (sd, h8_get_cycles (sd) + cycles);
4588 h8_set_insts (sd, h8_get_insts (sd) + insts);
4593 h8_set_exr (sd, (trace<<7) | intMask);
4595 h8_set_mask (sd, oldmask);
4599 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
4606 for (i = 0; i < size; i++)
4608 if (addr < memory_size)
4610 h8_set_memory (sd, addr + i, buffer[i]);
4611 h8_set_cache_idx (sd, addr + i, 0);
4615 h8_set_eightbit (sd, (addr + i) & 0xff, buffer[i]);
4622 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
4627 if (addr < memory_size)
4628 memcpy (buffer, h8_get_memory_buf (sd) + addr, size);
4630 memcpy (buffer, h8_get_eightbit_buf (sd) + (addr & 0xff), size);
4636 sim_store_register (SIM_DESC sd, int rn, unsigned char *value, int length)
4641 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
4642 shortval = (value[0] << 8) | (value[1]);
4643 intval = h8300hmode ? longval : shortval;
4649 if(h8300_normal_mode)
4650 h8_set_pc (sd, shortval); /* PC for Normal mode is 2 bytes */
4652 h8_set_pc (sd, intval);
4655 (*sim_callback->printf_filtered) (sim_callback,
4656 "sim_store_register: bad regnum %d.\n",
4666 h8_set_reg (sd, rn, intval);
4669 h8_set_ccr (sd, intval);
4672 h8_set_exr (sd, intval);
4675 h8_set_sbr (sd, intval);
4678 h8_set_vbr (sd, intval);
4681 h8_set_mach (sd, intval);
4684 h8_set_macl (sd, intval);
4687 h8_set_cycles (sd, longval);
4691 h8_set_insts (sd, longval);
4695 h8_set_ticks (sd, longval);
4702 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
4709 if (!h8300smode && rn >= EXR_REGNUM)
4714 (*sim_callback->printf_filtered) (sim_callback,
4715 "sim_fetch_register: bad regnum %d.\n",
4720 v = h8_get_ccr (sd);
4723 v = h8_get_exr (sd);
4729 v = h8_get_sbr (sd);
4732 v = h8_get_vbr (sd);
4735 v = h8_get_mach (sd);
4738 v = h8_get_macl (sd);
4748 v = h8_get_reg (sd, rn);
4751 v = h8_get_cycles (sd);
4755 v = h8_get_ticks (sd);
4759 v = h8_get_insts (sd);
4763 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4764 if ((h8300hmode || longreg) && !(rn == PC_REGNUM && h8300_normal_mode))
4780 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
4782 sim_engine_get_run_state (sd, reason, sigrc);
4786 set_simcache_size (SIM_DESC sd, int n)
4789 free (sd->sim_cache);
4792 sd->sim_cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
4793 memset (sd->sim_cache, 0, sizeof (decoded_inst) * n);
4794 sd->sim_cache_size = n;
4799 sim_info (SIM_DESC sd, int verbose)
4801 double timetaken = (double) h8_get_ticks (sd) / (double) now_persec ();
4802 double virttime = h8_get_cycles (sd) / 10.0e6;
4804 (*sim_callback->printf_filtered) (sim_callback,
4805 "\n\n#instructions executed %10d\n",
4807 (*sim_callback->printf_filtered) (sim_callback,
4808 "#cycles (v approximate) %10d\n",
4809 h8_get_cycles (sd));
4810 (*sim_callback->printf_filtered) (sim_callback,
4811 "#real time taken %10.4f\n",
4813 (*sim_callback->printf_filtered) (sim_callback,
4814 "#virtual time taken %10.4f\n",
4816 if (timetaken != 0.0)
4817 (*sim_callback->printf_filtered) (sim_callback,
4818 "#simulation ratio %10.4f\n",
4819 virttime / timetaken);
4820 (*sim_callback->printf_filtered) (sim_callback,
4822 h8_get_compiles (sd));
4823 (*sim_callback->printf_filtered) (sim_callback,
4824 "#cache size %10d\n",
4825 sd->sim_cache_size);
4828 /* This to be conditional on `what' (aka `verbose'),
4829 however it was never passed as non-zero. */
4833 for (i = 0; i < O_LAST; i++)
4835 if (h8_get_stats (sd, i))
4836 (*sim_callback->printf_filtered) (sim_callback, "%d: %d\n",
4837 i, h8_get_stats (sd, i));
4843 /* Indicate whether the cpu is an H8/300 or H8/300H.
4844 FLAG is non-zero for the H8/300H. */
4847 set_h8300h (unsigned long machine)
4849 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4850 This function being replaced by a sim_open:ARGV configuration
4853 h8300hmode = h8300smode = h8300sxmode = h8300_normal_mode = 0;
4855 if (machine == bfd_mach_h8300sx || machine == bfd_mach_h8300sxn)
4858 if (machine == bfd_mach_h8300s || machine == bfd_mach_h8300sn || h8300sxmode)
4861 if (machine == bfd_mach_h8300h || machine == bfd_mach_h8300hn || h8300smode)
4864 if(machine == bfd_mach_h8300hn || machine == bfd_mach_h8300sn || machine == bfd_mach_h8300sxn)
4865 h8300_normal_mode = 1;
4869 h8300_pc_get (sim_cpu *cpu)
4875 h8300_pc_set (sim_cpu *cpu, sim_cia pc)
4880 /* Cover function of sim_state_free to free the cpu buffers as well. */
4883 free_state (SIM_DESC sd)
4885 if (STATE_MODULES (sd) != NULL)
4886 sim_module_uninstall (sd);
4888 /* Fixme: free buffers in _sim_cpu. */
4889 sim_state_free (sd);
4893 sim_open (SIM_OPEN_KIND kind,
4894 struct host_callback_struct *callback,
4902 sd = sim_state_alloc (kind, callback);
4904 /* The cpu data is kept in a separately allocated chunk of memory. */
4905 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
4911 cpu = STATE_CPU (sd, 0);
4912 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
4913 sim_state_initialize (sd, cpu);
4914 /* sim_cpu object is new, so some initialization is needed. */
4915 init_pointers_needed = 1;
4917 /* For compatibility (FIXME: is this right?). */
4918 current_alignment = NONSTRICT_ALIGNMENT;
4919 current_target_byte_order = BIG_ENDIAN;
4921 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
4927 /* getopt will print the error message so we just have to exit if
4928 this fails. FIXME: Hmmm... in the case of gdb we need getopt
4929 to call print_filtered. */
4930 if (sim_parse_args (sd, argv) != SIM_RC_OK)
4932 /* Uninstall the modules to avoid memory leaks,
4933 file descriptor leaks, etc. */
4938 /* Check for/establish the a reference program image. */
4939 if (sim_analyze_program (sd,
4940 (STATE_PROG_ARGV (sd) != NULL
4941 ? *STATE_PROG_ARGV (sd)
4942 : NULL), abfd) != SIM_RC_OK)
4948 /* Establish any remaining configuration options. */
4949 if (sim_config (sd) != SIM_RC_OK)
4955 if (sim_post_argv_init (sd) != SIM_RC_OK)
4957 /* Uninstall the modules to avoid memory leaks,
4958 file descriptor leaks, etc. */
4963 /* CPU specific initialization. */
4964 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
4966 SIM_CPU *cpu = STATE_CPU (sd, i);
4968 CPU_PC_FETCH (cpu) = h8300_pc_get;
4969 CPU_PC_STORE (cpu) = h8300_pc_set;
4972 /* sim_hw_configure (sd); */
4974 /* FIXME: Much of the code in sim_load can be moved here. */
4978 sim_callback = callback;
4983 sim_close (SIM_DESC sd, int quitting)
4985 /* Nothing to do. */
4988 /* Called by gdb to load a program into memory. */
4991 sim_load (SIM_DESC sd, const char *prog, bfd *abfd, int from_tty)
4995 /* FIXME: The code below that sets a specific variant of the H8/300
4996 being simulated should be moved to sim_open(). */
4998 /* See if the file is for the H8/300 or H8/300H. */
4999 /* ??? This may not be the most efficient way. The z8k simulator
5000 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
5004 prog_bfd = bfd_openr (prog, NULL);
5005 if (prog_bfd != NULL)
5007 /* Set the cpu type. We ignore failure from bfd_check_format
5008 and bfd_openr as sim_load_file checks too. */
5009 if (bfd_check_format (prog_bfd, bfd_object))
5011 set_h8300h (bfd_get_mach (prog_bfd));
5015 /* If we're using gdb attached to the simulator, then we have to
5016 reallocate memory for the simulator.
5018 When gdb first starts, it calls fetch_registers (among other
5019 functions), which in turn calls init_pointers, which allocates
5022 The problem is when we do that, we don't know whether we're
5023 debugging an H8/300 or H8/300H program.
5025 This is the first point at which we can make that determination,
5026 so we just reallocate memory now; this will also allow us to handle
5027 switching between H8/300 and H8/300H programs without exiting
5030 if (h8300smode && !h8300_normal_mode)
5031 memory_size = H8300S_MSIZE;
5032 else if (h8300hmode && !h8300_normal_mode)
5033 memory_size = H8300H_MSIZE;
5035 memory_size = H8300_MSIZE;
5037 if (h8_get_memory_buf (sd))
5038 free (h8_get_memory_buf (sd));
5039 if (h8_get_cache_idx_buf (sd))
5040 free (h8_get_cache_idx_buf (sd));
5041 if (h8_get_eightbit_buf (sd))
5042 free (h8_get_eightbit_buf (sd));
5044 h8_set_memory_buf (sd, (unsigned char *)
5045 calloc (sizeof (char), memory_size));
5046 h8_set_cache_idx_buf (sd, (unsigned short *)
5047 calloc (sizeof (short), memory_size));
5048 sd->memory_size = memory_size;
5049 h8_set_eightbit_buf (sd, (unsigned char *) calloc (sizeof (char), 256));
5051 /* `msize' must be a power of two. */
5052 if ((memory_size & (memory_size - 1)) != 0)
5054 (*sim_callback->printf_filtered) (sim_callback,
5055 "sim_load: bad memory size.\n");
5058 h8_set_mask (sd, memory_size - 1);
5060 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
5061 sim_kind == SIM_OPEN_DEBUG,
5065 /* Close the bfd if we opened it. */
5066 if (abfd == NULL && prog_bfd != NULL)
5067 bfd_close (prog_bfd);
5071 /* Close the bfd if we opened it. */
5072 if (abfd == NULL && prog_bfd != NULL)
5073 bfd_close (prog_bfd);
5078 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
5085 h8_set_pc (sd, bfd_get_start_address (abfd));
5089 /* Command Line support. */
5092 /* Counting the no. of commandline arguments. */
5093 for (no_of_args = 0; argv[no_of_args] != NULL; no_of_args++)
5096 /* Allocating memory for the argv pointers. */
5097 h8_set_command_line (sd, (char **) malloc ((sizeof (char *))
5098 * (no_of_args + 1)));
5100 for (i = 0; i < no_of_args; i++)
5102 /* Copying the argument string. */
5103 h8_set_cmdline_arg (sd, i, (char *) strdup (argv[i]));
5105 h8_set_cmdline_arg (sd, i, NULL);