2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
28 #ifdef HAVE_SYS_PARAM_H
29 #include <sys/param.h>
34 #include "gdb/sim-h8300.h"
36 #include "sys/types.h"
37 #include "sim-options.h"
45 /* FIXME: Needs to live in header file.
46 This header should also include the things in remote-sim.h.
47 One could move this to remote-sim.h but this function isn't needed
49 static void set_simcache_size (SIM_DESC, int);
51 #define X(op, size) (op * 4 + size)
53 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
55 #define h8_opcodes ops
57 #include "opcode/h8300.h"
59 /* CPU data object: */
62 sim_state_initialize (SIM_DESC sd, sim_cpu *cpu)
64 /* FIXME: not really necessary, since sim_cpu_alloc calls zalloc. */
66 memset (&cpu->regs, 0, sizeof(cpu->regs));
67 cpu->regs[SBR_REGNUM] = 0xFFFFFF00;
69 cpu->delayed_branch = 0;
74 /* Initialize local simulator state. */
76 sd->sim_cache_size = 0;
82 memset (&cpu->stats, 0, sizeof (cpu->stats));
88 h8_get_pc (SIM_DESC sd)
90 return (STATE_CPU (sd, 0)) -> pc;
94 h8_set_pc (SIM_DESC sd, unsigned int val)
96 (STATE_CPU (sd, 0)) -> pc = val;
100 h8_get_ccr (SIM_DESC sd)
102 return (STATE_CPU (sd, 0)) -> regs[CCR_REGNUM];
106 h8_set_ccr (SIM_DESC sd, unsigned int val)
108 (STATE_CPU (sd, 0)) -> regs[CCR_REGNUM] = val;
112 h8_get_exr (SIM_DESC sd)
114 return (STATE_CPU (sd, 0)) -> regs[EXR_REGNUM];
118 h8_set_exr (SIM_DESC sd, unsigned int val)
120 (STATE_CPU (sd, 0)) -> regs[EXR_REGNUM] = val;
124 h8_get_sbr (SIM_DESC sd)
126 return (STATE_CPU (sd, 0)) -> regs[SBR_REGNUM];
130 h8_set_sbr (SIM_DESC sd, int val)
132 (STATE_CPU (sd, 0)) -> regs[SBR_REGNUM] = val;
136 h8_get_vbr (SIM_DESC sd)
138 return (STATE_CPU (sd, 0)) -> regs[VBR_REGNUM];
142 h8_set_vbr (SIM_DESC sd, int val)
144 (STATE_CPU (sd, 0)) -> regs[VBR_REGNUM] = val;
148 h8_get_cache_top (SIM_DESC sd)
150 return sd -> cache_top;
154 h8_set_cache_top (SIM_DESC sd, int val)
156 sd -> cache_top = val;
160 h8_get_mask (SIM_DESC sd)
162 return (STATE_CPU (sd, 0)) -> mask;
166 h8_set_mask (SIM_DESC sd, int val)
168 (STATE_CPU (sd, 0)) -> mask = val;
172 h8_get_exception (SIM_DESC sd)
174 return (STATE_CPU (sd, 0)) -> exception;
178 h8_set_exception (SIM_DESC sd, int val)
180 (STATE_CPU (sd, 0)) -> exception = val;
183 static enum h8300_sim_state
184 h8_get_state (SIM_DESC sd)
190 h8_set_state (SIM_DESC sd, enum h8300_sim_state val)
196 h8_get_cycles (SIM_DESC sd)
198 return (STATE_CPU (sd, 0)) -> regs[CYCLE_REGNUM];
202 h8_set_cycles (SIM_DESC sd, unsigned int val)
204 (STATE_CPU (sd, 0)) -> regs[CYCLE_REGNUM] = val;
208 h8_get_insts (SIM_DESC sd)
210 return (STATE_CPU (sd, 0)) -> regs[INST_REGNUM];
214 h8_set_insts (SIM_DESC sd, unsigned int val)
216 (STATE_CPU (sd, 0)) -> regs[INST_REGNUM] = val;
220 h8_get_ticks (SIM_DESC sd)
222 return (STATE_CPU (sd, 0)) -> regs[TICK_REGNUM];
226 h8_set_ticks (SIM_DESC sd, unsigned int val)
228 (STATE_CPU (sd, 0)) -> regs[TICK_REGNUM] = val;
232 h8_get_mach (SIM_DESC sd)
234 return (STATE_CPU (sd, 0)) -> regs[MACH_REGNUM];
238 h8_set_mach (SIM_DESC sd, unsigned int val)
240 (STATE_CPU (sd, 0)) -> regs[MACH_REGNUM] = val;
244 h8_get_macl (SIM_DESC sd)
246 return (STATE_CPU (sd, 0)) -> regs[MACL_REGNUM];
250 h8_set_macl (SIM_DESC sd, unsigned int val)
252 (STATE_CPU (sd, 0)) -> regs[MACL_REGNUM] = val;
256 h8_get_compiles (SIM_DESC sd)
258 return sd -> compiles;
262 h8_increment_compiles (SIM_DESC sd)
267 static unsigned int *
268 h8_get_reg_buf (SIM_DESC sd)
270 return &(((STATE_CPU (sd, 0)) -> regs)[0]);
274 h8_get_reg (SIM_DESC sd, int regnum)
276 return (STATE_CPU (sd, 0)) -> regs[regnum];
280 h8_set_reg (SIM_DESC sd, int regnum, int val)
282 (STATE_CPU (sd, 0)) -> regs[regnum] = val;
287 h8_get_stats (SIM_DESC sd, int idx)
289 return sd -> stats[idx];
293 h8_increment_stats (SIM_DESC sd, int idx)
299 static unsigned short *
300 h8_get_cache_idx_buf (SIM_DESC sd)
302 return sd -> cache_idx;
306 h8_set_cache_idx_buf (SIM_DESC sd, unsigned short *ptr)
308 sd -> cache_idx = ptr;
311 static unsigned short
312 h8_get_cache_idx (SIM_DESC sd, unsigned int idx)
314 if (idx > sd->memory_size)
315 return (unsigned short) -1;
316 return sd -> cache_idx[idx];
320 h8_set_cache_idx (SIM_DESC sd, int idx, unsigned int val)
322 sd -> cache_idx[idx] = (unsigned short) val;
325 static unsigned char *
326 h8_get_memory_buf (SIM_DESC sd)
328 return (STATE_CPU (sd, 0)) -> memory;
332 h8_set_memory_buf (SIM_DESC sd, unsigned char *ptr)
334 (STATE_CPU (sd, 0)) -> memory = ptr;
338 h8_get_memory (SIM_DESC sd, int idx)
340 return (STATE_CPU (sd, 0)) -> memory[idx];
344 h8_set_memory (SIM_DESC sd, int idx, unsigned int val)
346 (STATE_CPU (sd, 0)) -> memory[idx] = (unsigned char) val;
349 static unsigned char *
350 h8_get_eightbit_buf (SIM_DESC sd)
352 return (STATE_CPU (sd, 0)) -> eightbit;
356 h8_set_eightbit_buf (SIM_DESC sd, unsigned char *ptr)
358 (STATE_CPU (sd, 0)) -> eightbit = ptr;
362 h8_get_eightbit (SIM_DESC sd, int idx)
364 return (STATE_CPU (sd, 0)) -> eightbit[idx];
368 h8_set_eightbit (SIM_DESC sd, int idx, unsigned int val)
370 (STATE_CPU (sd, 0)) -> eightbit[idx] = (unsigned char) val;
374 h8_get_delayed_branch (SIM_DESC sd)
376 return (STATE_CPU (sd, 0)) -> delayed_branch;
380 h8_set_delayed_branch (SIM_DESC sd, unsigned int dest)
382 (STATE_CPU (sd, 0)) -> delayed_branch = dest;
386 h8_get_command_line (SIM_DESC sd)
388 return (STATE_CPU (sd, 0)) -> command_line;
392 h8_set_command_line (SIM_DESC sd, char ** val)
394 (STATE_CPU (sd, 0)) -> command_line = val;
398 h8_get_cmdline_arg (SIM_DESC sd, int index)
400 return (STATE_CPU (sd, 0)) -> command_line[index];
404 h8_set_cmdline_arg (SIM_DESC sd, int index, char * val)
406 (STATE_CPU (sd, 0)) -> command_line[index] = val;
409 /* MAC Saturation Mode */
411 h8_get_macS (SIM_DESC sd)
413 return (STATE_CPU (sd, 0)) -> macS;
417 h8_set_macS (SIM_DESC sd, int val)
419 (STATE_CPU (sd, 0)) -> macS = (val != 0);
424 h8_get_macZ (SIM_DESC sd)
426 return (STATE_CPU (sd, 0)) -> macZ;
430 h8_set_macZ (SIM_DESC sd, int val)
432 (STATE_CPU (sd, 0)) -> macZ = (val != 0);
435 /* MAC Negative Flag */
437 h8_get_macN (SIM_DESC sd)
439 return (STATE_CPU (sd, 0)) -> macN;
443 h8_set_macN (SIM_DESC sd, int val)
445 (STATE_CPU (sd, 0)) -> macN = (val != 0);
448 /* MAC Overflow Flag */
450 h8_get_macV (SIM_DESC sd)
452 return (STATE_CPU (sd, 0)) -> macV;
456 h8_set_macV (SIM_DESC sd, int val)
458 (STATE_CPU (sd, 0)) -> macV = (val != 0);
461 /* End CPU data object. */
463 /* The rate at which to call the host's poll_quit callback. */
465 enum { POLL_QUIT_INTERVAL = 0x80000 };
467 #define LOW_BYTE(x) ((x) & 0xff)
468 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
469 #define P(X, Y) ((X << 8) | Y)
478 #define I (intMaskBit != 0)
480 #define BUILDSR(SD) \
481 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
482 | (N << 3) | (Z << 2) | (V << 1) | C)
485 /* Get Status Register (flags). */ \
486 c = (h8_get_ccr (sd) >> 0) & 1; \
487 v = (h8_get_ccr (sd) >> 1) & 1; \
488 nz = !((h8_get_ccr (sd) >> 2) & 1); \
489 n = (h8_get_ccr (sd) >> 3) & 1; \
490 u = (h8_get_ccr (sd) >> 4) & 1; \
491 h = (h8_get_ccr (sd) >> 5) & 1; \
492 ui = ((h8_get_ccr (sd) >> 6) & 1); \
493 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
496 #ifdef __CHAR_IS_SIGNED__
497 #define SEXTCHAR(x) ((char) (x))
501 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
504 #define UEXTCHAR(x) ((x) & 0xff)
505 #define UEXTSHORT(x) ((x) & 0xffff)
506 #define SEXTSHORT(x) ((short) (x))
510 int h8300_normal_mode = 0;
513 static int memory_size;
518 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
540 return (h8300hmode && !h8300_normal_mode)? SL : SW;
545 /* Simulate an indirection / dereference.
546 return 0 for success, -1 for failure.
550 lvalue (SIM_DESC sd, int x, int rn, unsigned int *val)
552 if (val == NULL) /* Paranoia. */
558 if (rn == ZERO_REGNUM)
559 *val = X (OP_IMM, SP);
561 *val = X (OP_REG, SP);
564 *val = X (OP_MEM, SP);
567 sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
576 if (h8300smode && !h8300_normal_mode)
578 else if (h8300hmode && !h8300_normal_mode)
585 decode (SIM_DESC sd, int addr, unsigned char *data, decoded_inst *dst)
587 int cst[3] = {0, 0, 0};
588 int reg[3] = {0, 0, 0};
589 int rdisp[3] = {0, 0, 0};
591 const struct h8_opcode *q;
596 /* Find the exact opcode/arg combo. */
597 for (q = h8_opcodes; q->name; q++)
599 const op_type *nib = q->data.nib;
600 unsigned int len = 0;
602 if ((q->available == AV_H8SX && !h8300sxmode) ||
603 (q->available == AV_H8S && !h8300smode) ||
604 (q->available == AV_H8H && !h8300hmode))
607 cst[0] = cst[1] = cst[2] = 0;
608 reg[0] = reg[1] = reg[2] = 0;
609 rdisp[0] = rdisp[1] = rdisp[2] = 0;
613 op_type looking_for = *nib;
614 int thisnib = data[len / 2];
616 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
617 opnum = ((looking_for & OP3) ? 2 :
618 (looking_for & DST) ? 1 : 0);
620 if (looking_for < 16 && looking_for >= 0)
622 if (looking_for != thisnib)
627 if (looking_for & B31)
629 if (!((thisnib & 0x8) != 0))
632 looking_for = (op_type) (looking_for & ~B31);
635 else if (looking_for & B30)
637 if (!((thisnib & 0x8) == 0))
640 looking_for = (op_type) (looking_for & ~B30);
643 if (looking_for & B21)
645 if (!((thisnib & 0x4) != 0))
648 looking_for = (op_type) (looking_for & ~B21);
651 else if (looking_for & B20)
653 if (!((thisnib & 0x4) == 0))
656 looking_for = (op_type) (looking_for & ~B20);
659 if (looking_for & B11)
661 if (!((thisnib & 0x2) != 0))
664 looking_for = (op_type) (looking_for & ~B11);
667 else if (looking_for & B10)
669 if (!((thisnib & 0x2) == 0))
672 looking_for = (op_type) (looking_for & ~B10);
675 if (looking_for & B01)
677 if (!((thisnib & 0x1) != 0))
680 looking_for = (op_type) (looking_for & ~B01);
683 else if (looking_for & B00)
685 if (!((thisnib & 0x1) == 0))
688 looking_for = (op_type) (looking_for & ~B00);
691 if (looking_for & IGNORE)
693 /* Hitachi has declared that IGNORE must be zero. */
697 else if ((looking_for & MODE) == DATA)
699 ; /* Skip embedded data. */
701 else if ((looking_for & MODE) == DBIT)
703 /* Exclude adds/subs by looking at bit 0 and 2, and
704 make sure the operand size, either w or l,
705 matches by looking at bit 1. */
706 if ((looking_for & 7) != (thisnib & 7))
709 cst[opnum] = (thisnib & 0x8) ? 2 : 1;
711 else if ((looking_for & MODE) == REG ||
712 (looking_for & MODE) == LOWREG ||
713 (looking_for & MODE) == IND ||
714 (looking_for & MODE) == PREINC ||
715 (looking_for & MODE) == POSTINC ||
716 (looking_for & MODE) == PREDEC ||
717 (looking_for & MODE) == POSTDEC)
719 reg[opnum] = thisnib;
721 else if (looking_for & CTRL)
724 if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) ||
725 ((looking_for & MODE) == EXR && (thisnib != C_EXR)) ||
726 ((looking_for & MODE) == MACH && (thisnib != C_MACH)) ||
727 ((looking_for & MODE) == MACL && (thisnib != C_MACL)) ||
728 ((looking_for & MODE) == VBR && (thisnib != C_VBR)) ||
729 ((looking_for & MODE) == SBR && (thisnib != C_SBR)))
731 if (((looking_for & MODE) == CCR_EXR &&
732 (thisnib != C_CCR && thisnib != C_EXR)) ||
733 ((looking_for & MODE) == VBR_SBR &&
734 (thisnib != C_VBR && thisnib != C_SBR)) ||
735 ((looking_for & MODE) == MACREG &&
736 (thisnib != C_MACH && thisnib != C_MACL)))
738 if (((looking_for & MODE) == CC_EX_VB_SB &&
739 (thisnib != C_CCR && thisnib != C_EXR &&
740 thisnib != C_VBR && thisnib != C_SBR)))
743 reg[opnum] = thisnib;
745 else if ((looking_for & MODE) == ABS)
747 /* Absolute addresses are unsigned. */
748 switch (looking_for & SIZE)
751 cst[opnum] = UEXTCHAR (data[len / 2]);
755 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
759 (data[len / 2 + 0] << 24) +
760 (data[len / 2 + 1] << 16) +
761 (data[len / 2 + 2] << 8) +
765 printf ("decode: bad size ABS: %d\n",
766 (looking_for & SIZE));
770 else if ((looking_for & MODE) == DISP ||
771 (looking_for & MODE) == PCREL ||
772 (looking_for & MODE) == INDEXB ||
773 (looking_for & MODE) == INDEXW ||
774 (looking_for & MODE) == INDEXL)
776 switch (looking_for & SIZE)
779 cst[opnum] = thisnib & 3;
782 cst[opnum] = SEXTCHAR (data[len / 2]);
785 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
786 cst[opnum] = (short) cst[opnum]; /* Sign extend. */
789 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
793 (data[len / 2 + 0] << 24) +
794 (data[len / 2 + 1] << 16) +
795 (data[len / 2 + 2] << 8) +
799 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
800 (looking_for & SIZE));
804 else if ((looking_for & SIZE) == L_16 ||
805 (looking_for & SIZE) == L_16U)
807 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
808 /* Immediates are always unsigned. */
809 if ((looking_for & SIZE) != L_16U &&
810 (looking_for & MODE) != IMM)
811 cst[opnum] = (short) cst[opnum]; /* Sign extend. */
813 else if (looking_for & ABSJMP)
815 switch (looking_for & SIZE) {
817 cst[opnum] = (data[1] << 16) | (data[2] << 8) | (data[3]);
821 (data[len / 2 + 0] << 24) +
822 (data[len / 2 + 1] << 16) +
823 (data[len / 2 + 2] << 8) +
827 printf ("decode: bad size ABSJMP: %d\n",
828 (looking_for & SIZE));
832 else if ((looking_for & MODE) == MEMIND)
834 cst[opnum] = data[1];
836 else if ((looking_for & MODE) == VECIND)
838 if(h8300_normal_mode)
839 cst[opnum] = ((data[1] & 0x7f) + 0x80) * 2;
841 cst[opnum] = ((data[1] & 0x7f) + 0x80) * 4;
842 cst[opnum] += h8_get_vbr (sd); /* Add vector base reg. */
844 else if ((looking_for & SIZE) == L_32)
849 (data[i + 0] << 24) |
850 (data[i + 1] << 16) |
854 else if ((looking_for & SIZE) == L_24)
859 (data[i + 0] << 16) |
863 else if (looking_for & DISPREG)
865 rdisp[opnum] = thisnib & 0x7;
867 else if ((looking_for & MODE) == KBIT)
884 else if ((looking_for & SIZE) == L_8)
886 if ((looking_for & MODE) == ABS)
888 /* Will be combined with contents of SBR_REGNUM
889 by fetch (). For all modes except h8sx, this
890 will always contain the value 0xFFFFFF00. */
891 cst[opnum] = data[len / 2] & 0xff;
895 cst[opnum] = data[len / 2] & 0xff;
898 else if ((looking_for & SIZE) == L_2)
900 cst[opnum] = thisnib & 3;
902 else if ((looking_for & SIZE) == L_3 ||
903 (looking_for & SIZE) == L_3NZ)
905 cst[opnum] = thisnib & 7;
906 if (cst[opnum] == 0 && (looking_for & SIZE) == L_3NZ)
909 else if ((looking_for & SIZE) == L_4)
911 cst[opnum] = thisnib & 15;
913 else if ((looking_for & SIZE) == L_5)
915 cst[opnum] = data[len / 2] & 0x1f;
917 else if (looking_for == E)
922 /* Fill in the args. */
924 const op_type *args = q->args.nib;
929 nargs < 3 && *args != E;
935 opnum = ((x & OP3) ? 2 :
944 if ((x & MODE) == IMM ||
945 (x & MODE) == KBIT ||
948 /* Use the instruction to determine
950 p->type = X (OP_IMM, OP_SIZE (q->how));
951 p->literal = cst[opnum];
953 else if ((x & MODE) == CONST_2 ||
954 (x & MODE) == CONST_4 ||
955 (x & MODE) == CONST_8 ||
956 (x & MODE) == CONST_16)
958 /* Use the instruction to determine
960 p->type = X (OP_IMM, OP_SIZE (q->how));
962 case CONST_2: p->literal = 2; break;
963 case CONST_4: p->literal = 4; break;
964 case CONST_8: p->literal = 8; break;
965 case CONST_16: p->literal = 16; break;
968 else if ((x & MODE) == REG)
970 p->type = X (OP_REG, bitfrom (x));
973 else if ((x & MODE) == LOWREG)
975 p->type = X (OP_LOWREG, bitfrom (x));
978 else if ((x & MODE) == PREINC)
980 /* Use the instruction to determine
982 p->type = X (OP_PREINC, OP_SIZE (q->how));
983 p->reg = reg[opnum] & 0x7;
985 else if ((x & MODE) == POSTINC)
987 /* Use the instruction to determine
989 p->type = X (OP_POSTINC, OP_SIZE (q->how));
990 p->reg = reg[opnum] & 0x7;
992 else if ((x & MODE) == PREDEC)
994 /* Use the instruction to determine
996 p->type = X (OP_PREDEC, OP_SIZE (q->how));
997 p->reg = reg[opnum] & 0x7;
999 else if ((x & MODE) == POSTDEC)
1001 /* Use the instruction to determine
1002 the operand size. */
1003 p->type = X (OP_POSTDEC, OP_SIZE (q->how));
1004 p->reg = reg[opnum] & 0x7;
1006 else if ((x & MODE) == IND)
1008 /* Note: an indirect is transformed into
1009 a displacement of zero.
1011 /* Use the instruction to determine
1012 the operand size. */
1013 p->type = X (OP_DISP, OP_SIZE (q->how));
1014 p->reg = reg[opnum] & 0x7;
1016 if (OP_KIND (q->how) == O_JSR ||
1017 OP_KIND (q->how) == O_JMP)
1018 if (lvalue (sd, p->type, p->reg, (unsigned int *)&p->type))
1021 else if ((x & MODE) == ABS)
1023 /* Note: a 16 or 32 bit ABS is transformed into a
1024 displacement from pseudo-register ZERO_REGNUM,
1025 which is always zero. An 8 bit ABS becomes
1026 a displacement from SBR_REGNUM.
1028 /* Use the instruction to determine
1029 the operand size. */
1030 p->type = X (OP_DISP, OP_SIZE (q->how));
1031 p->literal = cst[opnum];
1033 /* 8-bit ABS is displacement from SBR.
1034 16 and 32-bit ABS are displacement from ZERO.
1035 (SBR will always be zero except for h8/sx)
1037 if ((x & SIZE) == L_8)
1038 p->reg = SBR_REGNUM;
1040 p->reg = ZERO_REGNUM;;
1042 else if ((x & MODE) == MEMIND ||
1043 (x & MODE) == VECIND)
1045 /* Size doesn't matter. */
1046 p->type = X (OP_MEM, SB);
1047 p->literal = cst[opnum];
1048 if (OP_KIND (q->how) == O_JSR ||
1049 OP_KIND (q->how) == O_JMP)
1050 if (lvalue (sd, p->type, p->reg, (unsigned int *)&p->type))
1053 else if ((x & MODE) == PCREL)
1055 /* Size doesn't matter. */
1056 p->type = X (OP_PCREL, SB);
1057 p->literal = cst[opnum];
1059 else if (x & ABSJMP)
1061 p->type = X (OP_IMM, SP);
1062 p->literal = cst[opnum];
1064 else if ((x & MODE) == INDEXB)
1066 p->type = X (OP_INDEXB, OP_SIZE (q->how));
1067 p->literal = cst[opnum];
1068 p->reg = rdisp[opnum];
1070 else if ((x & MODE) == INDEXW)
1072 p->type = X (OP_INDEXW, OP_SIZE (q->how));
1073 p->literal = cst[opnum];
1074 p->reg = rdisp[opnum];
1076 else if ((x & MODE) == INDEXL)
1078 p->type = X (OP_INDEXL, OP_SIZE (q->how));
1079 p->literal = cst[opnum];
1080 p->reg = rdisp[opnum];
1082 else if ((x & MODE) == DISP)
1084 /* Yuck -- special for mova args. */
1085 if (strncmp (q->name, "mova", 4) == 0 &&
1088 /* Mova can have a DISP2 dest, with an
1089 INDEXB or INDEXW src. The multiplier
1090 for the displacement value is determined
1091 by the src operand, not by the insn. */
1093 switch (OP_KIND (dst->src.type))
1096 p->type = X (OP_DISP, SB);
1097 p->literal = cst[opnum];
1100 p->type = X (OP_DISP, SW);
1101 p->literal = cst[opnum] * 2;
1109 p->type = X (OP_DISP, OP_SIZE (q->how));
1110 p->literal = cst[opnum];
1111 /* DISP2 is special. */
1112 if ((x & SIZE) == L_2)
1113 switch (OP_SIZE (q->how))
1116 case SW: p->literal *= 2; break;
1117 case SL: p->literal *= 4; break;
1120 p->reg = rdisp[opnum];
1127 p->type = X (OP_CCR, SB);
1130 p->type = X (OP_EXR, SB);
1133 p->type = X (OP_MACH, SL);
1136 p->type = X (OP_MACL, SL);
1139 p->type = X (OP_VBR, SL);
1142 p->type = X (OP_SBR, SL);
1146 else if ((x & MODE) == CCR)
1150 else if ((x & MODE) == EXR)
1155 printf ("Hmmmm 0x%x...\n", x);
1161 /* Unary operators: treat src and dst as equivalent. */
1162 if (dst->dst.type == -1)
1163 dst->dst = dst->src;
1164 if (dst->src.type == -1)
1165 dst->src = dst->dst;
1167 dst->opcode = q->how;
1168 dst->cycles = q->time;
1170 /* And jsr's to these locations are turned into
1173 if (OP_KIND (dst->opcode) == O_JSR)
1175 switch (dst->src.literal)
1178 dst->opcode = O (O_SYS_OPEN, SB);
1181 dst->opcode = O (O_SYS_READ, SB);
1184 dst->opcode = O (O_SYS_WRITE, SB);
1187 dst->opcode = O (O_SYS_LSEEK, SB);
1190 dst->opcode = O (O_SYS_CLOSE, SB);
1193 dst->opcode = O (O_SYS_STAT, SB);
1196 dst->opcode = O (O_SYS_FSTAT, SB);
1199 dst->opcode = O (O_SYS_CMDLINE, SB);
1202 /* End of Processing for system calls. */
1205 dst->next_pc = addr + len / 2;
1209 printf ("Don't understand 0x%x \n", looking_for);
1220 /* Fell off the end. */
1221 dst->opcode = O (O_ILL, SB);
1225 compile (SIM_DESC sd, int pc)
1229 /* Find the next cache entry to use. */
1230 idx = h8_get_cache_top (sd) + 1;
1231 h8_increment_compiles (sd);
1232 if (idx >= sd->sim_cache_size)
1236 h8_set_cache_top (sd, idx);
1238 /* Throw away its old meaning. */
1239 h8_set_cache_idx (sd, sd->sim_cache[idx].oldpc, 0);
1241 /* Set to new address. */
1242 sd->sim_cache[idx].oldpc = pc;
1244 /* Fill in instruction info. */
1245 decode (sd, pc, h8_get_memory_buf (sd) + pc, sd->sim_cache + idx);
1247 /* Point to new cache entry. */
1248 h8_set_cache_idx (sd, pc, idx);
1252 static unsigned char *breg[32];
1253 static unsigned short *wreg[16];
1255 #define GET_B_REG(X) *(breg[X])
1256 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1257 #define GET_W_REG(X) *(wreg[X])
1258 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1259 #define GET_L_REG(X) h8_get_reg (sd, X)
1260 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1262 #define GET_MEMORY_L(X) \
1263 ((X) < memory_size \
1264 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1265 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1266 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 24) \
1267 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 16) \
1268 | (h8_get_eightbit (sd, ((X)+2) & 0xff) << 8) \
1269 | (h8_get_eightbit (sd, ((X)+3) & 0xff) << 0)))
1271 #define GET_MEMORY_W(X) \
1272 ((X) < memory_size \
1273 ? ((h8_get_memory (sd, (X)+0) << 8) \
1274 | (h8_get_memory (sd, (X)+1) << 0)) \
1275 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 8) \
1276 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 0)))
1279 #define GET_MEMORY_B(X) \
1280 ((X) < memory_size ? (h8_get_memory (sd, (X))) \
1281 : (h8_get_eightbit (sd, (X) & 0xff)))
1283 #define SET_MEMORY_L(X, Y) \
1284 { register unsigned char *_p; register int __y = (Y); \
1285 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1286 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1287 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1288 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1291 #define SET_MEMORY_W(X, Y) \
1292 { register unsigned char *_p; register int __y = (Y); \
1293 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1294 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1295 _p[0] = __y >> 8; _p[1] = __y; \
1298 #define SET_MEMORY_B(X, Y) \
1299 ((X) < memory_size ? (h8_set_memory (sd, (X), (Y))) \
1300 : (h8_set_eightbit (sd, (X) & 0xff, (Y))))
1302 /* Simulate a memory fetch.
1303 Return 0 for success, -1 for failure.
1307 fetch_1 (SIM_DESC sd, ea_type *arg, int *val, int twice)
1310 int abs = arg->literal;
1315 return -1; /* Paranoia. */
1319 /* Indexed register plus displacement mode:
1321 This new family of addressing modes are similar to OP_DISP
1322 (register plus displacement), with two differences:
1323 1) INDEXB uses only the least significant byte of the register,
1324 INDEXW uses only the least significant word, and
1325 INDEXL uses the entire register (just like OP_DISP).
1327 2) The displacement value in abs is multiplied by two
1328 for SW-sized operations, and by four for SL-size.
1330 This gives nine possible variations.
1333 case X (OP_INDEXB, SB):
1334 case X (OP_INDEXB, SW):
1335 case X (OP_INDEXB, SL):
1336 case X (OP_INDEXW, SB):
1337 case X (OP_INDEXW, SW):
1338 case X (OP_INDEXW, SL):
1339 case X (OP_INDEXL, SB):
1340 case X (OP_INDEXL, SW):
1341 case X (OP_INDEXL, SL):
1343 switch (OP_KIND (arg->type)) {
1344 case OP_INDEXB: t &= 0xff; break;
1345 case OP_INDEXW: t &= 0xffff; break;
1349 switch (OP_SIZE (arg->type)) {
1351 *val = GET_MEMORY_B ((t * 1 + abs) & h8_get_mask (sd));
1354 *val = GET_MEMORY_W ((t * 2 + abs) & h8_get_mask (sd));
1357 *val = GET_MEMORY_L ((t * 4 + abs) & h8_get_mask (sd));
1362 case X (OP_LOWREG, SB):
1363 *val = GET_L_REG (rn) & 0xff;
1365 case X (OP_LOWREG, SW):
1366 *val = GET_L_REG (rn) & 0xffff;
1369 case X (OP_REG, SB): /* Register direct, byte. */
1370 *val = GET_B_REG (rn);
1372 case X (OP_REG, SW): /* Register direct, word. */
1373 *val = GET_W_REG (rn);
1375 case X (OP_REG, SL): /* Register direct, long. */
1376 *val = GET_L_REG (rn);
1378 case X (OP_IMM, SB): /* Immediate, byte. */
1379 case X (OP_IMM, SW): /* Immediate, word. */
1380 case X (OP_IMM, SL): /* Immediate, long. */
1383 case X (OP_POSTINC, SB): /* Register indirect w/post-incr: byte. */
1385 r = GET_MEMORY_B (t & h8_get_mask (sd));
1391 case X (OP_POSTINC, SW): /* Register indirect w/post-incr: word. */
1393 r = GET_MEMORY_W (t & h8_get_mask (sd));
1399 case X (OP_POSTINC, SL): /* Register indirect w/post-incr: long. */
1401 r = GET_MEMORY_L (t & h8_get_mask (sd));
1408 case X (OP_POSTDEC, SB): /* Register indirect w/post-decr: byte. */
1410 r = GET_MEMORY_B (t & h8_get_mask (sd));
1416 case X (OP_POSTDEC, SW): /* Register indirect w/post-decr: word. */
1418 r = GET_MEMORY_W (t & h8_get_mask (sd));
1424 case X (OP_POSTDEC, SL): /* Register indirect w/post-decr: long. */
1426 r = GET_MEMORY_L (t & h8_get_mask (sd));
1433 case X (OP_PREDEC, SB): /* Register indirect w/pre-decr: byte. */
1434 t = GET_L_REG (rn) - 1;
1436 t &= h8_get_mask (sd);
1437 *val = GET_MEMORY_B (t);
1440 case X (OP_PREDEC, SW): /* Register indirect w/pre-decr: word. */
1441 t = GET_L_REG (rn) - 2;
1443 t &= h8_get_mask (sd);
1444 *val = GET_MEMORY_W (t);
1447 case X (OP_PREDEC, SL): /* Register indirect w/pre-decr: long. */
1448 t = GET_L_REG (rn) - 4;
1450 t &= h8_get_mask (sd);
1451 *val = GET_MEMORY_L (t);
1454 case X (OP_PREINC, SB): /* Register indirect w/pre-incr: byte. */
1455 t = GET_L_REG (rn) + 1;
1457 t &= h8_get_mask (sd);
1458 *val = GET_MEMORY_B (t);
1461 case X (OP_PREINC, SW): /* Register indirect w/pre-incr: long. */
1462 t = GET_L_REG (rn) + 2;
1464 t &= h8_get_mask (sd);
1465 *val = GET_MEMORY_W (t);
1468 case X (OP_PREINC, SL): /* Register indirect w/pre-incr: long. */
1469 t = GET_L_REG (rn) + 4;
1471 t &= h8_get_mask (sd);
1472 *val = GET_MEMORY_L (t);
1475 case X (OP_DISP, SB): /* Register indirect w/displacement: byte. */
1476 t = GET_L_REG (rn) + abs;
1477 t &= h8_get_mask (sd);
1478 *val = GET_MEMORY_B (t);
1481 case X (OP_DISP, SW): /* Register indirect w/displacement: word. */
1482 t = GET_L_REG (rn) + abs;
1483 t &= h8_get_mask (sd);
1484 *val = GET_MEMORY_W (t);
1487 case X (OP_DISP, SL): /* Register indirect w/displacement: long. */
1488 t = GET_L_REG (rn) + abs;
1489 t &= h8_get_mask (sd);
1490 *val =GET_MEMORY_L (t);
1493 case X (OP_MEM, SL): /* Absolute memory address, long. */
1494 t = GET_MEMORY_L (abs);
1495 t &= h8_get_mask (sd);
1499 case X (OP_MEM, SW): /* Absolute memory address, word. */
1500 t = GET_MEMORY_W (abs);
1501 t &= h8_get_mask (sd);
1505 case X (OP_PCREL, SB): /* PC relative (for jump, branch etc). */
1506 case X (OP_PCREL, SW):
1507 case X (OP_PCREL, SL):
1508 case X (OP_PCREL, SN):
1512 case X (OP_MEM, SB): /* Why isn't this implemented? */
1514 sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
1517 return 0; /* Success. */
1523 fetch (SIM_DESC sd, ea_type *arg, int *val)
1525 return fetch_1 (sd, arg, val, 0);
1528 /* Fetch which will be followed by a store to the same location.
1529 The difference being that we don't want to do a post-increment
1530 or post-decrement at this time: we'll do it when we store. */
1533 fetch2 (SIM_DESC sd, ea_type *arg, int *val)
1535 return fetch_1 (sd, arg, val, 1);
1538 /* Simulate a memory store.
1539 Return 0 for success, -1 for failure.
1543 store_1 (SIM_DESC sd, ea_type *arg, int n, int twice)
1546 int abs = arg->literal;
1551 /* Indexed register plus displacement mode:
1553 This new family of addressing modes are similar to OP_DISP
1554 (register plus displacement), with two differences:
1555 1) INDEXB uses only the least significant byte of the register,
1556 INDEXW uses only the least significant word, and
1557 INDEXL uses the entire register (just like OP_DISP).
1559 2) The displacement value in abs is multiplied by two
1560 for SW-sized operations, and by four for SL-size.
1562 This gives nine possible variations.
1565 case X (OP_INDEXB, SB):
1566 case X (OP_INDEXB, SW):
1567 case X (OP_INDEXB, SL):
1568 case X (OP_INDEXW, SB):
1569 case X (OP_INDEXW, SW):
1570 case X (OP_INDEXW, SL):
1571 case X (OP_INDEXL, SB):
1572 case X (OP_INDEXL, SW):
1573 case X (OP_INDEXL, SL):
1575 switch (OP_KIND (arg->type)) {
1576 case OP_INDEXB: t &= 0xff; break;
1577 case OP_INDEXW: t &= 0xffff; break;
1581 switch (OP_SIZE (arg->type)) {
1583 SET_MEMORY_B ((t * 1 + abs) & h8_get_mask (sd), n);
1586 SET_MEMORY_W ((t * 2 + abs) & h8_get_mask (sd), n);
1589 SET_MEMORY_L ((t * 4 + abs) & h8_get_mask (sd), n);
1594 case X (OP_REG, SB): /* Register direct, byte. */
1597 case X (OP_REG, SW): /* Register direct, word. */
1600 case X (OP_REG, SL): /* Register direct, long. */
1604 case X (OP_PREDEC, SB): /* Register indirect w/pre-decr, byte. */
1609 t &= h8_get_mask (sd);
1610 SET_MEMORY_B (t, n);
1613 case X (OP_PREDEC, SW): /* Register indirect w/pre-decr, word. */
1618 t &= h8_get_mask (sd);
1619 SET_MEMORY_W (t, n);
1622 case X (OP_PREDEC, SL): /* Register indirect w/pre-decr, long. */
1627 t &= h8_get_mask (sd);
1628 SET_MEMORY_L (t, n);
1631 case X (OP_PREINC, SB): /* Register indirect w/pre-incr, byte. */
1636 t &= h8_get_mask (sd);
1637 SET_MEMORY_B (t, n);
1640 case X (OP_PREINC, SW): /* Register indirect w/pre-incr, word. */
1645 t &= h8_get_mask (sd);
1646 SET_MEMORY_W (t, n);
1649 case X (OP_PREINC, SL): /* Register indirect w/pre-incr, long. */
1654 t &= h8_get_mask (sd);
1655 SET_MEMORY_L (t, n);
1658 case X (OP_POSTDEC, SB): /* Register indirect w/post-decr, byte. */
1660 SET_L_REG (rn, t - 1);
1661 t &= h8_get_mask (sd);
1662 SET_MEMORY_B (t, n);
1665 case X (OP_POSTDEC, SW): /* Register indirect w/post-decr, word. */
1667 SET_L_REG (rn, t - 2);
1668 t &= h8_get_mask (sd);
1669 SET_MEMORY_W (t, n);
1672 case X (OP_POSTDEC, SL): /* Register indirect w/post-decr, long. */
1674 SET_L_REG (rn, t - 4);
1675 t &= h8_get_mask (sd);
1676 SET_MEMORY_L (t, n);
1679 case X (OP_POSTINC, SB): /* Register indirect w/post-incr, byte. */
1681 SET_L_REG (rn, t + 1);
1682 t &= h8_get_mask (sd);
1683 SET_MEMORY_B (t, n);
1686 case X (OP_POSTINC, SW): /* Register indirect w/post-incr, word. */
1688 SET_L_REG (rn, t + 2);
1689 t &= h8_get_mask (sd);
1690 SET_MEMORY_W (t, n);
1693 case X (OP_POSTINC, SL): /* Register indirect w/post-incr, long. */
1695 SET_L_REG (rn, t + 4);
1696 t &= h8_get_mask (sd);
1697 SET_MEMORY_L (t, n);
1700 case X (OP_DISP, SB): /* Register indirect w/displacement, byte. */
1701 t = GET_L_REG (rn) + abs;
1702 t &= h8_get_mask (sd);
1703 SET_MEMORY_B (t, n);
1706 case X (OP_DISP, SW): /* Register indirect w/displacement, word. */
1707 t = GET_L_REG (rn) + abs;
1708 t &= h8_get_mask (sd);
1709 SET_MEMORY_W (t, n);
1712 case X (OP_DISP, SL): /* Register indirect w/displacement, long. */
1713 t = GET_L_REG (rn) + abs;
1714 t &= h8_get_mask (sd);
1715 SET_MEMORY_L (t, n);
1719 case X (OP_MEM, SB): /* Why isn't this implemented? */
1720 case X (OP_MEM, SW): /* Why isn't this implemented? */
1721 case X (OP_MEM, SL): /* Why isn't this implemented? */
1723 sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
1732 store (SIM_DESC sd, ea_type *arg, int n)
1734 return store_1 (sd, arg, n, 0);
1737 /* Store which follows a fetch from the same location.
1738 The difference being that we don't want to do a pre-increment
1739 or pre-decrement at this time: it was already done when we fetched. */
1742 store2 (SIM_DESC sd, ea_type *arg, int n)
1744 return store_1 (sd, arg, n, 1);
1747 /* Flag to be set whenever a new SIM_DESC object is created. */
1748 static int init_pointers_needed = 1;
1751 init_pointers (SIM_DESC sd)
1753 if (init_pointers_needed)
1757 if (h8300smode && !h8300_normal_mode)
1758 memory_size = H8300S_MSIZE;
1759 else if (h8300hmode && !h8300_normal_mode)
1760 memory_size = H8300H_MSIZE;
1762 memory_size = H8300_MSIZE;
1763 /* `msize' must be a power of two. */
1764 if ((memory_size & (memory_size - 1)) != 0)
1768 "init_pointers: bad memory size %d, defaulting to %d.\n",
1769 memory_size, memory_size = H8300S_MSIZE);
1772 if (h8_get_memory_buf (sd))
1773 free (h8_get_memory_buf (sd));
1774 if (h8_get_cache_idx_buf (sd))
1775 free (h8_get_cache_idx_buf (sd));
1776 if (h8_get_eightbit_buf (sd))
1777 free (h8_get_eightbit_buf (sd));
1779 h8_set_memory_buf (sd, (unsigned char *)
1780 calloc (sizeof (char), memory_size));
1781 h8_set_cache_idx_buf (sd, (unsigned short *)
1782 calloc (sizeof (short), memory_size));
1783 sd->memory_size = memory_size;
1784 h8_set_eightbit_buf (sd, (unsigned char *) calloc (sizeof (char), 256));
1786 h8_set_mask (sd, memory_size - 1);
1788 memset (h8_get_reg_buf (sd), 0, sizeof (((STATE_CPU (sd, 0))->regs)));
1790 for (i = 0; i < 8; i++)
1792 /* FIXME: rewrite using local buffer. */
1793 unsigned char *p = (unsigned char *) (h8_get_reg_buf (sd) + i);
1794 unsigned char *e = (unsigned char *) (h8_get_reg_buf (sd) + i + 1);
1795 unsigned short *q = (unsigned short *) (h8_get_reg_buf (sd) + i);
1796 unsigned short *u = (unsigned short *) (h8_get_reg_buf (sd) + i + 1);
1797 h8_set_reg (sd, i, 0x00112233);
1812 wreg[i] = wreg[i + 8] = 0;
1826 if (wreg[i] == 0 || wreg[i + 8] == 0)
1827 sim_io_printf (sd, "init_pointers: internal error.\n");
1829 h8_set_reg (sd, i, 0);
1832 init_pointers_needed = 0;
1834 /* Initialize the seg registers. */
1836 set_simcache_size (sd, CSIZE);
1840 #define OBITOP(name, f, s, op) \
1841 case O (name, SB): \
1846 if (fetch (sd, &code->dst, &ea)) \
1848 if (fetch (sd, &code->src, &tmp)) \
1850 m = 1 << (tmp & 7); \
1853 if (store (sd, &code->dst,ea)) \
1859 sim_resume (SIM_DESC sd, int step, int siggnal)
1864 int tick_start = get_now ();
1872 int c, nz, v, n, u, h, ui, intMaskBit;
1875 enum sim_stop reason;
1877 host_callback *sim_callback = STATE_CALLBACK (sd);
1883 sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
1887 sim_engine_set_run_state (sd, sim_running, 0);
1890 pc = h8_get_pc (sd);
1892 /* The PC should never be odd. */
1895 sim_engine_set_run_state (sd, sim_stopped, SIGBUS);
1899 /* Get Status Register (flags). */
1902 if (h8300smode) /* Get exr. */
1904 trace = (h8_get_exr (sd) >> 7) & 1;
1905 intMask = h8_get_exr (sd) & 7;
1908 oldmask = h8_get_mask (sd);
1909 if (!h8300hmode || h8300_normal_mode)
1910 h8_set_mask (sd, 0xffff);
1913 unsigned short cidx;
1917 cidx = h8_get_cache_idx (sd, pc);
1918 if (cidx == (unsigned short) -1 ||
1919 cidx >= sd->sim_cache_size)
1922 code = sd->sim_cache + cidx;
1927 printf ("%x %d %s\n", pc, code->opcode,
1928 code->op ? code->op->name : "**");
1930 h8_increment_stats (sd, code->opcode);
1935 cycles += code->cycles;
1939 switch (code->opcode)
1943 * This opcode is a fake for when we get to an
1944 * instruction which hasnt been compiled
1950 case O (O_MOVAB, SL):
1951 case O (O_MOVAW, SL):
1952 case O (O_MOVAL, SL):
1953 /* 1) Evaluate 2nd argument (dst).
1954 2) Mask / zero extend according to whether 1st argument (src)
1955 is INDEXB, INDEXW, or INDEXL.
1956 3) Left-shift the result by 0, 1 or 2, according to size of mova
1957 (mova/b, mova/w, mova/l).
1958 4) Add literal value of 1st argument (src).
1959 5) Store result in 3rd argument (op3).
1962 /* Alas, since this is the only instruction with 3 arguments,
1963 decode doesn't handle them very well. Some fix-up is required.
1965 a) The size of dst is determined by whether src is
1966 INDEXB or INDEXW. */
1968 if (OP_KIND (code->src.type) == OP_INDEXB)
1969 code->dst.type = X (OP_KIND (code->dst.type), SB);
1970 else if (OP_KIND (code->src.type) == OP_INDEXW)
1971 code->dst.type = X (OP_KIND (code->dst.type), SW);
1973 /* b) If op3 == null, then this is the short form of the insn.
1974 Dst is the dispreg of src, and op3 is the 32-bit form
1975 of the same register.
1978 if (code->op3.type == 0)
1980 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1981 We get to compose dst and op3 as follows:
1983 op3 is a 32-bit register, ID == src.reg.
1984 dst is the same register, but 8 or 16 bits
1985 depending on whether src is INDEXB or INDEXW.
1988 code->op3.type = X (OP_REG, SL);
1989 code->op3.reg = code->src.reg;
1990 code->op3.literal = 0;
1992 if (OP_KIND (code->src.type) == OP_INDEXB)
1994 code->dst.type = X (OP_REG, SB);
1995 code->dst.reg = code->op3.reg + 8;
1998 code->dst.type = X (OP_REG, SW);
2001 if (fetch (sd, &code->dst, &ea))
2004 switch (OP_KIND (code->src.type)) {
2005 case OP_INDEXB: ea = ea & 0xff; break;
2006 case OP_INDEXW: ea = ea & 0xffff; break;
2007 case OP_INDEXL: break;
2008 default: goto illegal;
2011 switch (code->opcode) {
2012 case O (O_MOVAB, SL): break;
2013 case O (O_MOVAW, SL): ea = ea << 1; break;
2014 case O (O_MOVAL, SL): ea = ea << 2; break;
2015 default: goto illegal;
2018 ea = ea + code->src.literal;
2020 if (store (sd, &code->op3, ea))
2025 case O (O_SUBX, SB): /* subx, extended sub */
2026 if (fetch2 (sd, &code->dst, &rd))
2028 if (fetch (sd, &code->src, &ea))
2034 case O (O_SUBX, SW): /* subx, extended sub */
2035 if (fetch2 (sd, &code->dst, &rd))
2037 if (fetch (sd, &code->src, &ea))
2043 case O (O_SUBX, SL): /* subx, extended sub */
2044 if (fetch2 (sd, &code->dst, &rd))
2046 if (fetch (sd, &code->src, &ea))
2052 case O (O_ADDX, SB): /* addx, extended add */
2053 if (fetch2 (sd, &code->dst, &rd))
2055 if (fetch (sd, &code->src, &ea))
2061 case O (O_ADDX, SW): /* addx, extended add */
2062 if (fetch2 (sd, &code->dst, &rd))
2064 if (fetch (sd, &code->src, &ea))
2070 case O (O_ADDX, SL): /* addx, extended add */
2071 if (fetch2 (sd, &code->dst, &rd))
2073 if (fetch (sd, &code->src, &ea))
2079 case O (O_SUB, SB): /* sub.b */
2080 /* Fetch rd and ea. */
2081 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2087 case O (O_SUB, SW): /* sub.w */
2088 /* Fetch rd and ea. */
2089 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2095 case O (O_SUB, SL): /* sub.l */
2096 /* Fetch rd and ea. */
2097 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2103 case O (O_NEG, SB): /* neg.b */
2105 if (fetch2 (sd, &code->src, &ea))
2112 case O (O_NEG, SW): /* neg.w */
2114 if (fetch2 (sd, &code->src, &ea))
2121 case O (O_NEG, SL): /* neg.l */
2123 if (fetch2 (sd, &code->src, &ea))
2130 case O (O_ADD, SB): /* add.b */
2131 if (fetch2 (sd, &code->dst, &rd))
2133 if (fetch (sd, &code->src, &ea))
2138 case O (O_ADD, SW): /* add.w */
2139 if (fetch2 (sd, &code->dst, &rd))
2141 if (fetch (sd, &code->src, &ea))
2146 case O (O_ADD, SL): /* add.l */
2147 if (fetch2 (sd, &code->dst, &rd))
2149 if (fetch (sd, &code->src, &ea))
2154 case O (O_AND, SB): /* and.b */
2155 /* Fetch rd and ea. */
2156 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2161 case O (O_AND, SW): /* and.w */
2162 /* Fetch rd and ea. */
2163 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2168 case O (O_AND, SL): /* and.l */
2169 /* Fetch rd and ea. */
2170 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2175 case O (O_OR, SB): /* or.b */
2176 /* Fetch rd and ea. */
2177 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2182 case O (O_OR, SW): /* or.w */
2183 /* Fetch rd and ea. */
2184 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2189 case O (O_OR, SL): /* or.l */
2190 /* Fetch rd and ea. */
2191 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2196 case O (O_XOR, SB): /* xor.b */
2197 /* Fetch rd and ea. */
2198 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2203 case O (O_XOR, SW): /* xor.w */
2204 /* Fetch rd and ea. */
2205 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2210 case O (O_XOR, SL): /* xor.l */
2211 /* Fetch rd and ea. */
2212 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2218 if (fetch (sd, &code->src, &res))
2220 if (store (sd, &code->dst, res))
2222 goto just_flags_log8;
2224 if (fetch (sd, &code->src, &res))
2226 if (store (sd, &code->dst, res))
2228 goto just_flags_log16;
2230 if (fetch (sd, &code->src, &res))
2232 if (store (sd, &code->dst, res))
2234 goto just_flags_log32;
2236 case O (O_MOVMD, SB): /* movmd.b */
2243 rd = GET_MEMORY_B (GET_L_REG (5));
2244 SET_MEMORY_B (GET_L_REG (6), rd);
2245 SET_L_REG (5, GET_L_REG (5) + 1);
2246 SET_L_REG (6, GET_L_REG (6) + 1);
2251 case O (O_MOVMD, SW): /* movmd.w */
2258 rd = GET_MEMORY_W (GET_L_REG (5));
2259 SET_MEMORY_W (GET_L_REG (6), rd);
2260 SET_L_REG (5, GET_L_REG (5) + 2);
2261 SET_L_REG (6, GET_L_REG (6) + 2);
2266 case O (O_MOVMD, SL): /* movmd.l */
2273 rd = GET_MEMORY_L (GET_L_REG (5));
2274 SET_MEMORY_L (GET_L_REG (6), rd);
2275 SET_L_REG (5, GET_L_REG (5) + 4);
2276 SET_L_REG (6, GET_L_REG (6) + 4);
2281 case O (O_MOVSD, SB): /* movsd.b */
2282 /* This instruction implements strncpy, with a conditional branch.
2283 r4 contains n, r5 contains src, and r6 contains dst.
2284 The 16-bit displacement operand is added to the pc
2285 if and only if the end of string is reached before
2286 n bytes are transferred. */
2288 ea = GET_L_REG (4) & 0xffff;
2294 rd = GET_MEMORY_B (GET_L_REG (5));
2295 SET_MEMORY_B (GET_L_REG (6), rd);
2296 SET_L_REG (5, GET_L_REG (5) + 1);
2297 SET_L_REG (6, GET_L_REG (6) + 1);
2304 case O (O_EEPMOV, SB): /* eepmov.b */
2305 case O (O_EEPMOV, SW): /* eepmov.w */
2306 if (h8300hmode || h8300smode)
2308 register unsigned char *_src, *_dst;
2309 unsigned int count = ((code->opcode == O (O_EEPMOV, SW))
2310 ? h8_get_reg (sd, R4_REGNUM) & 0xffff
2311 : h8_get_reg (sd, R4_REGNUM) & 0xff);
2313 _src = (h8_get_reg (sd, R5_REGNUM) < memory_size
2314 ? h8_get_memory_buf (sd) + h8_get_reg (sd, R5_REGNUM)
2315 : h8_get_eightbit_buf (sd) +
2316 (h8_get_reg (sd, R5_REGNUM) & 0xff));
2317 if ((_src + count) >= (h8_get_memory_buf (sd) + memory_size))
2319 if ((_src + count) >= (h8_get_eightbit_buf (sd) + 0x100))
2322 _dst = (h8_get_reg (sd, R6_REGNUM) < memory_size
2323 ? h8_get_memory_buf (sd) + h8_get_reg (sd, R6_REGNUM)
2324 : h8_get_eightbit_buf (sd) +
2325 (h8_get_reg (sd, R6_REGNUM) & 0xff));
2327 if ((_dst + count) >= (h8_get_memory_buf (sd) + memory_size))
2329 if ((_dst + count) >= (h8_get_eightbit_buf (sd) + 0x100))
2332 memcpy (_dst, _src, count);
2334 h8_set_reg (sd, R5_REGNUM, h8_get_reg (sd, R5_REGNUM) + count);
2335 h8_set_reg (sd, R6_REGNUM, h8_get_reg (sd, R6_REGNUM) + count);
2336 h8_set_reg (sd, R4_REGNUM, h8_get_reg (sd, R4_REGNUM) &
2337 ((code->opcode == O (O_EEPMOV, SW))
2338 ? (~0xffff) : (~0xff)));
2339 cycles += 2 * count;
2344 case O (O_ADDS, SL): /* adds (.l) */
2346 * This insn only uses register operands, but still
2347 * it would be cleaner to use fetch and store... */
2348 SET_L_REG (code->dst.reg,
2349 GET_L_REG (code->dst.reg)
2350 + code->src.literal);
2354 case O (O_SUBS, SL): /* subs (.l) */
2356 * This insn only uses register operands, but still
2357 * it would be cleaner to use fetch and store... */
2358 SET_L_REG (code->dst.reg,
2359 GET_L_REG (code->dst.reg)
2360 - code->src.literal);
2363 case O (O_CMP, SB): /* cmp.b */
2364 if (fetch (sd, &code->dst, &rd))
2366 if (fetch (sd, &code->src, &ea))
2370 goto just_flags_alu8;
2372 case O (O_CMP, SW): /* cmp.w */
2373 if (fetch (sd, &code->dst, &rd))
2375 if (fetch (sd, &code->src, &ea))
2379 goto just_flags_alu16;
2381 case O (O_CMP, SL): /* cmp.l */
2382 if (fetch (sd, &code->dst, &rd))
2384 if (fetch (sd, &code->src, &ea))
2388 goto just_flags_alu32;
2390 case O (O_DEC, SB): /* dec.b */
2392 * This insn only uses register operands, but still
2393 * it would be cleaner to use fetch and store... */
2394 rd = GET_B_REG (code->src.reg);
2397 SET_B_REG (code->src.reg, res);
2398 goto just_flags_inc8;
2400 case O (O_DEC, SW): /* dec.w */
2402 * This insn only uses register operands, but still
2403 * it would be cleaner to use fetch and store... */
2404 rd = GET_W_REG (code->dst.reg);
2405 ea = -code->src.literal;
2407 SET_W_REG (code->dst.reg, res);
2408 goto just_flags_inc16;
2410 case O (O_DEC, SL): /* dec.l */
2412 * This insn only uses register operands, but still
2413 * it would be cleaner to use fetch and store... */
2414 rd = GET_L_REG (code->dst.reg);
2415 ea = -code->src.literal;
2417 SET_L_REG (code->dst.reg, res);
2418 goto just_flags_inc32;
2420 case O (O_INC, SB): /* inc.b */
2422 * This insn only uses register operands, but still
2423 * it would be cleaner to use fetch and store... */
2424 rd = GET_B_REG (code->src.reg);
2427 SET_B_REG (code->src.reg, res);
2428 goto just_flags_inc8;
2430 case O (O_INC, SW): /* inc.w */
2432 * This insn only uses register operands, but still
2433 * it would be cleaner to use fetch and store... */
2434 rd = GET_W_REG (code->dst.reg);
2435 ea = code->src.literal;
2437 SET_W_REG (code->dst.reg, res);
2438 goto just_flags_inc16;
2440 case O (O_INC, SL): /* inc.l */
2442 * This insn only uses register operands, but still
2443 * it would be cleaner to use fetch and store... */
2444 rd = GET_L_REG (code->dst.reg);
2445 ea = code->src.literal;
2447 SET_L_REG (code->dst.reg, res);
2448 goto just_flags_inc32;
2450 case O (O_LDC, SB): /* ldc.b */
2451 if (fetch (sd, &code->src, &res))
2455 case O (O_LDC, SW): /* ldc.w */
2456 if (fetch (sd, &code->src, &res))
2459 /* Word operand, value from MSB, must be shifted. */
2463 case O (O_LDC, SL): /* ldc.l */
2464 if (fetch (sd, &code->src, &res))
2466 switch (code->dst.type) {
2467 case X (OP_SBR, SL):
2468 h8_set_sbr (sd, res);
2470 case X (OP_VBR, SL):
2471 h8_set_vbr (sd, res);
2478 case O (O_STC, SW): /* stc.w */
2479 case O (O_STC, SB): /* stc.b */
2480 if (code->src.type == X (OP_CCR, SB))
2483 res = h8_get_ccr (sd);
2485 else if (code->src.type == X (OP_EXR, SB) && h8300smode)
2488 h8_set_exr (sd, (trace << 7) | intMask);
2489 res = h8_get_exr (sd);
2494 /* Word operand, value to MSB, must be shifted. */
2495 if (code->opcode == X (O_STC, SW))
2497 if (store (sd, &code->dst, res))
2500 case O (O_STC, SL): /* stc.l */
2501 switch (code->src.type) {
2502 case X (OP_SBR, SL):
2503 res = h8_get_sbr (sd);
2505 case X (OP_VBR, SL):
2506 res = h8_get_vbr (sd);
2511 if (store (sd, &code->dst, res))
2515 case O (O_ANDC, SB): /* andc.b */
2516 if (code->dst.type == X (OP_CCR, SB))
2519 rd = h8_get_ccr (sd);
2521 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2524 h8_set_exr (sd, (trace << 7) | intMask);
2525 rd = h8_get_exr (sd);
2529 ea = code->src.literal;
2533 case O (O_ORC, SB): /* orc.b */
2534 if (code->dst.type == X (OP_CCR, SB))
2537 rd = h8_get_ccr (sd);
2539 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2542 h8_set_exr (sd, (trace << 7) | intMask);
2543 rd = h8_get_exr (sd);
2547 ea = code->src.literal;
2551 case O (O_XORC, SB): /* xorc.b */
2552 if (code->dst.type == X (OP_CCR, SB))
2555 rd = h8_get_ccr (sd);
2557 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2560 h8_set_exr (sd, (trace << 7) | intMask);
2561 rd = h8_get_exr (sd);
2565 ea = code->src.literal;
2569 case O (O_BRAS, SB): /* bra/s */
2570 /* This is basically an ordinary branch, with a delay slot. */
2571 if (fetch (sd, &code->src, &res))
2579 /* Execution continues at next instruction, but
2580 delayed_branch is set up for next cycle. */
2581 h8_set_delayed_branch (sd, code->next_pc + res);
2585 case O (O_BRAB, SB): /* bra rd.b */
2586 case O (O_BRAW, SW): /* bra rd.w */
2587 case O (O_BRAL, SL): /* bra erd.l */
2588 if (fetch (sd, &code->src, &rd))
2590 switch (OP_SIZE (code->opcode)) {
2591 case SB: rd &= 0xff; break;
2592 case SW: rd &= 0xffff; break;
2593 case SL: rd &= 0xffffffff; break;
2595 pc = code->next_pc + rd;
2598 case O (O_BRABC, SB): /* bra/bc, branch if bit clear */
2599 case O (O_BRABS, SB): /* bra/bs, branch if bit set */
2600 case O (O_BSRBC, SB): /* bsr/bc, call if bit clear */
2601 case O (O_BSRBS, SB): /* bsr/bs, call if bit set */
2602 if (fetch (sd, &code->dst, &rd) ||
2603 fetch (sd, &code->src, &bit))
2606 if (code->opcode == O (O_BRABC, SB) || /* branch if clear */
2607 code->opcode == O (O_BSRBC, SB)) /* call if clear */
2609 if ((rd & (1 << bit))) /* no branch */
2612 else /* branch/call if set */
2614 if (!(rd & (1 << bit))) /* no branch */
2618 if (fetch (sd, &code->op3, &res)) /* branch */
2620 pc = code->next_pc + res;
2622 if (code->opcode == O (O_BRABC, SB) ||
2623 code->opcode == O (O_BRABS, SB)) /* branch */
2631 case O (O_BRA, SB): /* bra, branch always */
2636 case O (O_BRN, SB): /* brn, ;-/ branch never? */
2641 case O (O_BHI, SB): /* bhi */
2647 case O (O_BLS, SB): /* bls */
2652 case O (O_BCS, SB): /* bcs, branch if carry set */
2657 case O (O_BCC, SB): /* bcc, branch if carry clear */
2662 case O (O_BEQ, SB): /* beq, branch if zero set */
2666 case O (O_BGT, SB): /* bgt */
2667 if (((Z || (N ^ V)) == 0))
2671 case O (O_BLE, SB): /* ble */
2672 if (((Z || (N ^ V)) == 1))
2676 case O (O_BGE, SB): /* bge */
2680 case O (O_BLT, SB): /* blt */
2684 case O (O_BMI, SB): /* bmi */
2688 case O (O_BNE, SB): /* bne, branch if zero clear */
2693 case O (O_BPL, SB): /* bpl */
2697 case O (O_BVC, SB): /* bvc */
2701 case O (O_BVS, SB): /* bvs */
2706 /* Trap for Command Line setup. */
2707 case O (O_SYS_CMDLINE, SB):
2709 int i = 0; /* Loop counter. */
2710 int j = 0; /* Loop counter. */
2711 int ind_arg_len = 0; /* Length of each argument. */
2712 int no_of_args = 0; /* The no. or cmdline args. */
2713 int current_location = 0; /* Location of string. */
2714 int old_sp = 0; /* The Initial Stack Pointer. */
2715 int no_of_slots = 0; /* No. of slots required on the stack
2716 for storing cmdline args. */
2717 int sp_move = 0; /* No. of locations by which the stack needs
2719 int new_sp = 0; /* The final stack pointer location passed
2721 int *argv_ptrs; /* Pointers of argv strings to be stored. */
2722 int argv_ptrs_location = 0; /* Location of pointers to cmdline
2723 args on the stack. */
2724 int char_ptr_size = 0; /* Size of a character pointer on
2726 int addr_cmdline = 0; /* Memory location where cmdline has
2728 int size_cmdline = 0; /* Size of cmdline. */
2730 /* Set the address of 256 free locations where command line is
2732 addr_cmdline = cmdline_location();
2733 h8_set_reg (sd, 0, addr_cmdline);
2735 /* Counting the no. of commandline arguments. */
2736 for (i = 0; h8_get_cmdline_arg (sd, i) != NULL; i++)
2739 /* No. of arguments in the command line. */
2742 /* Current location is just a temporary variable,which we are
2743 setting to the point to the start of our commandline string. */
2744 current_location = addr_cmdline;
2746 /* Allocating space for storing pointers of the command line
2748 argv_ptrs = (int *) malloc (sizeof (int) * no_of_args);
2750 /* Setting char_ptr_size to the sizeof (char *) on the different
2752 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
2761 for (i = 0; i < no_of_args; i++)
2765 /* The size of the commandline argument. */
2766 ind_arg_len = strlen (h8_get_cmdline_arg (sd, i)) + 1;
2768 /* The total size of the command line string. */
2769 size_cmdline += ind_arg_len;
2771 /* As we have only 256 bytes, we need to provide a graceful
2772 exit. Anyways, a program using command line arguments
2773 where we cannot store all the command line arguments
2774 given may behave unpredictably. */
2775 if (size_cmdline >= 256)
2777 h8_set_reg (sd, 0, 0);
2782 /* current_location points to the memory where the next
2783 commandline argument is stored. */
2784 argv_ptrs[i] = current_location;
2785 for (j = 0; j < ind_arg_len; j++)
2787 SET_MEMORY_B ((current_location +
2788 (sizeof (char) * j)),
2789 *(h8_get_cmdline_arg (sd, i) +
2790 sizeof (char) * j));
2793 /* Setting current_location to the starting of next
2795 current_location += ind_arg_len;
2799 /* This is the original position of the stack pointer. */
2800 old_sp = h8_get_reg (sd, SP_REGNUM);
2802 /* We need space from the stack to store the pointers to argvs. */
2803 /* As we will infringe on the stack, we need to shift the stack
2804 pointer so that the data is not overwritten. We calculate how
2805 much space is required. */
2806 sp_move = (no_of_args) * (char_ptr_size);
2808 /* The final position of stack pointer, we have thus taken some
2809 space from the stack. */
2810 new_sp = old_sp - sp_move;
2812 /* Temporary variable holding value where the argv pointers need
2814 argv_ptrs_location = new_sp;
2816 /* The argv pointers are stored at sequential locations. As per
2818 for (i = 0; i < no_of_args; i++)
2820 /* Saving the argv pointer. */
2821 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
2823 SET_MEMORY_L (argv_ptrs_location, argv_ptrs[i]);
2827 SET_MEMORY_W (argv_ptrs_location, argv_ptrs[i]);
2830 /* The next location where the pointer to the next argv
2831 string has to be stored. */
2832 argv_ptrs_location += char_ptr_size;
2835 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2837 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
2839 SET_MEMORY_L (old_sp, 0x0);
2843 SET_MEMORY_W (old_sp, 0x0);
2846 /* Freeing allocated memory. */
2848 for (i = 0; i <= no_of_args; i++)
2850 free (h8_get_cmdline_arg (sd, i));
2852 free (h8_get_command_line (sd));
2854 /* The no. of argv arguments are returned in Reg 0. */
2855 h8_set_reg (sd, 0, no_of_args);
2856 /* The Pointer to argv in Register 1. */
2857 h8_set_reg (sd, 1, new_sp);
2858 /* Setting the stack pointer to the new value. */
2859 h8_set_reg (sd, SP_REGNUM, new_sp);
2863 /* System call processing starts. */
2864 case O (O_SYS_OPEN, SB):
2866 int len = 0; /* Length of filename. */
2867 char *filename; /* Filename would go here. */
2868 char temp_char; /* Temporary character */
2869 int mode = 0; /* Mode bits for the file. */
2870 int open_return; /* Return value of open, file descriptor. */
2871 int i; /* Loop counter */
2872 int filename_ptr; /* Pointer to filename in cpu memory. */
2874 /* Setting filename_ptr to first argument of open, */
2875 /* and trying to get mode. */
2876 if ((h8300sxmode || h8300hmode || h8300smode) && !h8300_normal_mode)
2878 filename_ptr = GET_L_REG (0);
2879 mode = GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM) + 4);
2883 filename_ptr = GET_W_REG (0);
2884 mode = GET_MEMORY_W (h8_get_reg (sd, SP_REGNUM) + 2);
2887 /* Trying to find the length of the filename. */
2888 temp_char = GET_MEMORY_B (h8_get_reg (sd, 0));
2891 while (temp_char != '\0')
2893 temp_char = GET_MEMORY_B (filename_ptr + len);
2897 /* Allocating space for the filename. */
2898 filename = (char *) malloc (sizeof (char) * len);
2900 /* String copying the filename from memory. */
2901 for (i = 0; i < len; i++)
2903 temp_char = GET_MEMORY_B (filename_ptr + i);
2904 filename[i] = temp_char;
2907 /* Callback to open and return the file descriptor. */
2908 open_return = sim_callback->open (sim_callback, filename, mode);
2910 /* Return value in register 0. */
2911 h8_set_reg (sd, 0, open_return);
2913 /* Freeing memory used for filename. */
2918 case O (O_SYS_READ, SB):
2920 char *char_ptr; /* Where characters read would be stored. */
2921 int fd; /* File descriptor */
2922 int buf_size; /* BUF_SIZE parameter in read. */
2923 int i = 0; /* Temporary Loop counter */
2924 int read_return = 0; /* Return value from callback to
2927 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2928 buf_size = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
2930 char_ptr = (char *) malloc (sizeof (char) * buf_size);
2932 /* Callback to read and return the no. of characters read. */
2934 sim_callback->read (sim_callback, fd, char_ptr, buf_size);
2936 /* The characters read are stored in cpu memory. */
2937 for (i = 0; i < buf_size; i++)
2939 SET_MEMORY_B ((h8_get_reg (sd, 1) + (sizeof (char) * i)),
2940 *(char_ptr + (sizeof (char) * i)));
2943 /* Return value in Register 0. */
2944 h8_set_reg (sd, 0, read_return);
2946 /* Freeing memory used as buffer. */
2951 case O (O_SYS_WRITE, SB):
2953 int fd; /* File descriptor */
2954 char temp_char; /* Temporary character */
2955 int len; /* Length of write, Parameter II to write. */
2956 int char_ptr; /* Character Pointer, Parameter I of write. */
2957 char *ptr; /* Where characters to be written are stored.
2959 int write_return; /* Return value from callback to write. */
2960 int i = 0; /* Loop counter */
2962 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2963 char_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
2964 len = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
2966 /* Allocating space for the characters to be written. */
2967 ptr = (char *) malloc (sizeof (char) * len);
2969 /* Fetching the characters from cpu memory. */
2970 for (i = 0; i < len; i++)
2972 temp_char = GET_MEMORY_B (char_ptr + i);
2976 /* Callback write and return the no. of characters written. */
2977 write_return = sim_callback->write (sim_callback, fd, ptr, len);
2979 /* Return value in Register 0. */
2980 h8_set_reg (sd, 0, write_return);
2982 /* Freeing memory used as buffer. */
2987 case O (O_SYS_LSEEK, SB):
2989 int fd; /* File descriptor */
2990 int offset; /* Offset */
2991 int origin; /* Origin */
2992 int lseek_return; /* Return value from callback to lseek. */
2994 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2995 offset = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
2996 origin = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
2998 /* Callback lseek and return offset. */
3000 sim_callback->lseek (sim_callback, fd, offset, origin);
3002 /* Return value in register 0. */
3003 h8_set_reg (sd, 0, lseek_return);
3007 case O (O_SYS_CLOSE, SB):
3009 int fd; /* File descriptor */
3010 int close_return; /* Return value from callback to close. */
3012 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
3014 /* Callback close and return. */
3015 close_return = sim_callback->close (sim_callback, fd);
3017 /* Return value in register 0. */
3018 h8_set_reg (sd, 0, close_return);
3022 case O (O_SYS_FSTAT, SB):
3024 int fd; /* File descriptor */
3025 struct stat stat_rec; /* Stat record */
3026 int fstat_return; /* Return value from callback to stat. */
3027 int stat_ptr; /* Pointer to stat record. */
3028 char *temp_stat_ptr; /* Temporary stat_rec pointer. */
3030 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
3032 /* Setting stat_ptr to second argument of stat. */
3033 stat_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
3035 /* Callback stat and return. */
3036 fstat_return = sim_callback->to_fstat (sim_callback, fd,
3039 /* Have stat_ptr point to starting of stat_rec. */
3040 temp_stat_ptr = (char *) (&stat_rec);
3042 /* Setting up the stat structure returned. */
3043 SET_MEMORY_W (stat_ptr, stat_rec.st_dev);
3045 SET_MEMORY_W (stat_ptr, stat_rec.st_ino);
3047 SET_MEMORY_L (stat_ptr, stat_rec.st_mode);
3049 SET_MEMORY_W (stat_ptr, stat_rec.st_nlink);
3051 SET_MEMORY_W (stat_ptr, stat_rec.st_uid);
3053 SET_MEMORY_W (stat_ptr, stat_rec.st_gid);
3055 SET_MEMORY_W (stat_ptr, stat_rec.st_rdev);
3057 SET_MEMORY_L (stat_ptr, stat_rec.st_size);
3059 SET_MEMORY_L (stat_ptr, stat_rec.st_atime);
3061 SET_MEMORY_L (stat_ptr, stat_rec.st_mtime);
3063 SET_MEMORY_L (stat_ptr, stat_rec.st_ctime);
3065 /* Return value in register 0. */
3066 h8_set_reg (sd, 0, fstat_return);
3070 case O (O_SYS_STAT, SB):
3072 int len = 0; /* Length of filename. */
3073 char *filename; /* Filename would go here. */
3074 char temp_char; /* Temporary character */
3075 int filename_ptr; /* Pointer to filename in cpu memory. */
3076 struct stat stat_rec; /* Stat record */
3077 int stat_return; /* Return value from callback to stat */
3078 int stat_ptr; /* Pointer to stat record. */
3079 char *temp_stat_ptr; /* Temporary stat_rec pointer. */
3080 int i = 0; /* Loop Counter */
3082 /* Setting filename_ptr to first argument of open. */
3083 filename_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
3085 /* Trying to find the length of the filename. */
3086 temp_char = GET_MEMORY_B (h8_get_reg (sd, 0));
3089 while (temp_char != '\0')
3091 temp_char = GET_MEMORY_B (filename_ptr + len);
3095 /* Allocating space for the filename. */
3096 filename = (char *) malloc (sizeof (char) * len);
3098 /* String copying the filename from memory. */
3099 for (i = 0; i < len; i++)
3101 temp_char = GET_MEMORY_B (filename_ptr + i);
3102 filename[i] = temp_char;
3105 /* Setting stat_ptr to second argument of stat. */
3106 /* stat_ptr = h8_get_reg (sd, 1); */
3107 stat_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
3109 /* Callback stat and return. */
3111 sim_callback->to_stat (sim_callback, filename, &stat_rec);
3113 /* Have stat_ptr point to starting of stat_rec. */
3114 temp_stat_ptr = (char *) (&stat_rec);
3116 /* Freeing memory used for filename. */
3119 /* Setting up the stat structure returned. */
3120 SET_MEMORY_W (stat_ptr, stat_rec.st_dev);
3122 SET_MEMORY_W (stat_ptr, stat_rec.st_ino);
3124 SET_MEMORY_L (stat_ptr, stat_rec.st_mode);
3126 SET_MEMORY_W (stat_ptr, stat_rec.st_nlink);
3128 SET_MEMORY_W (stat_ptr, stat_rec.st_uid);
3130 SET_MEMORY_W (stat_ptr, stat_rec.st_gid);
3132 SET_MEMORY_W (stat_ptr, stat_rec.st_rdev);
3134 SET_MEMORY_L (stat_ptr, stat_rec.st_size);
3136 SET_MEMORY_L (stat_ptr, stat_rec.st_atime);
3138 SET_MEMORY_L (stat_ptr, stat_rec.st_mtime);
3140 SET_MEMORY_L (stat_ptr, stat_rec.st_ctime);
3142 /* Return value in register 0. */
3143 h8_set_reg (sd, 0, stat_return);
3146 /* End of system call processing. */
3148 case O (O_NOT, SB): /* not.b */
3149 if (fetch2 (sd, &code->src, &rd))
3155 case O (O_NOT, SW): /* not.w */
3156 if (fetch2 (sd, &code->src, &rd))
3162 case O (O_NOT, SL): /* not.l */
3163 if (fetch2 (sd, &code->src, &rd))
3169 case O (O_SHLL, SB): /* shll.b */
3170 case O (O_SHLR, SB): /* shlr.b */
3171 if (fetch2 (sd, &code->dst, &rd))
3174 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3175 ea = 1; /* unary op */
3176 else /* binary op */
3177 fetch (sd, &code->src, &ea);
3179 if (code->opcode == O (O_SHLL, SB))
3182 c = rd & (0x80 >> (ea - 1));
3188 c = rd & (1 << (ea - 1));
3189 rd = (unsigned char) rd >> ea;
3193 case O (O_SHLL, SW): /* shll.w */
3194 case O (O_SHLR, SW): /* shlr.w */
3195 if (fetch2 (sd, &code->dst, &rd))
3198 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3199 ea = 1; /* unary op */
3201 fetch (sd, &code->src, &ea);
3203 if (code->opcode == O (O_SHLL, SW))
3206 c = rd & (0x8000 >> (ea - 1));
3212 c = rd & (1 << (ea - 1));
3213 rd = (unsigned short) rd >> ea;
3217 case O (O_SHLL, SL): /* shll.l */
3218 case O (O_SHLR, SL): /* shlr.l */
3219 if (fetch2 (sd, &code->dst, &rd))
3222 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3223 ea = 1; /* unary op */
3225 fetch (sd, &code->src, &ea);
3227 if (code->opcode == O (O_SHLL, SL))
3230 c = rd & (0x80000000 >> (ea - 1));
3236 c = rd & (1 << (ea - 1));
3237 rd = (unsigned int) rd >> ea;
3241 case O (O_SHAL, SB):
3242 case O (O_SHAR, SB):
3243 if (fetch2 (sd, &code->dst, &rd))
3246 if (code->src.type == X (OP_IMM, SB))
3247 fetch (sd, &code->src, &ea);
3251 if (code->opcode == O (O_SHAL, SB))
3253 c = rd & (0x80 >> (ea - 1));
3254 res = rd >> (7 - ea);
3255 v = ((res & 1) && !(res & 2))
3256 || (!(res & 1) && (res & 2));
3261 c = rd & (1 << (ea - 1));
3263 rd = ((signed char) rd) >> ea;
3267 case O (O_SHAL, SW):
3268 case O (O_SHAR, SW):
3269 if (fetch2 (sd, &code->dst, &rd))
3272 if (code->src.type == X (OP_IMM, SW))
3273 fetch (sd, &code->src, &ea);
3277 if (code->opcode == O (O_SHAL, SW))
3279 c = rd & (0x8000 >> (ea - 1));
3280 res = rd >> (15 - ea);
3281 v = ((res & 1) && !(res & 2))
3282 || (!(res & 1) && (res & 2));
3287 c = rd & (1 << (ea - 1));
3289 rd = ((signed short) rd) >> ea;
3293 case O (O_SHAL, SL):
3294 case O (O_SHAR, SL):
3295 if (fetch2 (sd, &code->dst, &rd))
3298 if (code->src.type == X (OP_IMM, SL))
3299 fetch (sd, &code->src, &ea);
3303 if (code->opcode == O (O_SHAL, SL))
3305 c = rd & (0x80000000 >> (ea - 1));
3306 res = rd >> (31 - ea);
3307 v = ((res & 1) && !(res & 2))
3308 || (!(res & 1) && (res & 2));
3313 c = rd & (1 << (ea - 1));
3315 rd = ((signed int) rd) >> ea;
3319 case O (O_ROTL, SB):
3320 case O (O_ROTR, SB):
3321 if (fetch2 (sd, &code->dst, &rd))
3324 if (code->src.type == X (OP_IMM, SB))
3325 fetch (sd, &code->src, &ea);
3330 if (code->opcode == O (O_ROTL, SB))
3340 rd = ((unsigned char) rd) >> 1;
3348 case O (O_ROTL, SW):
3349 case O (O_ROTR, SW):
3350 if (fetch2 (sd, &code->dst, &rd))
3353 if (code->src.type == X (OP_IMM, SW))
3354 fetch (sd, &code->src, &ea);
3359 if (code->opcode == O (O_ROTL, SW))
3369 rd = ((unsigned short) rd) >> 1;
3377 case O (O_ROTL, SL):
3378 case O (O_ROTR, SL):
3379 if (fetch2 (sd, &code->dst, &rd))
3382 if (code->src.type == X (OP_IMM, SL))
3383 fetch (sd, &code->src, &ea);
3388 if (code->opcode == O (O_ROTL, SL))
3390 c = rd & 0x80000000;
3398 rd = ((unsigned int) rd) >> 1;
3406 case O (O_ROTXL, SB):
3407 case O (O_ROTXR, SB):
3408 if (fetch2 (sd, &code->dst, &rd))
3411 if (code->src.type == X (OP_IMM, SB))
3412 fetch (sd, &code->src, &ea);
3417 if (code->opcode == O (O_ROTXL, SB))
3428 rd = ((unsigned char) rd) >> 1;
3437 case O (O_ROTXL, SW):
3438 case O (O_ROTXR, SW):
3439 if (fetch2 (sd, &code->dst, &rd))
3442 if (code->src.type == X (OP_IMM, SW))
3443 fetch (sd, &code->src, &ea);
3448 if (code->opcode == O (O_ROTXL, SW))
3459 rd = ((unsigned short) rd) >> 1;
3468 case O (O_ROTXL, SL):
3469 case O (O_ROTXR, SL):
3470 if (fetch2 (sd, &code->dst, &rd))
3473 if (code->src.type == X (OP_IMM, SL))
3474 fetch (sd, &code->src, &ea);
3479 if (code->opcode == O (O_ROTXL, SL))
3481 res = rd & 0x80000000;
3490 rd = ((unsigned int) rd) >> 1;
3501 case O (O_JMP, SB): /* jmp */
3503 fetch (sd, &code->src, &pc);
3508 case O (O_JSR, SB): /* jsr, jump to subroutine */
3510 if (fetch (sd, &code->src, &pc))
3513 tmp = h8_get_reg (sd, SP_REGNUM);
3515 if (h8300hmode && !h8300_normal_mode)
3518 SET_MEMORY_L (tmp, code->next_pc);
3523 SET_MEMORY_W (tmp, code->next_pc);
3525 h8_set_reg (sd, SP_REGNUM, tmp);
3531 case O (O_BSR, SB): /* bsr, branch to subroutine */
3532 if (fetch (sd, &code->src, &res))
3534 pc = code->next_pc + res;
3537 case O (O_RTE, SN): /* rte, return from exception */
3539 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3540 tmp = h8_get_reg (sd, SP_REGNUM);
3542 if (h8300smode) /* pop exr */
3544 h8_set_exr (sd, GET_MEMORY_L (tmp));
3547 if (h8300hmode && !h8300_normal_mode)
3549 h8_set_ccr (sd, GET_MEMORY_L (tmp));
3551 pc = GET_MEMORY_L (tmp);
3556 h8_set_ccr (sd, GET_MEMORY_W (tmp));
3558 pc = GET_MEMORY_W (tmp);
3563 h8_set_reg (sd, SP_REGNUM, tmp);
3566 case O (O_RTS, SN): /* rts, return from subroutine */
3568 tmp = h8_get_reg (sd, SP_REGNUM);
3570 if (h8300hmode && !h8300_normal_mode)
3572 pc = GET_MEMORY_L (tmp);
3577 pc = GET_MEMORY_W (tmp);
3581 h8_set_reg (sd, SP_REGNUM, tmp);
3584 case O (O_ILL, SB): /* illegal */
3585 sim_engine_set_run_state (sd, sim_stopped, SIGILL);
3588 case O (O_SLEEP, SN): /* sleep */
3589 /* Check for magic numbers in r1 and r2. */
3590 if ((h8_get_reg (sd, R1_REGNUM) & 0xffff) == LIBC_EXIT_MAGIC1 &&
3591 (h8_get_reg (sd, R2_REGNUM) & 0xffff) == LIBC_EXIT_MAGIC2 &&
3592 SIM_WIFEXITED (h8_get_reg (sd, 0)))
3594 /* This trap comes from _exit, not from gdb. */
3595 sim_engine_set_run_state (sd, sim_exited,
3596 SIM_WEXITSTATUS (h8_get_reg (sd, 0)));
3599 /* Unfortunately this won't really work, because
3600 when we take a breakpoint trap, R0 has a "random",
3601 user-defined value. Don't see any immediate solution. */
3602 else if (SIM_WIFSTOPPED (h8_get_reg (sd, 0)))
3604 /* Pass the stop signal up to gdb. */
3605 sim_engine_set_run_state (sd, sim_stopped,
3606 SIM_WSTOPSIG (h8_get_reg (sd, 0)));
3611 /* Treat it as a sigtrap. */
3612 sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
3616 case O (O_TRAPA, SB): /* trapa */
3617 if (fetch (sd, &code->src, &res))
3618 goto end; /* res is vector number. */
3620 tmp = h8_get_reg (sd, SP_REGNUM);
3621 if(h8300_normal_mode)
3624 SET_MEMORY_W (tmp, code->next_pc);
3626 SET_MEMORY_W (tmp, h8_get_ccr (sd));
3631 SET_MEMORY_L (tmp, code->next_pc);
3633 SET_MEMORY_L (tmp, h8_get_ccr (sd));
3641 SET_MEMORY_L (tmp, h8_get_exr (sd));
3644 h8_set_reg (sd, SP_REGNUM, tmp);
3646 if(h8300_normal_mode)
3647 pc = GET_MEMORY_L (0x10 + res * 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3649 pc = GET_MEMORY_L (0x20 + res * 4);
3653 sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
3656 case O (O_BSETEQ, SB):
3661 case O (O_BSETNE, SB):
3666 case O (O_BCLREQ, SB):
3671 case O (O_BCLRNE, SB):
3676 OBITOP (O_BNOT, 1, 1, ea ^= m); /* bnot */
3677 OBITOP (O_BTST, 1, 0, nz = ea & m); /* btst */
3679 OBITOP (O_BSET, 1, 1, ea |= m); /* bset */
3681 OBITOP (O_BCLR, 1, 1, ea &= ~m); /* bclr */
3682 OBITOP (O_BLD, 1, 0, c = ea & m); /* bld */
3683 OBITOP (O_BILD, 1, 0, c = !(ea & m)); /* bild */
3684 OBITOP (O_BST, 1, 1, ea &= ~m;
3685 if (C) ea |= m); /* bst */
3686 OBITOP (O_BIST, 1, 1, ea &= ~m;
3687 if (!C) ea |= m); /* bist */
3688 OBITOP (O_BSTZ, 1, 1, ea &= ~m;
3689 if (Z) ea |= m); /* bstz */
3690 OBITOP (O_BISTZ, 1, 1, ea &= ~m;
3691 if (!Z) ea |= m); /* bistz */
3692 OBITOP (O_BAND, 1, 0, c = (ea & m) && C); /* band */
3693 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); /* biand */
3694 OBITOP (O_BOR, 1, 0, c = (ea & m) || C); /* bor */
3695 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); /* bior */
3696 OBITOP (O_BXOR, 1, 0, c = ((ea & m) != 0)!= C); /* bxor */
3697 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); /* bixor */
3699 case O (O_BFLD, SB): /* bfld */
3702 if (fetch (sd, &code->src, &bit))
3707 if (fetch (sd, &code->dst, &ea))
3717 if (store (sd, &code->op3, ea))
3722 case O(O_BFST, SB): /* bfst */
3723 /* bitfield store */
3724 /* NOTE: the imm8 value is in dst, and the ea value
3725 (which is actually the destination) is in op3.
3726 It has to be that way, to avoid breaking the assembler. */
3728 if (fetch (sd, &code->dst, &bit)) /* imm8 */
3730 if (bit == 0) /* noop -- nothing to do. */
3733 if (fetch (sd, &code->src, &rd)) /* reg8 src */
3736 if (fetch2 (sd, &code->op3, &ea)) /* ea dst */
3739 /* Left-shift the register data into position. */
3740 for (tmp = bit; !(tmp & 1); tmp >>= 1)
3743 /* Combine it with the neighboring bits. */
3744 ea = (ea & ~bit) | (rd & bit);
3747 if (store2 (sd, &code->op3, ea))
3751 case O (O_CLRMAC, SN): /* clrmac */
3752 h8_set_mach (sd, 0);
3753 h8_set_macl (sd, 0);
3754 h8_set_macZ (sd, 1);
3755 h8_set_macV (sd, 0);
3756 h8_set_macN (sd, 0);
3759 case O (O_STMAC, SL): /* stmac, 260 */
3760 switch (code->src.type) {
3761 case X (OP_MACH, SL):
3762 res = h8_get_mach (sd);
3763 if (res & 0x200) /* sign extend */
3766 case X (OP_MACL, SL):
3767 res = h8_get_macl (sd);
3769 default: goto illegal;
3771 nz = !h8_get_macZ (sd);
3772 n = h8_get_macN (sd);
3773 v = h8_get_macV (sd);
3775 if (store (sd, &code->dst, res))
3780 case O (O_LDMAC, SL): /* ldmac, 179 */
3781 if (fetch (sd, &code->src, &rd))
3784 switch (code->dst.type) {
3785 case X (OP_MACH, SL):
3786 rd &= 0x3ff; /* Truncate to 10 bits */
3787 h8_set_mach (sd, rd);
3789 case X (OP_MACL, SL):
3790 h8_set_macl (sd, rd);
3792 default: goto illegal;
3794 h8_set_macV (sd, 0);
3798 if (fetch (sd, &code->src, &rd) ||
3799 fetch (sd, &code->dst, &res))
3802 /* Ye gods, this is non-portable!
3803 However, the existing mul/div code is similar. */
3804 res = SEXTSHORT (res) * SEXTSHORT (rd);
3806 if (h8_get_macS (sd)) /* Saturating mode */
3808 long long mac = h8_get_macl (sd);
3810 if (mac & 0x80000000) /* sign extend */
3811 mac |= 0xffffffff00000000LL;
3814 if (mac > 0x7fffffff || mac < 0xffffffff80000000LL)
3815 h8_set_macV (sd, 1);
3816 h8_set_macZ (sd, (mac == 0));
3817 h8_set_macN (sd, (mac < 0));
3818 h8_set_macl (sd, (int) mac);
3820 else /* "Less Saturating" mode */
3822 long long mac = h8_get_mach (sd);
3824 mac += h8_get_macl (sd);
3826 if (mac & 0x20000000000LL) /* sign extend */
3827 mac |= 0xfffffc0000000000LL;
3830 if (mac > 0x1ffffffffffLL ||
3831 mac < (long long) 0xfffffe0000000000LL)
3832 h8_set_macV (sd, 1);
3833 h8_set_macZ (sd, (mac == 0));
3834 h8_set_macN (sd, (mac < 0));
3835 h8_set_macl (sd, (int) mac);
3837 h8_set_mach (sd, (int) (mac & 0x3ff));
3841 case O (O_MULS, SW): /* muls.w */
3842 if (fetch (sd, &code->src, &ea) ||
3843 fetch (sd, &code->dst, &rd))
3846 ea = SEXTSHORT (ea);
3847 res = SEXTSHORT (ea * SEXTSHORT (rd));
3851 if (store (sd, &code->dst, res))
3856 case O (O_MULS, SL): /* muls.l */
3857 if (fetch (sd, &code->src, &ea) ||
3858 fetch (sd, &code->dst, &rd))
3863 n = res & 0x80000000;
3864 nz = res & 0xffffffff;
3865 if (store (sd, &code->dst, res))
3869 case O (O_MULSU, SL): /* muls/u.l */
3870 if (fetch (sd, &code->src, &ea) ||
3871 fetch (sd, &code->dst, &rd))
3874 /* Compute upper 32 bits of the 64-bit result. */
3875 res = (((long long) ea) * ((long long) rd)) >> 32;
3877 n = res & 0x80000000;
3878 nz = res & 0xffffffff;
3879 if (store (sd, &code->dst, res))
3883 case O (O_MULU, SW): /* mulu.w */
3884 if (fetch (sd, &code->src, &ea) ||
3885 fetch (sd, &code->dst, &rd))
3888 res = UEXTSHORT ((UEXTSHORT (ea) * UEXTSHORT (rd)));
3890 /* Don't set Z or N. */
3891 if (store (sd, &code->dst, res))
3896 case O (O_MULU, SL): /* mulu.l */
3897 if (fetch (sd, &code->src, &ea) ||
3898 fetch (sd, &code->dst, &rd))
3903 /* Don't set Z or N. */
3904 if (store (sd, &code->dst, res))
3909 case O (O_MULUU, SL): /* mulu/u.l */
3910 if (fetch (sd, &code->src, &ea) ||
3911 fetch (sd, &code->dst, &rd))
3914 /* Compute upper 32 bits of the 64-bit result. */
3915 res = (((unsigned long long) (unsigned) ea) *
3916 ((unsigned long long) (unsigned) rd)) >> 32;
3918 /* Don't set Z or N. */
3919 if (store (sd, &code->dst, res))
3924 case O (O_MULXS, SB): /* mulxs.b */
3925 if (fetch (sd, &code->src, &ea) ||
3926 fetch (sd, &code->dst, &rd))
3930 res = ea * SEXTCHAR (rd);
3934 if (store (sd, &code->dst, res))
3939 case O (O_MULXS, SW): /* mulxs.w */
3940 if (fetch (sd, &code->src, &ea) ||
3941 fetch (sd, &code->dst, &rd))
3944 ea = SEXTSHORT (ea);
3945 res = ea * SEXTSHORT (rd & 0xffff);
3947 n = res & 0x80000000;
3948 nz = res & 0xffffffff;
3949 if (store (sd, &code->dst, res))
3954 case O (O_MULXU, SB): /* mulxu.b */
3955 if (fetch (sd, &code->src, &ea) ||
3956 fetch (sd, &code->dst, &rd))
3959 res = UEXTCHAR (ea) * UEXTCHAR (rd);
3961 if (store (sd, &code->dst, res))
3966 case O (O_MULXU, SW): /* mulxu.w */
3967 if (fetch (sd, &code->src, &ea) ||
3968 fetch (sd, &code->dst, &rd))
3971 res = UEXTSHORT (ea) * UEXTSHORT (rd);
3973 if (store (sd, &code->dst, res))
3978 case O (O_TAS, SB): /* tas (test and set) */
3979 if (!h8300sxmode) /* h8sx can use any register. */
3980 switch (code->src.reg)
3991 if (fetch (sd, &code->src, &res))
3993 if (store (sd, &code->src, res | 0x80))
3996 goto just_flags_log8;
3998 case O (O_DIVU, SW): /* divu.w */
3999 if (fetch (sd, &code->src, &ea) ||
4000 fetch (sd, &code->dst, &rd))
4006 res = (unsigned) (UEXTSHORT (rd) / UEXTSHORT (ea));
4010 if (store (sd, &code->dst, res))
4014 case O (O_DIVU, SL): /* divu.l */
4015 if (fetch (sd, &code->src, &ea) ||
4016 fetch (sd, &code->dst, &rd))
4019 n = ea & 0x80000000;
4020 nz = ea & 0xffffffff;
4022 res = (unsigned) rd / ea;
4026 if (store (sd, &code->dst, res))
4030 case O (O_DIVS, SW): /* divs.w */
4031 if (fetch (sd, &code->src, &ea) ||
4032 fetch (sd, &code->dst, &rd))
4037 res = SEXTSHORT (rd) / SEXTSHORT (ea);
4047 if (store (sd, &code->dst, res))
4051 case O (O_DIVS, SL): /* divs.l */
4052 if (fetch (sd, &code->src, &ea) ||
4053 fetch (sd, &code->dst, &rd))
4067 n = res & 0x80000000;
4068 if (store (sd, &code->dst, res))
4072 case O (O_DIVXU, SB): /* divxu.b */
4073 if (fetch (sd, &code->src, &ea) ||
4074 fetch (sd, &code->dst, &rd))
4077 rd = UEXTSHORT (rd);
4084 tmp = (unsigned) rd % ea;
4085 res = (unsigned) rd / ea;
4093 if (store (sd, &code->dst, (res & 0xff) | (tmp << 8)))
4097 case O (O_DIVXU, SW): /* divxu.w */
4098 if (fetch (sd, &code->src, &ea) ||
4099 fetch (sd, &code->dst, &rd))
4102 ea = UEXTSHORT (ea);
4108 tmp = (unsigned) rd % ea;
4109 res = (unsigned) rd / ea;
4117 if (store (sd, &code->dst, (res & 0xffff) | (tmp << 16)))
4121 case O (O_DIVXS, SB): /* divxs.b */
4122 if (fetch (sd, &code->src, &ea) ||
4123 fetch (sd, &code->dst, &rd))
4126 rd = SEXTSHORT (rd);
4131 tmp = (int) rd % (int) ea;
4132 res = (int) rd / (int) ea;
4143 if (store (sd, &code->dst, (res & 0xff) | (tmp << 8)))
4147 case O (O_DIVXS, SW): /* divxs.w */
4148 if (fetch (sd, &code->src, &ea) ||
4149 fetch (sd, &code->dst, &rd))
4152 ea = SEXTSHORT (ea);
4156 tmp = (int) rd % (int) ea;
4157 res = (int) rd / (int) ea;
4167 n = res & 0x80000000;
4168 if (store (sd, &code->dst, (res & 0xffff) | (tmp << 16)))
4172 case O (O_EXTS, SW): /* exts.w, signed extend */
4173 if (fetch2 (sd, &code->dst, &rd))
4175 ea = rd & 0x80 ? -256 : 0;
4176 res = (rd & 0xff) + ea;
4179 case O (O_EXTS, SL): /* exts.l, signed extend */
4180 if (fetch2 (sd, &code->dst, &rd))
4182 if (code->src.type == X (OP_IMM, SL))
4184 if (fetch (sd, &code->src, &ea))
4187 if (ea == 2) /* exts.l #2, nn */
4189 /* Sign-extend from 8-bit to 32-bit. */
4190 ea = rd & 0x80 ? -256 : 0;
4191 res = (rd & 0xff) + ea;
4195 /* Sign-extend from 16-bit to 32-bit. */
4196 ea = rd & 0x8000 ? -65536 : 0;
4197 res = (rd & 0xffff) + ea;
4200 case O (O_EXTU, SW): /* extu.w, unsigned extend */
4201 if (fetch2 (sd, &code->dst, &rd))
4204 res = (rd & 0xff) + ea;
4207 case O (O_EXTU, SL): /* extu.l, unsigned extend */
4208 if (fetch2 (sd, &code->dst, &rd))
4210 if (code->src.type == X (OP_IMM, SL))
4212 if (fetch (sd, &code->src, &ea))
4215 if (ea == 2) /* extu.l #2, nn */
4217 /* Zero-extend from 8-bit to 32-bit. */
4219 res = (rd & 0xff) + ea;
4223 /* Zero-extend from 16-bit to 32-bit. */
4225 res = (rd & 0xffff) + ea;
4228 case O (O_NOP, SN): /* nop */
4231 case O (O_STM, SL): /* stm, store to memory */
4233 int nregs, firstreg, i;
4235 nregs = GET_MEMORY_B (pc + 1);
4238 firstreg = code->src.reg;
4240 for (i = firstreg; i <= firstreg + nregs; i++)
4242 h8_set_reg (sd, SP_REGNUM, h8_get_reg (sd, SP_REGNUM) - 4);
4243 SET_MEMORY_L (h8_get_reg (sd, SP_REGNUM), h8_get_reg (sd, i));
4248 case O (O_LDM, SL): /* ldm, load from memory */
4249 case O (O_RTEL, SN): /* rte/l, ldm plus rte */
4250 case O (O_RTSL, SN): /* rts/l, ldm plus rts */
4252 int nregs, firstreg, i;
4254 nregs = ((GET_MEMORY_B (pc + 1) >> 4) & 0xf);
4255 firstreg = code->dst.reg & 0xf;
4256 for (i = firstreg; i >= firstreg - nregs; i--)
4258 h8_set_reg (sd, i, GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM)));
4259 h8_set_reg (sd, SP_REGNUM, h8_get_reg (sd, SP_REGNUM) + 4);
4262 switch (code->opcode) {
4263 case O (O_RTEL, SN):
4265 case O (O_RTSL, SN):
4274 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4275 res = GET_B_REG (code->src.reg); /* FIXME fetch? */
4276 if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4277 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4278 res = res; /* Value added == 0. */
4279 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) &&
4280 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4281 res = res + 0x6; /* Value added == 6. */
4282 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4283 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4284 res = res + 0x6; /* Value added == 6. */
4285 else if (!c && (10 <= (res >> 4) && (res >> 4) <= 15) &&
4286 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4287 res = res + 0x60; /* Value added == 60. */
4288 else if (!c && (9 <= (res >> 4) && (res >> 4) <= 15) &&
4289 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4290 res = res + 0x66; /* Value added == 66. */
4291 else if (!c && (10 <= (res >> 4) && (res >> 4) <= 15) &&
4292 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4293 res = res + 0x66; /* Value added == 66. */
4294 else if ( c && (1 <= (res >> 4) && (res >> 4) <= 2) &&
4295 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4296 res = res + 0x60; /* Value added == 60. */
4297 else if ( c && (1 <= (res >> 4) && (res >> 4) <= 2) &&
4298 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4299 res = res + 0x66; /* Value added == 66. */
4300 else if (c && (1 <= (res >> 4) && (res >> 4) <= 3) &&
4301 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4302 res = res + 0x66; /* Value added == 66. */
4307 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4308 res = GET_B_REG (code->src.reg); /* FIXME fetch, fetch2... */
4309 if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4310 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4311 res = res; /* Value added == 0. */
4312 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) &&
4313 h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
4314 res = res + 0xfa; /* Value added == 0xfa. */
4315 else if ( c && (7 <= (res >> 4) && (res >> 4) <= 15) &&
4316 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4317 res = res + 0xa0; /* Value added == 0xa0. */
4318 else if (c && (6 <= (res >> 4) && (res >> 4) <= 15) &&
4319 h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
4320 res = res + 0x9a; /* Value added == 0x9a. */
4326 sim_engine_set_run_state (sd, sim_stopped, SIGILL);
4331 sim_io_printf (sd, "sim_resume: internal error.\n");
4332 sim_engine_set_run_state (sd, sim_stopped, SIGILL);
4336 if (code->dst.type == X (OP_CCR, SB) ||
4337 code->dst.type == X (OP_CCR, SW))
4339 h8_set_ccr (sd, res);
4342 else if (h8300smode &&
4343 (code->dst.type == X (OP_EXR, SB) ||
4344 code->dst.type == X (OP_EXR, SW)))
4346 h8_set_exr (sd, res);
4347 if (h8300smode) /* Get exr. */
4349 trace = (h8_get_exr (sd) >> 7) & 1;
4350 intMask = h8_get_exr (sd) & 7;
4359 /* When a branch works */
4360 if (fetch (sd, &code->src, &res))
4362 if (res & 1) /* bad address */
4364 pc = code->next_pc + res;
4367 /* Set the cond codes from res */
4370 /* Set the flags after an 8 bit inc/dec operation */
4374 v = (rd & 0x7f) == 0x7f;
4377 /* Set the flags after an 16 bit inc/dec operation */
4381 v = (rd & 0x7fff) == 0x7fff;
4384 /* Set the flags after an 32 bit inc/dec operation */
4386 n = res & 0x80000000;
4387 nz = res & 0xffffffff;
4388 v = (rd & 0x7fffffff) == 0x7fffffff;
4392 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4395 if (store2 (sd, &code->dst, rd))
4400 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4403 if (store2 (sd, &code->dst, rd))
4408 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4409 n = (rd & 0x80000000);
4410 nz = rd & 0xffffffff;
4411 if (store2 (sd, &code->dst, rd))
4416 if (store2 (sd, &code->dst, res))
4420 /* flags after a 32bit logical operation */
4421 n = res & 0x80000000;
4422 nz = res & 0xffffffff;
4427 if (store2 (sd, &code->dst, res))
4431 /* flags after a 16bit logical operation */
4438 if (store2 (sd, &code->dst, res))
4448 if (store2 (sd, &code->dst, res))
4455 switch (code->opcode / 4)
4459 v = ((rd & 0x80) == (ea & 0x80)
4460 && (rd & 0x80) != (res & 0x80));
4465 v = ((rd & 0x80) != (-ea & 0x80)
4466 && (rd & 0x80) != (res & 0x80));
4473 break; /* No effect on v flag. */
4478 if (store2 (sd, &code->dst, res))
4484 c = (res & 0x10000);
4485 switch (code->opcode / 4)
4489 v = ((rd & 0x8000) == (ea & 0x8000)
4490 && (rd & 0x8000) != (res & 0x8000));
4495 v = ((rd & 0x8000) != (-ea & 0x8000)
4496 && (rd & 0x8000) != (res & 0x8000));
4505 if (store2 (sd, &code->dst, res))
4509 n = res & 0x80000000;
4510 nz = res & 0xffffffff;
4511 switch (code->opcode / 4)
4515 v = ((rd & 0x80000000) == (ea & 0x80000000)
4516 && (rd & 0x80000000) != (res & 0x80000000));
4517 c = ((unsigned) res < (unsigned) rd) ||
4518 ((unsigned) res < (unsigned) ea);
4523 v = ((rd & 0x80000000) != (-ea & 0x80000000)
4524 && (rd & 0x80000000) != (res & 0x80000000));
4525 c = (unsigned) rd < (unsigned) -ea;
4528 v = (rd == 0x80000000);
4535 if ((res = h8_get_delayed_branch (sd)) != 0)
4538 h8_set_delayed_branch (sd, 0);
4545 if (--poll_count < 0)
4547 poll_count = POLL_QUIT_INTERVAL;
4548 if ((*sim_callback->poll_quit) != NULL
4549 && (*sim_callback->poll_quit) (sim_callback))
4550 sim_engine_set_run_state (sd, sim_stopped, SIGINT);
4552 sim_engine_get_run_state (sd, &reason, &sigrc);
4553 } while (reason == sim_running);
4555 h8_set_ticks (sd, h8_get_ticks (sd) + get_now () - tick_start);
4556 h8_set_cycles (sd, h8_get_cycles (sd) + cycles);
4557 h8_set_insts (sd, h8_get_insts (sd) + insts);
4562 h8_set_exr (sd, (trace<<7) | intMask);
4564 h8_set_mask (sd, oldmask);
4568 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
4575 for (i = 0; i < size; i++)
4577 if (addr < memory_size)
4579 h8_set_memory (sd, addr + i, buffer[i]);
4580 h8_set_cache_idx (sd, addr + i, 0);
4584 h8_set_eightbit (sd, (addr + i) & 0xff, buffer[i]);
4591 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
4596 if (addr < memory_size)
4597 memcpy (buffer, h8_get_memory_buf (sd) + addr, size);
4599 memcpy (buffer, h8_get_eightbit_buf (sd) + (addr & 0xff), size);
4605 sim_store_register (SIM_DESC sd, int rn, unsigned char *value, int length)
4610 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
4611 shortval = (value[0] << 8) | (value[1]);
4612 intval = h8300hmode ? longval : shortval;
4618 if(h8300_normal_mode)
4619 h8_set_pc (sd, shortval); /* PC for Normal mode is 2 bytes */
4621 h8_set_pc (sd, intval);
4624 sim_io_printf (sd, "sim_store_register: bad regnum %d.\n", rn);
4633 h8_set_reg (sd, rn, intval);
4636 h8_set_ccr (sd, intval);
4639 h8_set_exr (sd, intval);
4642 h8_set_sbr (sd, intval);
4645 h8_set_vbr (sd, intval);
4648 h8_set_mach (sd, intval);
4651 h8_set_macl (sd, intval);
4654 h8_set_cycles (sd, longval);
4658 h8_set_insts (sd, longval);
4662 h8_set_ticks (sd, longval);
4669 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
4676 if (!h8300smode && rn >= EXR_REGNUM)
4681 sim_io_printf (sd, "sim_fetch_register: bad regnum %d.\n", rn);
4685 v = h8_get_ccr (sd);
4688 v = h8_get_exr (sd);
4694 v = h8_get_sbr (sd);
4697 v = h8_get_vbr (sd);
4700 v = h8_get_mach (sd);
4703 v = h8_get_macl (sd);
4713 v = h8_get_reg (sd, rn);
4716 v = h8_get_cycles (sd);
4720 v = h8_get_ticks (sd);
4724 v = h8_get_insts (sd);
4728 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4729 if ((h8300hmode || longreg) && !(rn == PC_REGNUM && h8300_normal_mode))
4745 set_simcache_size (SIM_DESC sd, int n)
4748 free (sd->sim_cache);
4751 sd->sim_cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
4752 memset (sd->sim_cache, 0, sizeof (decoded_inst) * n);
4753 sd->sim_cache_size = n;
4758 sim_info (SIM_DESC sd, int verbose)
4760 double timetaken = (double) h8_get_ticks (sd) / (double) now_persec ();
4761 double virttime = h8_get_cycles (sd) / 10.0e6;
4763 sim_io_printf (sd, "\n\n#instructions executed %10d\n", h8_get_insts (sd));
4764 sim_io_printf (sd, "#cycles (v approximate) %10d\n", h8_get_cycles (sd));
4765 sim_io_printf (sd, "#real time taken %10.4f\n", timetaken);
4766 sim_io_printf (sd, "#virtual time taken %10.4f\n", virttime);
4767 if (timetaken != 0.0)
4768 sim_io_printf (sd, "#simulation ratio %10.4f\n", virttime / timetaken);
4769 sim_io_printf (sd, "#compiles %10d\n", h8_get_compiles (sd));
4770 sim_io_printf (sd, "#cache size %10d\n", sd->sim_cache_size);
4773 /* This to be conditional on `what' (aka `verbose'),
4774 however it was never passed as non-zero. */
4778 for (i = 0; i < O_LAST; i++)
4780 if (h8_get_stats (sd, i))
4781 sim_io_printf (sd, "%d: %d\n", i, h8_get_stats (sd, i));
4787 /* Indicate whether the cpu is an H8/300 or H8/300H.
4788 FLAG is non-zero for the H8/300H. */
4791 set_h8300h (unsigned long machine)
4793 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4794 This function being replaced by a sim_open:ARGV configuration
4797 h8300hmode = h8300smode = h8300sxmode = h8300_normal_mode = 0;
4799 if (machine == bfd_mach_h8300sx || machine == bfd_mach_h8300sxn)
4802 if (machine == bfd_mach_h8300s || machine == bfd_mach_h8300sn || h8300sxmode)
4805 if (machine == bfd_mach_h8300h || machine == bfd_mach_h8300hn || h8300smode)
4808 if(machine == bfd_mach_h8300hn || machine == bfd_mach_h8300sn || machine == bfd_mach_h8300sxn)
4809 h8300_normal_mode = 1;
4812 /* H8300-specific options.
4813 TODO: These really should be merged into the common model modules. */
4821 h8300_option_handler (SIM_DESC sd, sim_cpu *cpu ATTRIBUTE_UNUSED, int opt,
4822 char *arg, int is_command ATTRIBUTE_UNUSED)
4824 switch ((H8300_OPTIONS) opt)
4827 set_h8300h (bfd_mach_h8300h);
4830 set_h8300h (bfd_mach_h8300s);
4832 case OPTION_H8300SX:
4833 set_h8300h (bfd_mach_h8300sx);
4837 /* We'll actually never get here; the caller handles the error
4839 sim_io_eprintf (sd, "Unknown option `%s'\n", arg);
4846 static const OPTION h8300_options[] =
4848 { {"h8300h", no_argument, NULL, OPTION_H8300H},
4849 'h', NULL, "Indicate the CPU is H8/300H",
4850 h8300_option_handler },
4851 { {"h8300s", no_argument, NULL, OPTION_H8300S},
4852 'S', NULL, "Indicate the CPU is H8S",
4853 h8300_option_handler },
4854 { {"h8300sx", no_argument, NULL, OPTION_H8300SX},
4855 'x', NULL, "Indicate the CPU is H8SX",
4856 h8300_option_handler },
4857 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
4861 h8300_pc_get (sim_cpu *cpu)
4867 h8300_pc_set (sim_cpu *cpu, sim_cia pc)
4872 /* Cover function of sim_state_free to free the cpu buffers as well. */
4875 free_state (SIM_DESC sd)
4877 if (STATE_MODULES (sd) != NULL)
4878 sim_module_uninstall (sd);
4880 /* Fixme: free buffers in _sim_cpu. */
4881 sim_state_free (sd);
4885 sim_open (SIM_OPEN_KIND kind,
4886 struct host_callback_struct *callback,
4894 sd = sim_state_alloc (kind, callback);
4896 /* The cpu data is kept in a separately allocated chunk of memory. */
4897 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
4903 cpu = STATE_CPU (sd, 0);
4904 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
4905 sim_state_initialize (sd, cpu);
4906 /* sim_cpu object is new, so some initialization is needed. */
4907 init_pointers_needed = 1;
4909 /* For compatibility (FIXME: is this right?). */
4910 current_alignment = NONSTRICT_ALIGNMENT;
4911 current_target_byte_order = BIG_ENDIAN;
4913 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
4919 if (sim_add_option_table (sd, NULL, h8300_options) != SIM_RC_OK)
4925 /* getopt will print the error message so we just have to exit if
4926 this fails. FIXME: Hmmm... in the case of gdb we need getopt
4927 to call print_filtered. */
4928 if (sim_parse_args (sd, argv) != SIM_RC_OK)
4930 /* Uninstall the modules to avoid memory leaks,
4931 file descriptor leaks, etc. */
4936 /* Check for/establish the a reference program image. */
4937 if (sim_analyze_program (sd,
4938 (STATE_PROG_ARGV (sd) != NULL
4939 ? *STATE_PROG_ARGV (sd)
4940 : NULL), abfd) != SIM_RC_OK)
4946 /* Establish any remaining configuration options. */
4947 if (sim_config (sd) != SIM_RC_OK)
4953 if (sim_post_argv_init (sd) != SIM_RC_OK)
4955 /* Uninstall the modules to avoid memory leaks,
4956 file descriptor leaks, etc. */
4961 /* CPU specific initialization. */
4962 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
4964 SIM_CPU *cpu = STATE_CPU (sd, i);
4966 CPU_PC_FETCH (cpu) = h8300_pc_get;
4967 CPU_PC_STORE (cpu) = h8300_pc_set;
4970 /* sim_hw_configure (sd); */
4972 /* FIXME: Much of the code in sim_load can be moved here. */
4977 /* Called by gdb to load a program into memory. */
4980 sim_load (SIM_DESC sd, const char *prog, bfd *abfd, int from_tty)
4984 /* FIXME: The code below that sets a specific variant of the H8/300
4985 being simulated should be moved to sim_open(). */
4987 /* See if the file is for the H8/300 or H8/300H. */
4988 /* ??? This may not be the most efficient way. The z8k simulator
4989 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4993 prog_bfd = bfd_openr (prog, NULL);
4994 if (prog_bfd != NULL)
4996 /* Set the cpu type. We ignore failure from bfd_check_format
4997 and bfd_openr as sim_load_file checks too. */
4998 if (bfd_check_format (prog_bfd, bfd_object))
5000 set_h8300h (bfd_get_mach (prog_bfd));
5004 /* If we're using gdb attached to the simulator, then we have to
5005 reallocate memory for the simulator.
5007 When gdb first starts, it calls fetch_registers (among other
5008 functions), which in turn calls init_pointers, which allocates
5011 The problem is when we do that, we don't know whether we're
5012 debugging an H8/300 or H8/300H program.
5014 This is the first point at which we can make that determination,
5015 so we just reallocate memory now; this will also allow us to handle
5016 switching between H8/300 and H8/300H programs without exiting
5019 if (h8300smode && !h8300_normal_mode)
5020 memory_size = H8300S_MSIZE;
5021 else if (h8300hmode && !h8300_normal_mode)
5022 memory_size = H8300H_MSIZE;
5024 memory_size = H8300_MSIZE;
5026 if (h8_get_memory_buf (sd))
5027 free (h8_get_memory_buf (sd));
5028 if (h8_get_cache_idx_buf (sd))
5029 free (h8_get_cache_idx_buf (sd));
5030 if (h8_get_eightbit_buf (sd))
5031 free (h8_get_eightbit_buf (sd));
5033 h8_set_memory_buf (sd, (unsigned char *)
5034 calloc (sizeof (char), memory_size));
5035 h8_set_cache_idx_buf (sd, (unsigned short *)
5036 calloc (sizeof (short), memory_size));
5037 sd->memory_size = memory_size;
5038 h8_set_eightbit_buf (sd, (unsigned char *) calloc (sizeof (char), 256));
5040 /* `msize' must be a power of two. */
5041 if ((memory_size & (memory_size - 1)) != 0)
5043 sim_io_printf (sd, "sim_load: bad memory size.\n");
5046 h8_set_mask (sd, memory_size - 1);
5048 if (sim_load_file (sd, STATE_MY_NAME (sd), STATE_CALLBACK (sd), prog,
5049 prog_bfd, STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG,
5053 /* Close the bfd if we opened it. */
5054 if (abfd == NULL && prog_bfd != NULL)
5055 bfd_close (prog_bfd);
5059 /* Close the bfd if we opened it. */
5060 if (abfd == NULL && prog_bfd != NULL)
5061 bfd_close (prog_bfd);
5066 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
5073 h8_set_pc (sd, bfd_get_start_address (abfd));
5077 /* Command Line support. */
5080 /* Counting the no. of commandline arguments. */
5081 for (no_of_args = 0; argv[no_of_args] != NULL; no_of_args++)
5084 /* Allocating memory for the argv pointers. */
5085 h8_set_command_line (sd, (char **) malloc ((sizeof (char *))
5086 * (no_of_args + 1)));
5088 for (i = 0; i < no_of_args; i++)
5090 /* Copying the argument string. */
5091 h8_set_cmdline_arg (sd, i, (char *) strdup (argv[i]));
5093 h8_set_cmdline_arg (sd, i, NULL);