2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
28 #ifdef HAVE_SYS_PARAM_H
29 #include <sys/param.h>
34 #include "gdb/sim-h8300.h"
36 #include "sys/types.h"
37 #include "sim-options.h"
45 /* FIXME: Needs to live in header file.
46 This header should also include the things in remote-sim.h.
47 One could move this to remote-sim.h but this function isn't needed
49 static void set_simcache_size (SIM_DESC, int);
51 #define X(op, size) (op * 4 + size)
53 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
55 #define h8_opcodes ops
57 #include "opcode/h8300.h"
59 /* CPU data object: */
62 sim_state_initialize (SIM_DESC sd, sim_cpu *cpu)
64 /* FIXME: not really necessary, since sim_cpu_alloc calls zalloc. */
66 memset (&cpu->regs, 0, sizeof(cpu->regs));
67 cpu->regs[SBR_REGNUM] = 0xFFFFFF00;
69 cpu->delayed_branch = 0;
74 /* Initialize local simulator state. */
76 sd->sim_cache_size = 0;
82 memset (&cpu->stats, 0, sizeof (cpu->stats));
88 h8_get_pc (SIM_DESC sd)
90 return (STATE_CPU (sd, 0)) -> pc;
94 h8_set_pc (SIM_DESC sd, unsigned int val)
96 (STATE_CPU (sd, 0)) -> pc = val;
100 h8_get_ccr (SIM_DESC sd)
102 return (STATE_CPU (sd, 0)) -> regs[CCR_REGNUM];
106 h8_set_ccr (SIM_DESC sd, unsigned int val)
108 (STATE_CPU (sd, 0)) -> regs[CCR_REGNUM] = val;
112 h8_get_exr (SIM_DESC sd)
114 return (STATE_CPU (sd, 0)) -> regs[EXR_REGNUM];
118 h8_set_exr (SIM_DESC sd, unsigned int val)
120 (STATE_CPU (sd, 0)) -> regs[EXR_REGNUM] = val;
124 h8_get_sbr (SIM_DESC sd)
126 return (STATE_CPU (sd, 0)) -> regs[SBR_REGNUM];
130 h8_set_sbr (SIM_DESC sd, int val)
132 (STATE_CPU (sd, 0)) -> regs[SBR_REGNUM] = val;
136 h8_get_vbr (SIM_DESC sd)
138 return (STATE_CPU (sd, 0)) -> regs[VBR_REGNUM];
142 h8_set_vbr (SIM_DESC sd, int val)
144 (STATE_CPU (sd, 0)) -> regs[VBR_REGNUM] = val;
148 h8_get_cache_top (SIM_DESC sd)
150 return sd -> cache_top;
154 h8_set_cache_top (SIM_DESC sd, int val)
156 sd -> cache_top = val;
160 h8_get_mask (SIM_DESC sd)
162 return (STATE_CPU (sd, 0)) -> mask;
166 h8_set_mask (SIM_DESC sd, int val)
168 (STATE_CPU (sd, 0)) -> mask = val;
172 h8_get_exception (SIM_DESC sd)
174 return (STATE_CPU (sd, 0)) -> exception;
178 h8_set_exception (SIM_DESC sd, int val)
180 (STATE_CPU (sd, 0)) -> exception = val;
183 static enum h8300_sim_state
184 h8_get_state (SIM_DESC sd)
190 h8_set_state (SIM_DESC sd, enum h8300_sim_state val)
196 h8_get_cycles (SIM_DESC sd)
198 return (STATE_CPU (sd, 0)) -> regs[CYCLE_REGNUM];
202 h8_set_cycles (SIM_DESC sd, unsigned int val)
204 (STATE_CPU (sd, 0)) -> regs[CYCLE_REGNUM] = val;
208 h8_get_insts (SIM_DESC sd)
210 return (STATE_CPU (sd, 0)) -> regs[INST_REGNUM];
214 h8_set_insts (SIM_DESC sd, unsigned int val)
216 (STATE_CPU (sd, 0)) -> regs[INST_REGNUM] = val;
220 h8_get_ticks (SIM_DESC sd)
222 return (STATE_CPU (sd, 0)) -> regs[TICK_REGNUM];
226 h8_set_ticks (SIM_DESC sd, unsigned int val)
228 (STATE_CPU (sd, 0)) -> regs[TICK_REGNUM] = val;
232 h8_get_mach (SIM_DESC sd)
234 return (STATE_CPU (sd, 0)) -> regs[MACH_REGNUM];
238 h8_set_mach (SIM_DESC sd, unsigned int val)
240 (STATE_CPU (sd, 0)) -> regs[MACH_REGNUM] = val;
244 h8_get_macl (SIM_DESC sd)
246 return (STATE_CPU (sd, 0)) -> regs[MACL_REGNUM];
250 h8_set_macl (SIM_DESC sd, unsigned int val)
252 (STATE_CPU (sd, 0)) -> regs[MACL_REGNUM] = val;
256 h8_get_compiles (SIM_DESC sd)
258 return sd -> compiles;
262 h8_increment_compiles (SIM_DESC sd)
267 static unsigned int *
268 h8_get_reg_buf (SIM_DESC sd)
270 return &(((STATE_CPU (sd, 0)) -> regs)[0]);
274 h8_get_reg (SIM_DESC sd, int regnum)
276 return (STATE_CPU (sd, 0)) -> regs[regnum];
280 h8_set_reg (SIM_DESC sd, int regnum, int val)
282 (STATE_CPU (sd, 0)) -> regs[regnum] = val;
287 h8_get_stats (SIM_DESC sd, int idx)
289 return sd -> stats[idx];
293 h8_increment_stats (SIM_DESC sd, int idx)
299 static unsigned short *
300 h8_get_cache_idx_buf (SIM_DESC sd)
302 return sd -> cache_idx;
306 h8_set_cache_idx_buf (SIM_DESC sd, unsigned short *ptr)
308 sd -> cache_idx = ptr;
311 static unsigned short
312 h8_get_cache_idx (SIM_DESC sd, unsigned int idx)
314 if (idx > sd->memory_size)
315 return (unsigned short) -1;
316 return sd -> cache_idx[idx];
320 h8_set_cache_idx (SIM_DESC sd, int idx, unsigned int val)
322 sd -> cache_idx[idx] = (unsigned short) val;
325 static unsigned char *
326 h8_get_memory_buf (SIM_DESC sd)
328 return (STATE_CPU (sd, 0)) -> memory;
332 h8_set_memory_buf (SIM_DESC sd, unsigned char *ptr)
334 (STATE_CPU (sd, 0)) -> memory = ptr;
338 h8_get_memory (SIM_DESC sd, int idx)
340 return (STATE_CPU (sd, 0)) -> memory[idx];
344 h8_set_memory (SIM_DESC sd, int idx, unsigned int val)
346 (STATE_CPU (sd, 0)) -> memory[idx] = (unsigned char) val;
349 static unsigned char *
350 h8_get_eightbit_buf (SIM_DESC sd)
352 return (STATE_CPU (sd, 0)) -> eightbit;
356 h8_set_eightbit_buf (SIM_DESC sd, unsigned char *ptr)
358 (STATE_CPU (sd, 0)) -> eightbit = ptr;
362 h8_get_eightbit (SIM_DESC sd, int idx)
364 return (STATE_CPU (sd, 0)) -> eightbit[idx];
368 h8_set_eightbit (SIM_DESC sd, int idx, unsigned int val)
370 (STATE_CPU (sd, 0)) -> eightbit[idx] = (unsigned char) val;
374 h8_get_delayed_branch (SIM_DESC sd)
376 return (STATE_CPU (sd, 0)) -> delayed_branch;
380 h8_set_delayed_branch (SIM_DESC sd, unsigned int dest)
382 (STATE_CPU (sd, 0)) -> delayed_branch = dest;
386 h8_get_command_line (SIM_DESC sd)
388 return (STATE_CPU (sd, 0)) -> command_line;
392 h8_set_command_line (SIM_DESC sd, char ** val)
394 (STATE_CPU (sd, 0)) -> command_line = val;
398 h8_get_cmdline_arg (SIM_DESC sd, int index)
400 return (STATE_CPU (sd, 0)) -> command_line[index];
404 h8_set_cmdline_arg (SIM_DESC sd, int index, char * val)
406 (STATE_CPU (sd, 0)) -> command_line[index] = val;
409 /* MAC Saturation Mode */
411 h8_get_macS (SIM_DESC sd)
413 return (STATE_CPU (sd, 0)) -> macS;
417 h8_set_macS (SIM_DESC sd, int val)
419 (STATE_CPU (sd, 0)) -> macS = (val != 0);
424 h8_get_macZ (SIM_DESC sd)
426 return (STATE_CPU (sd, 0)) -> macZ;
430 h8_set_macZ (SIM_DESC sd, int val)
432 (STATE_CPU (sd, 0)) -> macZ = (val != 0);
435 /* MAC Negative Flag */
437 h8_get_macN (SIM_DESC sd)
439 return (STATE_CPU (sd, 0)) -> macN;
443 h8_set_macN (SIM_DESC sd, int val)
445 (STATE_CPU (sd, 0)) -> macN = (val != 0);
448 /* MAC Overflow Flag */
450 h8_get_macV (SIM_DESC sd)
452 return (STATE_CPU (sd, 0)) -> macV;
456 h8_set_macV (SIM_DESC sd, int val)
458 (STATE_CPU (sd, 0)) -> macV = (val != 0);
461 /* End CPU data object. */
463 /* The rate at which to call the host's poll_quit callback. */
465 enum { POLL_QUIT_INTERVAL = 0x80000 };
467 #define LOW_BYTE(x) ((x) & 0xff)
468 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
469 #define P(X, Y) ((X << 8) | Y)
478 #define I (intMaskBit != 0)
480 #define BUILDSR(SD) \
481 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
482 | (N << 3) | (Z << 2) | (V << 1) | C)
485 /* Get Status Register (flags). */ \
486 c = (h8_get_ccr (sd) >> 0) & 1; \
487 v = (h8_get_ccr (sd) >> 1) & 1; \
488 nz = !((h8_get_ccr (sd) >> 2) & 1); \
489 n = (h8_get_ccr (sd) >> 3) & 1; \
490 u = (h8_get_ccr (sd) >> 4) & 1; \
491 h = (h8_get_ccr (sd) >> 5) & 1; \
492 ui = ((h8_get_ccr (sd) >> 6) & 1); \
493 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
496 #ifdef __CHAR_IS_SIGNED__
497 #define SEXTCHAR(x) ((char) (x))
501 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
504 #define UEXTCHAR(x) ((x) & 0xff)
505 #define UEXTSHORT(x) ((x) & 0xffff)
506 #define SEXTSHORT(x) ((short) (x))
510 int h8300_normal_mode = 0;
513 static int memory_size;
518 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
540 return (h8300hmode && !h8300_normal_mode)? SL : SW;
545 /* Simulate an indirection / dereference.
546 return 0 for success, -1 for failure.
550 lvalue (SIM_DESC sd, int x, int rn, unsigned int *val)
552 if (val == NULL) /* Paranoia. */
558 if (rn == ZERO_REGNUM)
559 *val = X (OP_IMM, SP);
561 *val = X (OP_REG, SP);
564 *val = X (OP_MEM, SP);
567 sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
576 if (h8300smode && !h8300_normal_mode)
578 else if (h8300hmode && !h8300_normal_mode)
585 decode (SIM_DESC sd, int addr, unsigned char *data, decoded_inst *dst)
587 int cst[3] = {0, 0, 0};
588 int reg[3] = {0, 0, 0};
589 int rdisp[3] = {0, 0, 0};
591 const struct h8_opcode *q;
596 /* Find the exact opcode/arg combo. */
597 for (q = h8_opcodes; q->name; q++)
599 const op_type *nib = q->data.nib;
600 unsigned int len = 0;
602 if ((q->available == AV_H8SX && !h8300sxmode) ||
603 (q->available == AV_H8S && !h8300smode) ||
604 (q->available == AV_H8H && !h8300hmode))
607 cst[0] = cst[1] = cst[2] = 0;
608 reg[0] = reg[1] = reg[2] = 0;
609 rdisp[0] = rdisp[1] = rdisp[2] = 0;
613 op_type looking_for = *nib;
614 int thisnib = data[len / 2];
616 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
617 opnum = ((looking_for & OP3) ? 2 :
618 (looking_for & DST) ? 1 : 0);
620 if (looking_for < 16 && looking_for >= 0)
622 if (looking_for != thisnib)
627 if (looking_for & B31)
629 if (!((thisnib & 0x8) != 0))
632 looking_for = (op_type) (looking_for & ~B31);
635 else if (looking_for & B30)
637 if (!((thisnib & 0x8) == 0))
640 looking_for = (op_type) (looking_for & ~B30);
643 if (looking_for & B21)
645 if (!((thisnib & 0x4) != 0))
648 looking_for = (op_type) (looking_for & ~B21);
651 else if (looking_for & B20)
653 if (!((thisnib & 0x4) == 0))
656 looking_for = (op_type) (looking_for & ~B20);
659 if (looking_for & B11)
661 if (!((thisnib & 0x2) != 0))
664 looking_for = (op_type) (looking_for & ~B11);
667 else if (looking_for & B10)
669 if (!((thisnib & 0x2) == 0))
672 looking_for = (op_type) (looking_for & ~B10);
675 if (looking_for & B01)
677 if (!((thisnib & 0x1) != 0))
680 looking_for = (op_type) (looking_for & ~B01);
683 else if (looking_for & B00)
685 if (!((thisnib & 0x1) == 0))
688 looking_for = (op_type) (looking_for & ~B00);
691 if (looking_for & IGNORE)
693 /* Hitachi has declared that IGNORE must be zero. */
697 else if ((looking_for & MODE) == DATA)
699 ; /* Skip embedded data. */
701 else if ((looking_for & MODE) == DBIT)
703 /* Exclude adds/subs by looking at bit 0 and 2, and
704 make sure the operand size, either w or l,
705 matches by looking at bit 1. */
706 if ((looking_for & 7) != (thisnib & 7))
709 cst[opnum] = (thisnib & 0x8) ? 2 : 1;
711 else if ((looking_for & MODE) == REG ||
712 (looking_for & MODE) == LOWREG ||
713 (looking_for & MODE) == IND ||
714 (looking_for & MODE) == PREINC ||
715 (looking_for & MODE) == POSTINC ||
716 (looking_for & MODE) == PREDEC ||
717 (looking_for & MODE) == POSTDEC)
719 reg[opnum] = thisnib;
721 else if (looking_for & CTRL)
724 if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) ||
725 ((looking_for & MODE) == EXR && (thisnib != C_EXR)) ||
726 ((looking_for & MODE) == MACH && (thisnib != C_MACH)) ||
727 ((looking_for & MODE) == MACL && (thisnib != C_MACL)) ||
728 ((looking_for & MODE) == VBR && (thisnib != C_VBR)) ||
729 ((looking_for & MODE) == SBR && (thisnib != C_SBR)))
731 if (((looking_for & MODE) == CCR_EXR &&
732 (thisnib != C_CCR && thisnib != C_EXR)) ||
733 ((looking_for & MODE) == VBR_SBR &&
734 (thisnib != C_VBR && thisnib != C_SBR)) ||
735 ((looking_for & MODE) == MACREG &&
736 (thisnib != C_MACH && thisnib != C_MACL)))
738 if (((looking_for & MODE) == CC_EX_VB_SB &&
739 (thisnib != C_CCR && thisnib != C_EXR &&
740 thisnib != C_VBR && thisnib != C_SBR)))
743 reg[opnum] = thisnib;
745 else if ((looking_for & MODE) == ABS)
747 /* Absolute addresses are unsigned. */
748 switch (looking_for & SIZE)
751 cst[opnum] = UEXTCHAR (data[len / 2]);
755 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
759 (data[len / 2 + 0] << 24) +
760 (data[len / 2 + 1] << 16) +
761 (data[len / 2 + 2] << 8) +
765 printf ("decode: bad size ABS: %d\n",
766 (looking_for & SIZE));
770 else if ((looking_for & MODE) == DISP ||
771 (looking_for & MODE) == PCREL ||
772 (looking_for & MODE) == INDEXB ||
773 (looking_for & MODE) == INDEXW ||
774 (looking_for & MODE) == INDEXL)
776 switch (looking_for & SIZE)
779 cst[opnum] = thisnib & 3;
782 cst[opnum] = SEXTCHAR (data[len / 2]);
785 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
786 cst[opnum] = (short) cst[opnum]; /* Sign extend. */
789 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
793 (data[len / 2 + 0] << 24) +
794 (data[len / 2 + 1] << 16) +
795 (data[len / 2 + 2] << 8) +
799 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
800 (looking_for & SIZE));
804 else if ((looking_for & SIZE) == L_16 ||
805 (looking_for & SIZE) == L_16U)
807 cst[opnum] = (data[len / 2] << 8) + data[len / 2 + 1];
808 /* Immediates are always unsigned. */
809 if ((looking_for & SIZE) != L_16U &&
810 (looking_for & MODE) != IMM)
811 cst[opnum] = (short) cst[opnum]; /* Sign extend. */
813 else if (looking_for & ABSJMP)
815 switch (looking_for & SIZE) {
817 cst[opnum] = (data[1] << 16) | (data[2] << 8) | (data[3]);
821 (data[len / 2 + 0] << 24) +
822 (data[len / 2 + 1] << 16) +
823 (data[len / 2 + 2] << 8) +
827 printf ("decode: bad size ABSJMP: %d\n",
828 (looking_for & SIZE));
832 else if ((looking_for & MODE) == MEMIND)
834 cst[opnum] = data[1];
836 else if ((looking_for & MODE) == VECIND)
838 if(h8300_normal_mode)
839 cst[opnum] = ((data[1] & 0x7f) + 0x80) * 2;
841 cst[opnum] = ((data[1] & 0x7f) + 0x80) * 4;
842 cst[opnum] += h8_get_vbr (sd); /* Add vector base reg. */
844 else if ((looking_for & SIZE) == L_32)
849 (data[i + 0] << 24) |
850 (data[i + 1] << 16) |
854 else if ((looking_for & SIZE) == L_24)
859 (data[i + 0] << 16) |
863 else if (looking_for & DISPREG)
865 rdisp[opnum] = thisnib & 0x7;
867 else if ((looking_for & MODE) == KBIT)
884 else if ((looking_for & SIZE) == L_8)
886 if ((looking_for & MODE) == ABS)
888 /* Will be combined with contents of SBR_REGNUM
889 by fetch (). For all modes except h8sx, this
890 will always contain the value 0xFFFFFF00. */
891 cst[opnum] = data[len / 2] & 0xff;
895 cst[opnum] = data[len / 2] & 0xff;
898 else if ((looking_for & SIZE) == L_2)
900 cst[opnum] = thisnib & 3;
902 else if ((looking_for & SIZE) == L_3 ||
903 (looking_for & SIZE) == L_3NZ)
905 cst[opnum] = thisnib & 7;
906 if (cst[opnum] == 0 && (looking_for & SIZE) == L_3NZ)
909 else if ((looking_for & SIZE) == L_4)
911 cst[opnum] = thisnib & 15;
913 else if ((looking_for & SIZE) == L_5)
915 cst[opnum] = data[len / 2] & 0x1f;
917 else if (looking_for == E)
922 /* Fill in the args. */
924 const op_type *args = q->args.nib;
929 nargs < 3 && *args != E;
935 opnum = ((x & OP3) ? 2 :
944 if ((x & MODE) == IMM ||
945 (x & MODE) == KBIT ||
948 /* Use the instruction to determine
950 p->type = X (OP_IMM, OP_SIZE (q->how));
951 p->literal = cst[opnum];
953 else if ((x & MODE) == CONST_2 ||
954 (x & MODE) == CONST_4 ||
955 (x & MODE) == CONST_8 ||
956 (x & MODE) == CONST_16)
958 /* Use the instruction to determine
960 p->type = X (OP_IMM, OP_SIZE (q->how));
962 case CONST_2: p->literal = 2; break;
963 case CONST_4: p->literal = 4; break;
964 case CONST_8: p->literal = 8; break;
965 case CONST_16: p->literal = 16; break;
968 else if ((x & MODE) == REG)
970 p->type = X (OP_REG, bitfrom (x));
973 else if ((x & MODE) == LOWREG)
975 p->type = X (OP_LOWREG, bitfrom (x));
978 else if ((x & MODE) == PREINC)
980 /* Use the instruction to determine
982 p->type = X (OP_PREINC, OP_SIZE (q->how));
983 p->reg = reg[opnum] & 0x7;
985 else if ((x & MODE) == POSTINC)
987 /* Use the instruction to determine
989 p->type = X (OP_POSTINC, OP_SIZE (q->how));
990 p->reg = reg[opnum] & 0x7;
992 else if ((x & MODE) == PREDEC)
994 /* Use the instruction to determine
996 p->type = X (OP_PREDEC, OP_SIZE (q->how));
997 p->reg = reg[opnum] & 0x7;
999 else if ((x & MODE) == POSTDEC)
1001 /* Use the instruction to determine
1002 the operand size. */
1003 p->type = X (OP_POSTDEC, OP_SIZE (q->how));
1004 p->reg = reg[opnum] & 0x7;
1006 else if ((x & MODE) == IND)
1008 /* Note: an indirect is transformed into
1009 a displacement of zero.
1011 /* Use the instruction to determine
1012 the operand size. */
1013 p->type = X (OP_DISP, OP_SIZE (q->how));
1014 p->reg = reg[opnum] & 0x7;
1016 if (OP_KIND (q->how) == O_JSR ||
1017 OP_KIND (q->how) == O_JMP)
1018 if (lvalue (sd, p->type, p->reg, (unsigned int *)&p->type))
1021 else if ((x & MODE) == ABS)
1023 /* Note: a 16 or 32 bit ABS is transformed into a
1024 displacement from pseudo-register ZERO_REGNUM,
1025 which is always zero. An 8 bit ABS becomes
1026 a displacement from SBR_REGNUM.
1028 /* Use the instruction to determine
1029 the operand size. */
1030 p->type = X (OP_DISP, OP_SIZE (q->how));
1031 p->literal = cst[opnum];
1033 /* 8-bit ABS is displacement from SBR.
1034 16 and 32-bit ABS are displacement from ZERO.
1035 (SBR will always be zero except for h8/sx)
1037 if ((x & SIZE) == L_8)
1038 p->reg = SBR_REGNUM;
1040 p->reg = ZERO_REGNUM;;
1042 else if ((x & MODE) == MEMIND ||
1043 (x & MODE) == VECIND)
1045 /* Size doesn't matter. */
1046 p->type = X (OP_MEM, SB);
1047 p->literal = cst[opnum];
1048 if (OP_KIND (q->how) == O_JSR ||
1049 OP_KIND (q->how) == O_JMP)
1050 if (lvalue (sd, p->type, p->reg, (unsigned int *)&p->type))
1053 else if ((x & MODE) == PCREL)
1055 /* Size doesn't matter. */
1056 p->type = X (OP_PCREL, SB);
1057 p->literal = cst[opnum];
1059 else if (x & ABSJMP)
1061 p->type = X (OP_IMM, SP);
1062 p->literal = cst[opnum];
1064 else if ((x & MODE) == INDEXB)
1066 p->type = X (OP_INDEXB, OP_SIZE (q->how));
1067 p->literal = cst[opnum];
1068 p->reg = rdisp[opnum];
1070 else if ((x & MODE) == INDEXW)
1072 p->type = X (OP_INDEXW, OP_SIZE (q->how));
1073 p->literal = cst[opnum];
1074 p->reg = rdisp[opnum];
1076 else if ((x & MODE) == INDEXL)
1078 p->type = X (OP_INDEXL, OP_SIZE (q->how));
1079 p->literal = cst[opnum];
1080 p->reg = rdisp[opnum];
1082 else if ((x & MODE) == DISP)
1084 /* Yuck -- special for mova args. */
1085 if (strncmp (q->name, "mova", 4) == 0 &&
1088 /* Mova can have a DISP2 dest, with an
1089 INDEXB or INDEXW src. The multiplier
1090 for the displacement value is determined
1091 by the src operand, not by the insn. */
1093 switch (OP_KIND (dst->src.type))
1096 p->type = X (OP_DISP, SB);
1097 p->literal = cst[opnum];
1100 p->type = X (OP_DISP, SW);
1101 p->literal = cst[opnum] * 2;
1109 p->type = X (OP_DISP, OP_SIZE (q->how));
1110 p->literal = cst[opnum];
1111 /* DISP2 is special. */
1112 if ((x & SIZE) == L_2)
1113 switch (OP_SIZE (q->how))
1116 case SW: p->literal *= 2; break;
1117 case SL: p->literal *= 4; break;
1120 p->reg = rdisp[opnum];
1127 p->type = X (OP_CCR, SB);
1130 p->type = X (OP_EXR, SB);
1133 p->type = X (OP_MACH, SL);
1136 p->type = X (OP_MACL, SL);
1139 p->type = X (OP_VBR, SL);
1142 p->type = X (OP_SBR, SL);
1146 else if ((x & MODE) == CCR)
1150 else if ((x & MODE) == EXR)
1155 printf ("Hmmmm 0x%x...\n", x);
1161 /* Unary operators: treat src and dst as equivalent. */
1162 if (dst->dst.type == -1)
1163 dst->dst = dst->src;
1164 if (dst->src.type == -1)
1165 dst->src = dst->dst;
1167 dst->opcode = q->how;
1168 dst->cycles = q->time;
1170 /* And jsr's to these locations are turned into
1173 if (OP_KIND (dst->opcode) == O_JSR)
1175 switch (dst->src.literal)
1178 dst->opcode = O (O_SYS_OPEN, SB);
1181 dst->opcode = O (O_SYS_READ, SB);
1184 dst->opcode = O (O_SYS_WRITE, SB);
1187 dst->opcode = O (O_SYS_LSEEK, SB);
1190 dst->opcode = O (O_SYS_CLOSE, SB);
1193 dst->opcode = O (O_SYS_STAT, SB);
1196 dst->opcode = O (O_SYS_FSTAT, SB);
1199 dst->opcode = O (O_SYS_CMDLINE, SB);
1202 /* End of Processing for system calls. */
1205 dst->next_pc = addr + len / 2;
1209 printf ("Don't understand 0x%x \n", looking_for);
1220 /* Fell off the end. */
1221 dst->opcode = O (O_ILL, SB);
1225 compile (SIM_DESC sd, int pc)
1229 /* Find the next cache entry to use. */
1230 idx = h8_get_cache_top (sd) + 1;
1231 h8_increment_compiles (sd);
1232 if (idx >= sd->sim_cache_size)
1236 h8_set_cache_top (sd, idx);
1238 /* Throw away its old meaning. */
1239 h8_set_cache_idx (sd, sd->sim_cache[idx].oldpc, 0);
1241 /* Set to new address. */
1242 sd->sim_cache[idx].oldpc = pc;
1244 /* Fill in instruction info. */
1245 decode (sd, pc, h8_get_memory_buf (sd) + pc, sd->sim_cache + idx);
1247 /* Point to new cache entry. */
1248 h8_set_cache_idx (sd, pc, idx);
1252 static unsigned char *breg[32];
1253 static unsigned short *wreg[16];
1254 static unsigned int *lreg[18];
1256 #define GET_B_REG(X) *(breg[X])
1257 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1258 #define GET_W_REG(X) *(wreg[X])
1259 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1260 #define GET_L_REG(X) h8_get_reg (sd, X)
1261 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1263 #define GET_MEMORY_L(X) \
1264 ((X) < memory_size \
1265 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1266 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1267 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 24) \
1268 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 16) \
1269 | (h8_get_eightbit (sd, ((X)+2) & 0xff) << 8) \
1270 | (h8_get_eightbit (sd, ((X)+3) & 0xff) << 0)))
1272 #define GET_MEMORY_W(X) \
1273 ((X) < memory_size \
1274 ? ((h8_get_memory (sd, (X)+0) << 8) \
1275 | (h8_get_memory (sd, (X)+1) << 0)) \
1276 : ((h8_get_eightbit (sd, ((X)+0) & 0xff) << 8) \
1277 | (h8_get_eightbit (sd, ((X)+1) & 0xff) << 0)))
1280 #define GET_MEMORY_B(X) \
1281 ((X) < memory_size ? (h8_get_memory (sd, (X))) \
1282 : (h8_get_eightbit (sd, (X) & 0xff)))
1284 #define SET_MEMORY_L(X, Y) \
1285 { register unsigned char *_p; register int __y = (Y); \
1286 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1287 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1288 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1289 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1292 #define SET_MEMORY_W(X, Y) \
1293 { register unsigned char *_p; register int __y = (Y); \
1294 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : \
1295 h8_get_eightbit_buf (sd) + ((X) & 0xff)); \
1296 _p[0] = __y >> 8; _p[1] = __y; \
1299 #define SET_MEMORY_B(X, Y) \
1300 ((X) < memory_size ? (h8_set_memory (sd, (X), (Y))) \
1301 : (h8_set_eightbit (sd, (X) & 0xff, (Y))))
1303 /* Simulate a memory fetch.
1304 Return 0 for success, -1 for failure.
1308 fetch_1 (SIM_DESC sd, ea_type *arg, int *val, int twice)
1311 int abs = arg->literal;
1316 return -1; /* Paranoia. */
1320 /* Indexed register plus displacement mode:
1322 This new family of addressing modes are similar to OP_DISP
1323 (register plus displacement), with two differences:
1324 1) INDEXB uses only the least significant byte of the register,
1325 INDEXW uses only the least significant word, and
1326 INDEXL uses the entire register (just like OP_DISP).
1328 2) The displacement value in abs is multiplied by two
1329 for SW-sized operations, and by four for SL-size.
1331 This gives nine possible variations.
1334 case X (OP_INDEXB, SB):
1335 case X (OP_INDEXB, SW):
1336 case X (OP_INDEXB, SL):
1337 case X (OP_INDEXW, SB):
1338 case X (OP_INDEXW, SW):
1339 case X (OP_INDEXW, SL):
1340 case X (OP_INDEXL, SB):
1341 case X (OP_INDEXL, SW):
1342 case X (OP_INDEXL, SL):
1344 switch (OP_KIND (arg->type)) {
1345 case OP_INDEXB: t &= 0xff; break;
1346 case OP_INDEXW: t &= 0xffff; break;
1350 switch (OP_SIZE (arg->type)) {
1352 *val = GET_MEMORY_B ((t * 1 + abs) & h8_get_mask (sd));
1355 *val = GET_MEMORY_W ((t * 2 + abs) & h8_get_mask (sd));
1358 *val = GET_MEMORY_L ((t * 4 + abs) & h8_get_mask (sd));
1363 case X (OP_LOWREG, SB):
1364 *val = GET_L_REG (rn) & 0xff;
1366 case X (OP_LOWREG, SW):
1367 *val = GET_L_REG (rn) & 0xffff;
1370 case X (OP_REG, SB): /* Register direct, byte. */
1371 *val = GET_B_REG (rn);
1373 case X (OP_REG, SW): /* Register direct, word. */
1374 *val = GET_W_REG (rn);
1376 case X (OP_REG, SL): /* Register direct, long. */
1377 *val = GET_L_REG (rn);
1379 case X (OP_IMM, SB): /* Immediate, byte. */
1380 case X (OP_IMM, SW): /* Immediate, word. */
1381 case X (OP_IMM, SL): /* Immediate, long. */
1384 case X (OP_POSTINC, SB): /* Register indirect w/post-incr: byte. */
1386 r = GET_MEMORY_B (t & h8_get_mask (sd));
1392 case X (OP_POSTINC, SW): /* Register indirect w/post-incr: word. */
1394 r = GET_MEMORY_W (t & h8_get_mask (sd));
1400 case X (OP_POSTINC, SL): /* Register indirect w/post-incr: long. */
1402 r = GET_MEMORY_L (t & h8_get_mask (sd));
1409 case X (OP_POSTDEC, SB): /* Register indirect w/post-decr: byte. */
1411 r = GET_MEMORY_B (t & h8_get_mask (sd));
1417 case X (OP_POSTDEC, SW): /* Register indirect w/post-decr: word. */
1419 r = GET_MEMORY_W (t & h8_get_mask (sd));
1425 case X (OP_POSTDEC, SL): /* Register indirect w/post-decr: long. */
1427 r = GET_MEMORY_L (t & h8_get_mask (sd));
1434 case X (OP_PREDEC, SB): /* Register indirect w/pre-decr: byte. */
1435 t = GET_L_REG (rn) - 1;
1437 t &= h8_get_mask (sd);
1438 *val = GET_MEMORY_B (t);
1441 case X (OP_PREDEC, SW): /* Register indirect w/pre-decr: word. */
1442 t = GET_L_REG (rn) - 2;
1444 t &= h8_get_mask (sd);
1445 *val = GET_MEMORY_W (t);
1448 case X (OP_PREDEC, SL): /* Register indirect w/pre-decr: long. */
1449 t = GET_L_REG (rn) - 4;
1451 t &= h8_get_mask (sd);
1452 *val = GET_MEMORY_L (t);
1455 case X (OP_PREINC, SB): /* Register indirect w/pre-incr: byte. */
1456 t = GET_L_REG (rn) + 1;
1458 t &= h8_get_mask (sd);
1459 *val = GET_MEMORY_B (t);
1462 case X (OP_PREINC, SW): /* Register indirect w/pre-incr: long. */
1463 t = GET_L_REG (rn) + 2;
1465 t &= h8_get_mask (sd);
1466 *val = GET_MEMORY_W (t);
1469 case X (OP_PREINC, SL): /* Register indirect w/pre-incr: long. */
1470 t = GET_L_REG (rn) + 4;
1472 t &= h8_get_mask (sd);
1473 *val = GET_MEMORY_L (t);
1476 case X (OP_DISP, SB): /* Register indirect w/displacement: byte. */
1477 t = GET_L_REG (rn) + abs;
1478 t &= h8_get_mask (sd);
1479 *val = GET_MEMORY_B (t);
1482 case X (OP_DISP, SW): /* Register indirect w/displacement: word. */
1483 t = GET_L_REG (rn) + abs;
1484 t &= h8_get_mask (sd);
1485 *val = GET_MEMORY_W (t);
1488 case X (OP_DISP, SL): /* Register indirect w/displacement: long. */
1489 t = GET_L_REG (rn) + abs;
1490 t &= h8_get_mask (sd);
1491 *val =GET_MEMORY_L (t);
1494 case X (OP_MEM, SL): /* Absolute memory address, long. */
1495 t = GET_MEMORY_L (abs);
1496 t &= h8_get_mask (sd);
1500 case X (OP_MEM, SW): /* Absolute memory address, word. */
1501 t = GET_MEMORY_W (abs);
1502 t &= h8_get_mask (sd);
1506 case X (OP_PCREL, SB): /* PC relative (for jump, branch etc). */
1507 case X (OP_PCREL, SW):
1508 case X (OP_PCREL, SL):
1509 case X (OP_PCREL, SN):
1513 case X (OP_MEM, SB): /* Why isn't this implemented? */
1515 sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
1518 return 0; /* Success. */
1524 fetch (SIM_DESC sd, ea_type *arg, int *val)
1526 return fetch_1 (sd, arg, val, 0);
1529 /* Fetch which will be followed by a store to the same location.
1530 The difference being that we don't want to do a post-increment
1531 or post-decrement at this time: we'll do it when we store. */
1534 fetch2 (SIM_DESC sd, ea_type *arg, int *val)
1536 return fetch_1 (sd, arg, val, 1);
1539 /* Simulate a memory store.
1540 Return 0 for success, -1 for failure.
1544 store_1 (SIM_DESC sd, ea_type *arg, int n, int twice)
1547 int abs = arg->literal;
1552 /* Indexed register plus displacement mode:
1554 This new family of addressing modes are similar to OP_DISP
1555 (register plus displacement), with two differences:
1556 1) INDEXB uses only the least significant byte of the register,
1557 INDEXW uses only the least significant word, and
1558 INDEXL uses the entire register (just like OP_DISP).
1560 2) The displacement value in abs is multiplied by two
1561 for SW-sized operations, and by four for SL-size.
1563 This gives nine possible variations.
1566 case X (OP_INDEXB, SB):
1567 case X (OP_INDEXB, SW):
1568 case X (OP_INDEXB, SL):
1569 case X (OP_INDEXW, SB):
1570 case X (OP_INDEXW, SW):
1571 case X (OP_INDEXW, SL):
1572 case X (OP_INDEXL, SB):
1573 case X (OP_INDEXL, SW):
1574 case X (OP_INDEXL, SL):
1576 switch (OP_KIND (arg->type)) {
1577 case OP_INDEXB: t &= 0xff; break;
1578 case OP_INDEXW: t &= 0xffff; break;
1582 switch (OP_SIZE (arg->type)) {
1584 SET_MEMORY_B ((t * 1 + abs) & h8_get_mask (sd), n);
1587 SET_MEMORY_W ((t * 2 + abs) & h8_get_mask (sd), n);
1590 SET_MEMORY_L ((t * 4 + abs) & h8_get_mask (sd), n);
1595 case X (OP_REG, SB): /* Register direct, byte. */
1598 case X (OP_REG, SW): /* Register direct, word. */
1601 case X (OP_REG, SL): /* Register direct, long. */
1605 case X (OP_PREDEC, SB): /* Register indirect w/pre-decr, byte. */
1610 t &= h8_get_mask (sd);
1611 SET_MEMORY_B (t, n);
1614 case X (OP_PREDEC, SW): /* Register indirect w/pre-decr, word. */
1619 t &= h8_get_mask (sd);
1620 SET_MEMORY_W (t, n);
1623 case X (OP_PREDEC, SL): /* Register indirect w/pre-decr, long. */
1628 t &= h8_get_mask (sd);
1629 SET_MEMORY_L (t, n);
1632 case X (OP_PREINC, SB): /* Register indirect w/pre-incr, byte. */
1637 t &= h8_get_mask (sd);
1638 SET_MEMORY_B (t, n);
1641 case X (OP_PREINC, SW): /* Register indirect w/pre-incr, word. */
1646 t &= h8_get_mask (sd);
1647 SET_MEMORY_W (t, n);
1650 case X (OP_PREINC, SL): /* Register indirect w/pre-incr, long. */
1655 t &= h8_get_mask (sd);
1656 SET_MEMORY_L (t, n);
1659 case X (OP_POSTDEC, SB): /* Register indirect w/post-decr, byte. */
1661 SET_L_REG (rn, t - 1);
1662 t &= h8_get_mask (sd);
1663 SET_MEMORY_B (t, n);
1666 case X (OP_POSTDEC, SW): /* Register indirect w/post-decr, word. */
1668 SET_L_REG (rn, t - 2);
1669 t &= h8_get_mask (sd);
1670 SET_MEMORY_W (t, n);
1673 case X (OP_POSTDEC, SL): /* Register indirect w/post-decr, long. */
1675 SET_L_REG (rn, t - 4);
1676 t &= h8_get_mask (sd);
1677 SET_MEMORY_L (t, n);
1680 case X (OP_POSTINC, SB): /* Register indirect w/post-incr, byte. */
1682 SET_L_REG (rn, t + 1);
1683 t &= h8_get_mask (sd);
1684 SET_MEMORY_B (t, n);
1687 case X (OP_POSTINC, SW): /* Register indirect w/post-incr, word. */
1689 SET_L_REG (rn, t + 2);
1690 t &= h8_get_mask (sd);
1691 SET_MEMORY_W (t, n);
1694 case X (OP_POSTINC, SL): /* Register indirect w/post-incr, long. */
1696 SET_L_REG (rn, t + 4);
1697 t &= h8_get_mask (sd);
1698 SET_MEMORY_L (t, n);
1701 case X (OP_DISP, SB): /* Register indirect w/displacement, byte. */
1702 t = GET_L_REG (rn) + abs;
1703 t &= h8_get_mask (sd);
1704 SET_MEMORY_B (t, n);
1707 case X (OP_DISP, SW): /* Register indirect w/displacement, word. */
1708 t = GET_L_REG (rn) + abs;
1709 t &= h8_get_mask (sd);
1710 SET_MEMORY_W (t, n);
1713 case X (OP_DISP, SL): /* Register indirect w/displacement, long. */
1714 t = GET_L_REG (rn) + abs;
1715 t &= h8_get_mask (sd);
1716 SET_MEMORY_L (t, n);
1720 case X (OP_MEM, SB): /* Why isn't this implemented? */
1721 case X (OP_MEM, SW): /* Why isn't this implemented? */
1722 case X (OP_MEM, SL): /* Why isn't this implemented? */
1724 sim_engine_set_run_state (sd, sim_stopped, SIGSEGV);
1733 store (SIM_DESC sd, ea_type *arg, int n)
1735 return store_1 (sd, arg, n, 0);
1738 /* Store which follows a fetch from the same location.
1739 The difference being that we don't want to do a pre-increment
1740 or pre-decrement at this time: it was already done when we fetched. */
1743 store2 (SIM_DESC sd, ea_type *arg, int n)
1745 return store_1 (sd, arg, n, 1);
1748 /* Flag to be set whenever a new SIM_DESC object is created. */
1749 static int init_pointers_needed = 1;
1752 init_pointers (SIM_DESC sd)
1754 if (init_pointers_needed)
1758 if (h8300smode && !h8300_normal_mode)
1759 memory_size = H8300S_MSIZE;
1760 else if (h8300hmode && !h8300_normal_mode)
1761 memory_size = H8300H_MSIZE;
1763 memory_size = H8300_MSIZE;
1764 /* `msize' must be a power of two. */
1765 if ((memory_size & (memory_size - 1)) != 0)
1769 "init_pointers: bad memory size %d, defaulting to %d.\n",
1770 memory_size, memory_size = H8300S_MSIZE);
1773 if (h8_get_memory_buf (sd))
1774 free (h8_get_memory_buf (sd));
1775 if (h8_get_cache_idx_buf (sd))
1776 free (h8_get_cache_idx_buf (sd));
1777 if (h8_get_eightbit_buf (sd))
1778 free (h8_get_eightbit_buf (sd));
1780 h8_set_memory_buf (sd, (unsigned char *)
1781 calloc (sizeof (char), memory_size));
1782 h8_set_cache_idx_buf (sd, (unsigned short *)
1783 calloc (sizeof (short), memory_size));
1784 sd->memory_size = memory_size;
1785 h8_set_eightbit_buf (sd, (unsigned char *) calloc (sizeof (char), 256));
1787 h8_set_mask (sd, memory_size - 1);
1789 memset (h8_get_reg_buf (sd), 0, sizeof (((STATE_CPU (sd, 0))->regs)));
1791 for (i = 0; i < 8; i++)
1793 /* FIXME: rewrite using local buffer. */
1794 unsigned char *p = (unsigned char *) (h8_get_reg_buf (sd) + i);
1795 unsigned char *e = (unsigned char *) (h8_get_reg_buf (sd) + i + 1);
1796 unsigned short *q = (unsigned short *) (h8_get_reg_buf (sd) + i);
1797 unsigned short *u = (unsigned short *) (h8_get_reg_buf (sd) + i + 1);
1798 h8_set_reg (sd, i, 0x00112233);
1813 wreg[i] = wreg[i + 8] = 0;
1827 if (wreg[i] == 0 || wreg[i + 8] == 0)
1828 sim_io_printf (sd, "init_pointers: internal error.\n");
1830 h8_set_reg (sd, i, 0);
1831 lreg[i] = h8_get_reg_buf (sd) + i;
1834 /* Note: sim uses pseudo-register ZERO as a zero register. */
1835 lreg[ZERO_REGNUM] = h8_get_reg_buf (sd) + ZERO_REGNUM;
1836 init_pointers_needed = 0;
1838 /* Initialize the seg registers. */
1840 set_simcache_size (sd, CSIZE);
1844 #define OBITOP(name, f, s, op) \
1845 case O (name, SB): \
1850 if (fetch (sd, &code->dst, &ea)) \
1852 if (fetch (sd, &code->src, &tmp)) \
1854 m = 1 << (tmp & 7); \
1857 if (store (sd, &code->dst,ea)) \
1863 sim_resume (SIM_DESC sd, int step, int siggnal)
1868 int tick_start = get_now ();
1876 int c, nz, v, n, u, h, ui, intMaskBit;
1879 enum sim_stop reason;
1881 host_callback *sim_callback = STATE_CALLBACK (sd);
1887 sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
1891 sim_engine_set_run_state (sd, sim_running, 0);
1894 pc = h8_get_pc (sd);
1896 /* The PC should never be odd. */
1899 sim_engine_set_run_state (sd, sim_stopped, SIGBUS);
1903 /* Get Status Register (flags). */
1906 if (h8300smode) /* Get exr. */
1908 trace = (h8_get_exr (sd) >> 7) & 1;
1909 intMask = h8_get_exr (sd) & 7;
1912 oldmask = h8_get_mask (sd);
1913 if (!h8300hmode || h8300_normal_mode)
1914 h8_set_mask (sd, 0xffff);
1917 unsigned short cidx;
1921 cidx = h8_get_cache_idx (sd, pc);
1922 if (cidx == (unsigned short) -1 ||
1923 cidx >= sd->sim_cache_size)
1926 code = sd->sim_cache + cidx;
1931 printf ("%x %d %s\n", pc, code->opcode,
1932 code->op ? code->op->name : "**");
1934 h8_increment_stats (sd, code->opcode);
1939 cycles += code->cycles;
1943 switch (code->opcode)
1947 * This opcode is a fake for when we get to an
1948 * instruction which hasnt been compiled
1954 case O (O_MOVAB, SL):
1955 case O (O_MOVAW, SL):
1956 case O (O_MOVAL, SL):
1957 /* 1) Evaluate 2nd argument (dst).
1958 2) Mask / zero extend according to whether 1st argument (src)
1959 is INDEXB, INDEXW, or INDEXL.
1960 3) Left-shift the result by 0, 1 or 2, according to size of mova
1961 (mova/b, mova/w, mova/l).
1962 4) Add literal value of 1st argument (src).
1963 5) Store result in 3rd argument (op3).
1966 /* Alas, since this is the only instruction with 3 arguments,
1967 decode doesn't handle them very well. Some fix-up is required.
1969 a) The size of dst is determined by whether src is
1970 INDEXB or INDEXW. */
1972 if (OP_KIND (code->src.type) == OP_INDEXB)
1973 code->dst.type = X (OP_KIND (code->dst.type), SB);
1974 else if (OP_KIND (code->src.type) == OP_INDEXW)
1975 code->dst.type = X (OP_KIND (code->dst.type), SW);
1977 /* b) If op3 == null, then this is the short form of the insn.
1978 Dst is the dispreg of src, and op3 is the 32-bit form
1979 of the same register.
1982 if (code->op3.type == 0)
1984 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1985 We get to compose dst and op3 as follows:
1987 op3 is a 32-bit register, ID == src.reg.
1988 dst is the same register, but 8 or 16 bits
1989 depending on whether src is INDEXB or INDEXW.
1992 code->op3.type = X (OP_REG, SL);
1993 code->op3.reg = code->src.reg;
1994 code->op3.literal = 0;
1996 if (OP_KIND (code->src.type) == OP_INDEXB)
1998 code->dst.type = X (OP_REG, SB);
1999 code->dst.reg = code->op3.reg + 8;
2002 code->dst.type = X (OP_REG, SW);
2005 if (fetch (sd, &code->dst, &ea))
2008 switch (OP_KIND (code->src.type)) {
2009 case OP_INDEXB: ea = ea & 0xff; break;
2010 case OP_INDEXW: ea = ea & 0xffff; break;
2011 case OP_INDEXL: break;
2012 default: goto illegal;
2015 switch (code->opcode) {
2016 case O (O_MOVAB, SL): break;
2017 case O (O_MOVAW, SL): ea = ea << 1; break;
2018 case O (O_MOVAL, SL): ea = ea << 2; break;
2019 default: goto illegal;
2022 ea = ea + code->src.literal;
2024 if (store (sd, &code->op3, ea))
2029 case O (O_SUBX, SB): /* subx, extended sub */
2030 if (fetch2 (sd, &code->dst, &rd))
2032 if (fetch (sd, &code->src, &ea))
2038 case O (O_SUBX, SW): /* subx, extended sub */
2039 if (fetch2 (sd, &code->dst, &rd))
2041 if (fetch (sd, &code->src, &ea))
2047 case O (O_SUBX, SL): /* subx, extended sub */
2048 if (fetch2 (sd, &code->dst, &rd))
2050 if (fetch (sd, &code->src, &ea))
2056 case O (O_ADDX, SB): /* addx, extended add */
2057 if (fetch2 (sd, &code->dst, &rd))
2059 if (fetch (sd, &code->src, &ea))
2065 case O (O_ADDX, SW): /* addx, extended add */
2066 if (fetch2 (sd, &code->dst, &rd))
2068 if (fetch (sd, &code->src, &ea))
2074 case O (O_ADDX, SL): /* addx, extended add */
2075 if (fetch2 (sd, &code->dst, &rd))
2077 if (fetch (sd, &code->src, &ea))
2083 case O (O_SUB, SB): /* sub.b */
2084 /* Fetch rd and ea. */
2085 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2091 case O (O_SUB, SW): /* sub.w */
2092 /* Fetch rd and ea. */
2093 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2099 case O (O_SUB, SL): /* sub.l */
2100 /* Fetch rd and ea. */
2101 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2107 case O (O_NEG, SB): /* neg.b */
2109 if (fetch2 (sd, &code->src, &ea))
2116 case O (O_NEG, SW): /* neg.w */
2118 if (fetch2 (sd, &code->src, &ea))
2125 case O (O_NEG, SL): /* neg.l */
2127 if (fetch2 (sd, &code->src, &ea))
2134 case O (O_ADD, SB): /* add.b */
2135 if (fetch2 (sd, &code->dst, &rd))
2137 if (fetch (sd, &code->src, &ea))
2142 case O (O_ADD, SW): /* add.w */
2143 if (fetch2 (sd, &code->dst, &rd))
2145 if (fetch (sd, &code->src, &ea))
2150 case O (O_ADD, SL): /* add.l */
2151 if (fetch2 (sd, &code->dst, &rd))
2153 if (fetch (sd, &code->src, &ea))
2158 case O (O_AND, SB): /* and.b */
2159 /* Fetch rd and ea. */
2160 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2165 case O (O_AND, SW): /* and.w */
2166 /* Fetch rd and ea. */
2167 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2172 case O (O_AND, SL): /* and.l */
2173 /* Fetch rd and ea. */
2174 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2179 case O (O_OR, SB): /* or.b */
2180 /* Fetch rd and ea. */
2181 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2186 case O (O_OR, SW): /* or.w */
2187 /* Fetch rd and ea. */
2188 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2193 case O (O_OR, SL): /* or.l */
2194 /* Fetch rd and ea. */
2195 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2200 case O (O_XOR, SB): /* xor.b */
2201 /* Fetch rd and ea. */
2202 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2207 case O (O_XOR, SW): /* xor.w */
2208 /* Fetch rd and ea. */
2209 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2214 case O (O_XOR, SL): /* xor.l */
2215 /* Fetch rd and ea. */
2216 if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd))
2222 if (fetch (sd, &code->src, &res))
2224 if (store (sd, &code->dst, res))
2226 goto just_flags_log8;
2228 if (fetch (sd, &code->src, &res))
2230 if (store (sd, &code->dst, res))
2232 goto just_flags_log16;
2234 if (fetch (sd, &code->src, &res))
2236 if (store (sd, &code->dst, res))
2238 goto just_flags_log32;
2240 case O (O_MOVMD, SB): /* movmd.b */
2247 rd = GET_MEMORY_B (GET_L_REG (5));
2248 SET_MEMORY_B (GET_L_REG (6), rd);
2249 SET_L_REG (5, GET_L_REG (5) + 1);
2250 SET_L_REG (6, GET_L_REG (6) + 1);
2255 case O (O_MOVMD, SW): /* movmd.w */
2262 rd = GET_MEMORY_W (GET_L_REG (5));
2263 SET_MEMORY_W (GET_L_REG (6), rd);
2264 SET_L_REG (5, GET_L_REG (5) + 2);
2265 SET_L_REG (6, GET_L_REG (6) + 2);
2270 case O (O_MOVMD, SL): /* movmd.l */
2277 rd = GET_MEMORY_L (GET_L_REG (5));
2278 SET_MEMORY_L (GET_L_REG (6), rd);
2279 SET_L_REG (5, GET_L_REG (5) + 4);
2280 SET_L_REG (6, GET_L_REG (6) + 4);
2285 case O (O_MOVSD, SB): /* movsd.b */
2286 /* This instruction implements strncpy, with a conditional branch.
2287 r4 contains n, r5 contains src, and r6 contains dst.
2288 The 16-bit displacement operand is added to the pc
2289 if and only if the end of string is reached before
2290 n bytes are transferred. */
2292 ea = GET_L_REG (4) & 0xffff;
2298 rd = GET_MEMORY_B (GET_L_REG (5));
2299 SET_MEMORY_B (GET_L_REG (6), rd);
2300 SET_L_REG (5, GET_L_REG (5) + 1);
2301 SET_L_REG (6, GET_L_REG (6) + 1);
2308 case O (O_EEPMOV, SB): /* eepmov.b */
2309 case O (O_EEPMOV, SW): /* eepmov.w */
2310 if (h8300hmode || h8300smode)
2312 register unsigned char *_src, *_dst;
2313 unsigned int count = ((code->opcode == O (O_EEPMOV, SW))
2314 ? h8_get_reg (sd, R4_REGNUM) & 0xffff
2315 : h8_get_reg (sd, R4_REGNUM) & 0xff);
2317 _src = (h8_get_reg (sd, R5_REGNUM) < memory_size
2318 ? h8_get_memory_buf (sd) + h8_get_reg (sd, R5_REGNUM)
2319 : h8_get_eightbit_buf (sd) +
2320 (h8_get_reg (sd, R5_REGNUM) & 0xff));
2321 if ((_src + count) >= (h8_get_memory_buf (sd) + memory_size))
2323 if ((_src + count) >= (h8_get_eightbit_buf (sd) + 0x100))
2326 _dst = (h8_get_reg (sd, R6_REGNUM) < memory_size
2327 ? h8_get_memory_buf (sd) + h8_get_reg (sd, R6_REGNUM)
2328 : h8_get_eightbit_buf (sd) +
2329 (h8_get_reg (sd, R6_REGNUM) & 0xff));
2331 if ((_dst + count) >= (h8_get_memory_buf (sd) + memory_size))
2333 if ((_dst + count) >= (h8_get_eightbit_buf (sd) + 0x100))
2336 memcpy (_dst, _src, count);
2338 h8_set_reg (sd, R5_REGNUM, h8_get_reg (sd, R5_REGNUM) + count);
2339 h8_set_reg (sd, R6_REGNUM, h8_get_reg (sd, R6_REGNUM) + count);
2340 h8_set_reg (sd, R4_REGNUM, h8_get_reg (sd, R4_REGNUM) &
2341 ((code->opcode == O (O_EEPMOV, SW))
2342 ? (~0xffff) : (~0xff)));
2343 cycles += 2 * count;
2348 case O (O_ADDS, SL): /* adds (.l) */
2350 * This insn only uses register operands, but still
2351 * it would be cleaner to use fetch and store... */
2352 SET_L_REG (code->dst.reg,
2353 GET_L_REG (code->dst.reg)
2354 + code->src.literal);
2358 case O (O_SUBS, SL): /* subs (.l) */
2360 * This insn only uses register operands, but still
2361 * it would be cleaner to use fetch and store... */
2362 SET_L_REG (code->dst.reg,
2363 GET_L_REG (code->dst.reg)
2364 - code->src.literal);
2367 case O (O_CMP, SB): /* cmp.b */
2368 if (fetch (sd, &code->dst, &rd))
2370 if (fetch (sd, &code->src, &ea))
2374 goto just_flags_alu8;
2376 case O (O_CMP, SW): /* cmp.w */
2377 if (fetch (sd, &code->dst, &rd))
2379 if (fetch (sd, &code->src, &ea))
2383 goto just_flags_alu16;
2385 case O (O_CMP, SL): /* cmp.l */
2386 if (fetch (sd, &code->dst, &rd))
2388 if (fetch (sd, &code->src, &ea))
2392 goto just_flags_alu32;
2394 case O (O_DEC, SB): /* dec.b */
2396 * This insn only uses register operands, but still
2397 * it would be cleaner to use fetch and store... */
2398 rd = GET_B_REG (code->src.reg);
2401 SET_B_REG (code->src.reg, res);
2402 goto just_flags_inc8;
2404 case O (O_DEC, SW): /* dec.w */
2406 * This insn only uses register operands, but still
2407 * it would be cleaner to use fetch and store... */
2408 rd = GET_W_REG (code->dst.reg);
2409 ea = -code->src.literal;
2411 SET_W_REG (code->dst.reg, res);
2412 goto just_flags_inc16;
2414 case O (O_DEC, SL): /* dec.l */
2416 * This insn only uses register operands, but still
2417 * it would be cleaner to use fetch and store... */
2418 rd = GET_L_REG (code->dst.reg);
2419 ea = -code->src.literal;
2421 SET_L_REG (code->dst.reg, res);
2422 goto just_flags_inc32;
2424 case O (O_INC, SB): /* inc.b */
2426 * This insn only uses register operands, but still
2427 * it would be cleaner to use fetch and store... */
2428 rd = GET_B_REG (code->src.reg);
2431 SET_B_REG (code->src.reg, res);
2432 goto just_flags_inc8;
2434 case O (O_INC, SW): /* inc.w */
2436 * This insn only uses register operands, but still
2437 * it would be cleaner to use fetch and store... */
2438 rd = GET_W_REG (code->dst.reg);
2439 ea = code->src.literal;
2441 SET_W_REG (code->dst.reg, res);
2442 goto just_flags_inc16;
2444 case O (O_INC, SL): /* inc.l */
2446 * This insn only uses register operands, but still
2447 * it would be cleaner to use fetch and store... */
2448 rd = GET_L_REG (code->dst.reg);
2449 ea = code->src.literal;
2451 SET_L_REG (code->dst.reg, res);
2452 goto just_flags_inc32;
2454 case O (O_LDC, SB): /* ldc.b */
2455 if (fetch (sd, &code->src, &res))
2459 case O (O_LDC, SW): /* ldc.w */
2460 if (fetch (sd, &code->src, &res))
2463 /* Word operand, value from MSB, must be shifted. */
2467 case O (O_LDC, SL): /* ldc.l */
2468 if (fetch (sd, &code->src, &res))
2470 switch (code->dst.type) {
2471 case X (OP_SBR, SL):
2472 h8_set_sbr (sd, res);
2474 case X (OP_VBR, SL):
2475 h8_set_vbr (sd, res);
2482 case O (O_STC, SW): /* stc.w */
2483 case O (O_STC, SB): /* stc.b */
2484 if (code->src.type == X (OP_CCR, SB))
2487 res = h8_get_ccr (sd);
2489 else if (code->src.type == X (OP_EXR, SB) && h8300smode)
2492 h8_set_exr (sd, (trace << 7) | intMask);
2493 res = h8_get_exr (sd);
2498 /* Word operand, value to MSB, must be shifted. */
2499 if (code->opcode == X (O_STC, SW))
2501 if (store (sd, &code->dst, res))
2504 case O (O_STC, SL): /* stc.l */
2505 switch (code->src.type) {
2506 case X (OP_SBR, SL):
2507 res = h8_get_sbr (sd);
2509 case X (OP_VBR, SL):
2510 res = h8_get_vbr (sd);
2515 if (store (sd, &code->dst, res))
2519 case O (O_ANDC, SB): /* andc.b */
2520 if (code->dst.type == X (OP_CCR, SB))
2523 rd = h8_get_ccr (sd);
2525 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2528 h8_set_exr (sd, (trace << 7) | intMask);
2529 rd = h8_get_exr (sd);
2533 ea = code->src.literal;
2537 case O (O_ORC, SB): /* orc.b */
2538 if (code->dst.type == X (OP_CCR, SB))
2541 rd = h8_get_ccr (sd);
2543 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2546 h8_set_exr (sd, (trace << 7) | intMask);
2547 rd = h8_get_exr (sd);
2551 ea = code->src.literal;
2555 case O (O_XORC, SB): /* xorc.b */
2556 if (code->dst.type == X (OP_CCR, SB))
2559 rd = h8_get_ccr (sd);
2561 else if (code->dst.type == X (OP_EXR, SB) && h8300smode)
2564 h8_set_exr (sd, (trace << 7) | intMask);
2565 rd = h8_get_exr (sd);
2569 ea = code->src.literal;
2573 case O (O_BRAS, SB): /* bra/s */
2574 /* This is basically an ordinary branch, with a delay slot. */
2575 if (fetch (sd, &code->src, &res))
2583 /* Execution continues at next instruction, but
2584 delayed_branch is set up for next cycle. */
2585 h8_set_delayed_branch (sd, code->next_pc + res);
2589 case O (O_BRAB, SB): /* bra rd.b */
2590 case O (O_BRAW, SW): /* bra rd.w */
2591 case O (O_BRAL, SL): /* bra erd.l */
2592 if (fetch (sd, &code->src, &rd))
2594 switch (OP_SIZE (code->opcode)) {
2595 case SB: rd &= 0xff; break;
2596 case SW: rd &= 0xffff; break;
2597 case SL: rd &= 0xffffffff; break;
2599 pc = code->next_pc + rd;
2602 case O (O_BRABC, SB): /* bra/bc, branch if bit clear */
2603 case O (O_BRABS, SB): /* bra/bs, branch if bit set */
2604 case O (O_BSRBC, SB): /* bsr/bc, call if bit clear */
2605 case O (O_BSRBS, SB): /* bsr/bs, call if bit set */
2606 if (fetch (sd, &code->dst, &rd) ||
2607 fetch (sd, &code->src, &bit))
2610 if (code->opcode == O (O_BRABC, SB) || /* branch if clear */
2611 code->opcode == O (O_BSRBC, SB)) /* call if clear */
2613 if ((rd & (1 << bit))) /* no branch */
2616 else /* branch/call if set */
2618 if (!(rd & (1 << bit))) /* no branch */
2622 if (fetch (sd, &code->op3, &res)) /* branch */
2624 pc = code->next_pc + res;
2626 if (code->opcode == O (O_BRABC, SB) ||
2627 code->opcode == O (O_BRABS, SB)) /* branch */
2635 case O (O_BRA, SB): /* bra, branch always */
2640 case O (O_BRN, SB): /* brn, ;-/ branch never? */
2645 case O (O_BHI, SB): /* bhi */
2651 case O (O_BLS, SB): /* bls */
2656 case O (O_BCS, SB): /* bcs, branch if carry set */
2661 case O (O_BCC, SB): /* bcc, branch if carry clear */
2666 case O (O_BEQ, SB): /* beq, branch if zero set */
2670 case O (O_BGT, SB): /* bgt */
2671 if (((Z || (N ^ V)) == 0))
2675 case O (O_BLE, SB): /* ble */
2676 if (((Z || (N ^ V)) == 1))
2680 case O (O_BGE, SB): /* bge */
2684 case O (O_BLT, SB): /* blt */
2688 case O (O_BMI, SB): /* bmi */
2692 case O (O_BNE, SB): /* bne, branch if zero clear */
2697 case O (O_BPL, SB): /* bpl */
2701 case O (O_BVC, SB): /* bvc */
2705 case O (O_BVS, SB): /* bvs */
2710 /* Trap for Command Line setup. */
2711 case O (O_SYS_CMDLINE, SB):
2713 int i = 0; /* Loop counter. */
2714 int j = 0; /* Loop counter. */
2715 int ind_arg_len = 0; /* Length of each argument. */
2716 int no_of_args = 0; /* The no. or cmdline args. */
2717 int current_location = 0; /* Location of string. */
2718 int old_sp = 0; /* The Initial Stack Pointer. */
2719 int no_of_slots = 0; /* No. of slots required on the stack
2720 for storing cmdline args. */
2721 int sp_move = 0; /* No. of locations by which the stack needs
2723 int new_sp = 0; /* The final stack pointer location passed
2725 int *argv_ptrs; /* Pointers of argv strings to be stored. */
2726 int argv_ptrs_location = 0; /* Location of pointers to cmdline
2727 args on the stack. */
2728 int char_ptr_size = 0; /* Size of a character pointer on
2730 int addr_cmdline = 0; /* Memory location where cmdline has
2732 int size_cmdline = 0; /* Size of cmdline. */
2734 /* Set the address of 256 free locations where command line is
2736 addr_cmdline = cmdline_location();
2737 h8_set_reg (sd, 0, addr_cmdline);
2739 /* Counting the no. of commandline arguments. */
2740 for (i = 0; h8_get_cmdline_arg (sd, i) != NULL; i++)
2743 /* No. of arguments in the command line. */
2746 /* Current location is just a temporary variable,which we are
2747 setting to the point to the start of our commandline string. */
2748 current_location = addr_cmdline;
2750 /* Allocating space for storing pointers of the command line
2752 argv_ptrs = (int *) malloc (sizeof (int) * no_of_args);
2754 /* Setting char_ptr_size to the sizeof (char *) on the different
2756 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
2765 for (i = 0; i < no_of_args; i++)
2769 /* The size of the commandline argument. */
2770 ind_arg_len = strlen (h8_get_cmdline_arg (sd, i)) + 1;
2772 /* The total size of the command line string. */
2773 size_cmdline += ind_arg_len;
2775 /* As we have only 256 bytes, we need to provide a graceful
2776 exit. Anyways, a program using command line arguments
2777 where we cannot store all the command line arguments
2778 given may behave unpredictably. */
2779 if (size_cmdline >= 256)
2781 h8_set_reg (sd, 0, 0);
2786 /* current_location points to the memory where the next
2787 commandline argument is stored. */
2788 argv_ptrs[i] = current_location;
2789 for (j = 0; j < ind_arg_len; j++)
2791 SET_MEMORY_B ((current_location +
2792 (sizeof (char) * j)),
2793 *(h8_get_cmdline_arg (sd, i) +
2794 sizeof (char) * j));
2797 /* Setting current_location to the starting of next
2799 current_location += ind_arg_len;
2803 /* This is the original position of the stack pointer. */
2804 old_sp = h8_get_reg (sd, SP_REGNUM);
2806 /* We need space from the stack to store the pointers to argvs. */
2807 /* As we will infringe on the stack, we need to shift the stack
2808 pointer so that the data is not overwritten. We calculate how
2809 much space is required. */
2810 sp_move = (no_of_args) * (char_ptr_size);
2812 /* The final position of stack pointer, we have thus taken some
2813 space from the stack. */
2814 new_sp = old_sp - sp_move;
2816 /* Temporary variable holding value where the argv pointers need
2818 argv_ptrs_location = new_sp;
2820 /* The argv pointers are stored at sequential locations. As per
2822 for (i = 0; i < no_of_args; i++)
2824 /* Saving the argv pointer. */
2825 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
2827 SET_MEMORY_L (argv_ptrs_location, argv_ptrs[i]);
2831 SET_MEMORY_W (argv_ptrs_location, argv_ptrs[i]);
2834 /* The next location where the pointer to the next argv
2835 string has to be stored. */
2836 argv_ptrs_location += char_ptr_size;
2839 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2841 if ((h8300hmode || h8300smode) && !h8300_normal_mode)
2843 SET_MEMORY_L (old_sp, 0x0);
2847 SET_MEMORY_W (old_sp, 0x0);
2850 /* Freeing allocated memory. */
2852 for (i = 0; i <= no_of_args; i++)
2854 free (h8_get_cmdline_arg (sd, i));
2856 free (h8_get_command_line (sd));
2858 /* The no. of argv arguments are returned in Reg 0. */
2859 h8_set_reg (sd, 0, no_of_args);
2860 /* The Pointer to argv in Register 1. */
2861 h8_set_reg (sd, 1, new_sp);
2862 /* Setting the stack pointer to the new value. */
2863 h8_set_reg (sd, SP_REGNUM, new_sp);
2867 /* System call processing starts. */
2868 case O (O_SYS_OPEN, SB):
2870 int len = 0; /* Length of filename. */
2871 char *filename; /* Filename would go here. */
2872 char temp_char; /* Temporary character */
2873 int mode = 0; /* Mode bits for the file. */
2874 int open_return; /* Return value of open, file descriptor. */
2875 int i; /* Loop counter */
2876 int filename_ptr; /* Pointer to filename in cpu memory. */
2878 /* Setting filename_ptr to first argument of open, */
2879 /* and trying to get mode. */
2880 if ((h8300sxmode || h8300hmode || h8300smode) && !h8300_normal_mode)
2882 filename_ptr = GET_L_REG (0);
2883 mode = GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM) + 4);
2887 filename_ptr = GET_W_REG (0);
2888 mode = GET_MEMORY_W (h8_get_reg (sd, SP_REGNUM) + 2);
2891 /* Trying to find the length of the filename. */
2892 temp_char = GET_MEMORY_B (h8_get_reg (sd, 0));
2895 while (temp_char != '\0')
2897 temp_char = GET_MEMORY_B (filename_ptr + len);
2901 /* Allocating space for the filename. */
2902 filename = (char *) malloc (sizeof (char) * len);
2904 /* String copying the filename from memory. */
2905 for (i = 0; i < len; i++)
2907 temp_char = GET_MEMORY_B (filename_ptr + i);
2908 filename[i] = temp_char;
2911 /* Callback to open and return the file descriptor. */
2912 open_return = sim_callback->open (sim_callback, filename, mode);
2914 /* Return value in register 0. */
2915 h8_set_reg (sd, 0, open_return);
2917 /* Freeing memory used for filename. */
2922 case O (O_SYS_READ, SB):
2924 char *char_ptr; /* Where characters read would be stored. */
2925 int fd; /* File descriptor */
2926 int buf_size; /* BUF_SIZE parameter in read. */
2927 int i = 0; /* Temporary Loop counter */
2928 int read_return = 0; /* Return value from callback to
2931 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2932 buf_size = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
2934 char_ptr = (char *) malloc (sizeof (char) * buf_size);
2936 /* Callback to read and return the no. of characters read. */
2938 sim_callback->read (sim_callback, fd, char_ptr, buf_size);
2940 /* The characters read are stored in cpu memory. */
2941 for (i = 0; i < buf_size; i++)
2943 SET_MEMORY_B ((h8_get_reg (sd, 1) + (sizeof (char) * i)),
2944 *(char_ptr + (sizeof (char) * i)));
2947 /* Return value in Register 0. */
2948 h8_set_reg (sd, 0, read_return);
2950 /* Freeing memory used as buffer. */
2955 case O (O_SYS_WRITE, SB):
2957 int fd; /* File descriptor */
2958 char temp_char; /* Temporary character */
2959 int len; /* Length of write, Parameter II to write. */
2960 int char_ptr; /* Character Pointer, Parameter I of write. */
2961 char *ptr; /* Where characters to be written are stored.
2963 int write_return; /* Return value from callback to write. */
2964 int i = 0; /* Loop counter */
2966 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2967 char_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
2968 len = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
2970 /* Allocating space for the characters to be written. */
2971 ptr = (char *) malloc (sizeof (char) * len);
2973 /* Fetching the characters from cpu memory. */
2974 for (i = 0; i < len; i++)
2976 temp_char = GET_MEMORY_B (char_ptr + i);
2980 /* Callback write and return the no. of characters written. */
2981 write_return = sim_callback->write (sim_callback, fd, ptr, len);
2983 /* Return value in Register 0. */
2984 h8_set_reg (sd, 0, write_return);
2986 /* Freeing memory used as buffer. */
2991 case O (O_SYS_LSEEK, SB):
2993 int fd; /* File descriptor */
2994 int offset; /* Offset */
2995 int origin; /* Origin */
2996 int lseek_return; /* Return value from callback to lseek. */
2998 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
2999 offset = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
3000 origin = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (2) : GET_W_REG (2);
3002 /* Callback lseek and return offset. */
3004 sim_callback->lseek (sim_callback, fd, offset, origin);
3006 /* Return value in register 0. */
3007 h8_set_reg (sd, 0, lseek_return);
3011 case O (O_SYS_CLOSE, SB):
3013 int fd; /* File descriptor */
3014 int close_return; /* Return value from callback to close. */
3016 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
3018 /* Callback close and return. */
3019 close_return = sim_callback->close (sim_callback, fd);
3021 /* Return value in register 0. */
3022 h8_set_reg (sd, 0, close_return);
3026 case O (O_SYS_FSTAT, SB):
3028 int fd; /* File descriptor */
3029 struct stat stat_rec; /* Stat record */
3030 int fstat_return; /* Return value from callback to stat. */
3031 int stat_ptr; /* Pointer to stat record. */
3032 char *temp_stat_ptr; /* Temporary stat_rec pointer. */
3034 fd = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
3036 /* Setting stat_ptr to second argument of stat. */
3037 stat_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
3039 /* Callback stat and return. */
3040 fstat_return = sim_callback->to_fstat (sim_callback, fd,
3043 /* Have stat_ptr point to starting of stat_rec. */
3044 temp_stat_ptr = (char *) (&stat_rec);
3046 /* Setting up the stat structure returned. */
3047 SET_MEMORY_W (stat_ptr, stat_rec.st_dev);
3049 SET_MEMORY_W (stat_ptr, stat_rec.st_ino);
3051 SET_MEMORY_L (stat_ptr, stat_rec.st_mode);
3053 SET_MEMORY_W (stat_ptr, stat_rec.st_nlink);
3055 SET_MEMORY_W (stat_ptr, stat_rec.st_uid);
3057 SET_MEMORY_W (stat_ptr, stat_rec.st_gid);
3059 SET_MEMORY_W (stat_ptr, stat_rec.st_rdev);
3061 SET_MEMORY_L (stat_ptr, stat_rec.st_size);
3063 SET_MEMORY_L (stat_ptr, stat_rec.st_atime);
3065 SET_MEMORY_L (stat_ptr, stat_rec.st_mtime);
3067 SET_MEMORY_L (stat_ptr, stat_rec.st_ctime);
3069 /* Return value in register 0. */
3070 h8_set_reg (sd, 0, fstat_return);
3074 case O (O_SYS_STAT, SB):
3076 int len = 0; /* Length of filename. */
3077 char *filename; /* Filename would go here. */
3078 char temp_char; /* Temporary character */
3079 int filename_ptr; /* Pointer to filename in cpu memory. */
3080 struct stat stat_rec; /* Stat record */
3081 int stat_return; /* Return value from callback to stat */
3082 int stat_ptr; /* Pointer to stat record. */
3083 char *temp_stat_ptr; /* Temporary stat_rec pointer. */
3084 int i = 0; /* Loop Counter */
3086 /* Setting filename_ptr to first argument of open. */
3087 filename_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (0) : GET_W_REG (0);
3089 /* Trying to find the length of the filename. */
3090 temp_char = GET_MEMORY_B (h8_get_reg (sd, 0));
3093 while (temp_char != '\0')
3095 temp_char = GET_MEMORY_B (filename_ptr + len);
3099 /* Allocating space for the filename. */
3100 filename = (char *) malloc (sizeof (char) * len);
3102 /* String copying the filename from memory. */
3103 for (i = 0; i < len; i++)
3105 temp_char = GET_MEMORY_B (filename_ptr + i);
3106 filename[i] = temp_char;
3109 /* Setting stat_ptr to second argument of stat. */
3110 /* stat_ptr = h8_get_reg (sd, 1); */
3111 stat_ptr = (h8300hmode && !h8300_normal_mode) ? GET_L_REG (1) : GET_W_REG (1);
3113 /* Callback stat and return. */
3115 sim_callback->to_stat (sim_callback, filename, &stat_rec);
3117 /* Have stat_ptr point to starting of stat_rec. */
3118 temp_stat_ptr = (char *) (&stat_rec);
3120 /* Freeing memory used for filename. */
3123 /* Setting up the stat structure returned. */
3124 SET_MEMORY_W (stat_ptr, stat_rec.st_dev);
3126 SET_MEMORY_W (stat_ptr, stat_rec.st_ino);
3128 SET_MEMORY_L (stat_ptr, stat_rec.st_mode);
3130 SET_MEMORY_W (stat_ptr, stat_rec.st_nlink);
3132 SET_MEMORY_W (stat_ptr, stat_rec.st_uid);
3134 SET_MEMORY_W (stat_ptr, stat_rec.st_gid);
3136 SET_MEMORY_W (stat_ptr, stat_rec.st_rdev);
3138 SET_MEMORY_L (stat_ptr, stat_rec.st_size);
3140 SET_MEMORY_L (stat_ptr, stat_rec.st_atime);
3142 SET_MEMORY_L (stat_ptr, stat_rec.st_mtime);
3144 SET_MEMORY_L (stat_ptr, stat_rec.st_ctime);
3146 /* Return value in register 0. */
3147 h8_set_reg (sd, 0, stat_return);
3150 /* End of system call processing. */
3152 case O (O_NOT, SB): /* not.b */
3153 if (fetch2 (sd, &code->src, &rd))
3159 case O (O_NOT, SW): /* not.w */
3160 if (fetch2 (sd, &code->src, &rd))
3166 case O (O_NOT, SL): /* not.l */
3167 if (fetch2 (sd, &code->src, &rd))
3173 case O (O_SHLL, SB): /* shll.b */
3174 case O (O_SHLR, SB): /* shlr.b */
3175 if (fetch2 (sd, &code->dst, &rd))
3178 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3179 ea = 1; /* unary op */
3180 else /* binary op */
3181 fetch (sd, &code->src, &ea);
3183 if (code->opcode == O (O_SHLL, SB))
3186 c = rd & (0x80 >> (ea - 1));
3192 c = rd & (1 << (ea - 1));
3193 rd = (unsigned char) rd >> ea;
3197 case O (O_SHLL, SW): /* shll.w */
3198 case O (O_SHLR, SW): /* shlr.w */
3199 if (fetch2 (sd, &code->dst, &rd))
3202 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3203 ea = 1; /* unary op */
3205 fetch (sd, &code->src, &ea);
3207 if (code->opcode == O (O_SHLL, SW))
3210 c = rd & (0x8000 >> (ea - 1));
3216 c = rd & (1 << (ea - 1));
3217 rd = (unsigned short) rd >> ea;
3221 case O (O_SHLL, SL): /* shll.l */
3222 case O (O_SHLR, SL): /* shlr.l */
3223 if (fetch2 (sd, &code->dst, &rd))
3226 if (memcmp (&code->src, &code->dst, sizeof (code->src)) == 0)
3227 ea = 1; /* unary op */
3229 fetch (sd, &code->src, &ea);
3231 if (code->opcode == O (O_SHLL, SL))
3234 c = rd & (0x80000000 >> (ea - 1));
3240 c = rd & (1 << (ea - 1));
3241 rd = (unsigned int) rd >> ea;
3245 case O (O_SHAL, SB):
3246 case O (O_SHAR, SB):
3247 if (fetch2 (sd, &code->dst, &rd))
3250 if (code->src.type == X (OP_IMM, SB))
3251 fetch (sd, &code->src, &ea);
3255 if (code->opcode == O (O_SHAL, SB))
3257 c = rd & (0x80 >> (ea - 1));
3258 res = rd >> (7 - ea);
3259 v = ((res & 1) && !(res & 2))
3260 || (!(res & 1) && (res & 2));
3265 c = rd & (1 << (ea - 1));
3267 rd = ((signed char) rd) >> ea;
3271 case O (O_SHAL, SW):
3272 case O (O_SHAR, SW):
3273 if (fetch2 (sd, &code->dst, &rd))
3276 if (code->src.type == X (OP_IMM, SW))
3277 fetch (sd, &code->src, &ea);
3281 if (code->opcode == O (O_SHAL, SW))
3283 c = rd & (0x8000 >> (ea - 1));
3284 res = rd >> (15 - ea);
3285 v = ((res & 1) && !(res & 2))
3286 || (!(res & 1) && (res & 2));
3291 c = rd & (1 << (ea - 1));
3293 rd = ((signed short) rd) >> ea;
3297 case O (O_SHAL, SL):
3298 case O (O_SHAR, SL):
3299 if (fetch2 (sd, &code->dst, &rd))
3302 if (code->src.type == X (OP_IMM, SL))
3303 fetch (sd, &code->src, &ea);
3307 if (code->opcode == O (O_SHAL, SL))
3309 c = rd & (0x80000000 >> (ea - 1));
3310 res = rd >> (31 - ea);
3311 v = ((res & 1) && !(res & 2))
3312 || (!(res & 1) && (res & 2));
3317 c = rd & (1 << (ea - 1));
3319 rd = ((signed int) rd) >> ea;
3323 case O (O_ROTL, SB):
3324 case O (O_ROTR, SB):
3325 if (fetch2 (sd, &code->dst, &rd))
3328 if (code->src.type == X (OP_IMM, SB))
3329 fetch (sd, &code->src, &ea);
3334 if (code->opcode == O (O_ROTL, SB))
3344 rd = ((unsigned char) rd) >> 1;
3352 case O (O_ROTL, SW):
3353 case O (O_ROTR, SW):
3354 if (fetch2 (sd, &code->dst, &rd))
3357 if (code->src.type == X (OP_IMM, SW))
3358 fetch (sd, &code->src, &ea);
3363 if (code->opcode == O (O_ROTL, SW))
3373 rd = ((unsigned short) rd) >> 1;
3381 case O (O_ROTL, SL):
3382 case O (O_ROTR, SL):
3383 if (fetch2 (sd, &code->dst, &rd))
3386 if (code->src.type == X (OP_IMM, SL))
3387 fetch (sd, &code->src, &ea);
3392 if (code->opcode == O (O_ROTL, SL))
3394 c = rd & 0x80000000;
3402 rd = ((unsigned int) rd) >> 1;
3410 case O (O_ROTXL, SB):
3411 case O (O_ROTXR, SB):
3412 if (fetch2 (sd, &code->dst, &rd))
3415 if (code->src.type == X (OP_IMM, SB))
3416 fetch (sd, &code->src, &ea);
3421 if (code->opcode == O (O_ROTXL, SB))
3432 rd = ((unsigned char) rd) >> 1;
3441 case O (O_ROTXL, SW):
3442 case O (O_ROTXR, SW):
3443 if (fetch2 (sd, &code->dst, &rd))
3446 if (code->src.type == X (OP_IMM, SW))
3447 fetch (sd, &code->src, &ea);
3452 if (code->opcode == O (O_ROTXL, SW))
3463 rd = ((unsigned short) rd) >> 1;
3472 case O (O_ROTXL, SL):
3473 case O (O_ROTXR, SL):
3474 if (fetch2 (sd, &code->dst, &rd))
3477 if (code->src.type == X (OP_IMM, SL))
3478 fetch (sd, &code->src, &ea);
3483 if (code->opcode == O (O_ROTXL, SL))
3485 res = rd & 0x80000000;
3494 rd = ((unsigned int) rd) >> 1;
3505 case O (O_JMP, SB): /* jmp */
3507 fetch (sd, &code->src, &pc);
3512 case O (O_JSR, SB): /* jsr, jump to subroutine */
3514 if (fetch (sd, &code->src, &pc))
3517 tmp = h8_get_reg (sd, SP_REGNUM);
3519 if (h8300hmode && !h8300_normal_mode)
3522 SET_MEMORY_L (tmp, code->next_pc);
3527 SET_MEMORY_W (tmp, code->next_pc);
3529 h8_set_reg (sd, SP_REGNUM, tmp);
3535 case O (O_BSR, SB): /* bsr, branch to subroutine */
3536 if (fetch (sd, &code->src, &res))
3538 pc = code->next_pc + res;
3541 case O (O_RTE, SN): /* rte, return from exception */
3543 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3544 tmp = h8_get_reg (sd, SP_REGNUM);
3546 if (h8300smode) /* pop exr */
3548 h8_set_exr (sd, GET_MEMORY_L (tmp));
3551 if (h8300hmode && !h8300_normal_mode)
3553 h8_set_ccr (sd, GET_MEMORY_L (tmp));
3555 pc = GET_MEMORY_L (tmp);
3560 h8_set_ccr (sd, GET_MEMORY_W (tmp));
3562 pc = GET_MEMORY_W (tmp);
3567 h8_set_reg (sd, SP_REGNUM, tmp);
3570 case O (O_RTS, SN): /* rts, return from subroutine */
3572 tmp = h8_get_reg (sd, SP_REGNUM);
3574 if (h8300hmode && !h8300_normal_mode)
3576 pc = GET_MEMORY_L (tmp);
3581 pc = GET_MEMORY_W (tmp);
3585 h8_set_reg (sd, SP_REGNUM, tmp);
3588 case O (O_ILL, SB): /* illegal */
3589 sim_engine_set_run_state (sd, sim_stopped, SIGILL);
3592 case O (O_SLEEP, SN): /* sleep */
3593 /* Check for magic numbers in r1 and r2. */
3594 if ((h8_get_reg (sd, R1_REGNUM) & 0xffff) == LIBC_EXIT_MAGIC1 &&
3595 (h8_get_reg (sd, R2_REGNUM) & 0xffff) == LIBC_EXIT_MAGIC2 &&
3596 SIM_WIFEXITED (h8_get_reg (sd, 0)))
3598 /* This trap comes from _exit, not from gdb. */
3599 sim_engine_set_run_state (sd, sim_exited,
3600 SIM_WEXITSTATUS (h8_get_reg (sd, 0)));
3603 /* Unfortunately this won't really work, because
3604 when we take a breakpoint trap, R0 has a "random",
3605 user-defined value. Don't see any immediate solution. */
3606 else if (SIM_WIFSTOPPED (h8_get_reg (sd, 0)))
3608 /* Pass the stop signal up to gdb. */
3609 sim_engine_set_run_state (sd, sim_stopped,
3610 SIM_WSTOPSIG (h8_get_reg (sd, 0)));
3615 /* Treat it as a sigtrap. */
3616 sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
3620 case O (O_TRAPA, SB): /* trapa */
3621 if (fetch (sd, &code->src, &res))
3622 goto end; /* res is vector number. */
3624 tmp = h8_get_reg (sd, SP_REGNUM);
3625 if(h8300_normal_mode)
3628 SET_MEMORY_W (tmp, code->next_pc);
3630 SET_MEMORY_W (tmp, h8_get_ccr (sd));
3635 SET_MEMORY_L (tmp, code->next_pc);
3637 SET_MEMORY_L (tmp, h8_get_ccr (sd));
3645 SET_MEMORY_L (tmp, h8_get_exr (sd));
3648 h8_set_reg (sd, SP_REGNUM, tmp);
3650 if(h8300_normal_mode)
3651 pc = GET_MEMORY_L (0x10 + res * 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3653 pc = GET_MEMORY_L (0x20 + res * 4);
3657 sim_engine_set_run_state (sd, sim_stopped, SIGTRAP);
3660 case O (O_BSETEQ, SB):
3665 case O (O_BSETNE, SB):
3670 case O (O_BCLREQ, SB):
3675 case O (O_BCLRNE, SB):
3680 OBITOP (O_BNOT, 1, 1, ea ^= m); /* bnot */
3681 OBITOP (O_BTST, 1, 0, nz = ea & m); /* btst */
3683 OBITOP (O_BSET, 1, 1, ea |= m); /* bset */
3685 OBITOP (O_BCLR, 1, 1, ea &= ~m); /* bclr */
3686 OBITOP (O_BLD, 1, 0, c = ea & m); /* bld */
3687 OBITOP (O_BILD, 1, 0, c = !(ea & m)); /* bild */
3688 OBITOP (O_BST, 1, 1, ea &= ~m;
3689 if (C) ea |= m); /* bst */
3690 OBITOP (O_BIST, 1, 1, ea &= ~m;
3691 if (!C) ea |= m); /* bist */
3692 OBITOP (O_BSTZ, 1, 1, ea &= ~m;
3693 if (Z) ea |= m); /* bstz */
3694 OBITOP (O_BISTZ, 1, 1, ea &= ~m;
3695 if (!Z) ea |= m); /* bistz */
3696 OBITOP (O_BAND, 1, 0, c = (ea & m) && C); /* band */
3697 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); /* biand */
3698 OBITOP (O_BOR, 1, 0, c = (ea & m) || C); /* bor */
3699 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); /* bior */
3700 OBITOP (O_BXOR, 1, 0, c = ((ea & m) != 0)!= C); /* bxor */
3701 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); /* bixor */
3703 case O (O_BFLD, SB): /* bfld */
3706 if (fetch (sd, &code->src, &bit))
3711 if (fetch (sd, &code->dst, &ea))
3721 if (store (sd, &code->op3, ea))
3726 case O(O_BFST, SB): /* bfst */
3727 /* bitfield store */
3728 /* NOTE: the imm8 value is in dst, and the ea value
3729 (which is actually the destination) is in op3.
3730 It has to be that way, to avoid breaking the assembler. */
3732 if (fetch (sd, &code->dst, &bit)) /* imm8 */
3734 if (bit == 0) /* noop -- nothing to do. */
3737 if (fetch (sd, &code->src, &rd)) /* reg8 src */
3740 if (fetch2 (sd, &code->op3, &ea)) /* ea dst */
3743 /* Left-shift the register data into position. */
3744 for (tmp = bit; !(tmp & 1); tmp >>= 1)
3747 /* Combine it with the neighboring bits. */
3748 ea = (ea & ~bit) | (rd & bit);
3751 if (store2 (sd, &code->op3, ea))
3755 case O (O_CLRMAC, SN): /* clrmac */
3756 h8_set_mach (sd, 0);
3757 h8_set_macl (sd, 0);
3758 h8_set_macZ (sd, 1);
3759 h8_set_macV (sd, 0);
3760 h8_set_macN (sd, 0);
3763 case O (O_STMAC, SL): /* stmac, 260 */
3764 switch (code->src.type) {
3765 case X (OP_MACH, SL):
3766 res = h8_get_mach (sd);
3767 if (res & 0x200) /* sign extend */
3770 case X (OP_MACL, SL):
3771 res = h8_get_macl (sd);
3773 default: goto illegal;
3775 nz = !h8_get_macZ (sd);
3776 n = h8_get_macN (sd);
3777 v = h8_get_macV (sd);
3779 if (store (sd, &code->dst, res))
3784 case O (O_LDMAC, SL): /* ldmac, 179 */
3785 if (fetch (sd, &code->src, &rd))
3788 switch (code->dst.type) {
3789 case X (OP_MACH, SL):
3790 rd &= 0x3ff; /* Truncate to 10 bits */
3791 h8_set_mach (sd, rd);
3793 case X (OP_MACL, SL):
3794 h8_set_macl (sd, rd);
3796 default: goto illegal;
3798 h8_set_macV (sd, 0);
3802 if (fetch (sd, &code->src, &rd) ||
3803 fetch (sd, &code->dst, &res))
3806 /* Ye gods, this is non-portable!
3807 However, the existing mul/div code is similar. */
3808 res = SEXTSHORT (res) * SEXTSHORT (rd);
3810 if (h8_get_macS (sd)) /* Saturating mode */
3812 long long mac = h8_get_macl (sd);
3814 if (mac & 0x80000000) /* sign extend */
3815 mac |= 0xffffffff00000000LL;
3818 if (mac > 0x7fffffff || mac < 0xffffffff80000000LL)
3819 h8_set_macV (sd, 1);
3820 h8_set_macZ (sd, (mac == 0));
3821 h8_set_macN (sd, (mac < 0));
3822 h8_set_macl (sd, (int) mac);
3824 else /* "Less Saturating" mode */
3826 long long mac = h8_get_mach (sd);
3828 mac += h8_get_macl (sd);
3830 if (mac & 0x20000000000LL) /* sign extend */
3831 mac |= 0xfffffc0000000000LL;
3834 if (mac > 0x1ffffffffffLL ||
3835 mac < (long long) 0xfffffe0000000000LL)
3836 h8_set_macV (sd, 1);
3837 h8_set_macZ (sd, (mac == 0));
3838 h8_set_macN (sd, (mac < 0));
3839 h8_set_macl (sd, (int) mac);
3841 h8_set_mach (sd, (int) (mac & 0x3ff));
3845 case O (O_MULS, SW): /* muls.w */
3846 if (fetch (sd, &code->src, &ea) ||
3847 fetch (sd, &code->dst, &rd))
3850 ea = SEXTSHORT (ea);
3851 res = SEXTSHORT (ea * SEXTSHORT (rd));
3855 if (store (sd, &code->dst, res))
3860 case O (O_MULS, SL): /* muls.l */
3861 if (fetch (sd, &code->src, &ea) ||
3862 fetch (sd, &code->dst, &rd))
3867 n = res & 0x80000000;
3868 nz = res & 0xffffffff;
3869 if (store (sd, &code->dst, res))
3873 case O (O_MULSU, SL): /* muls/u.l */
3874 if (fetch (sd, &code->src, &ea) ||
3875 fetch (sd, &code->dst, &rd))
3878 /* Compute upper 32 bits of the 64-bit result. */
3879 res = (((long long) ea) * ((long long) rd)) >> 32;
3881 n = res & 0x80000000;
3882 nz = res & 0xffffffff;
3883 if (store (sd, &code->dst, res))
3887 case O (O_MULU, SW): /* mulu.w */
3888 if (fetch (sd, &code->src, &ea) ||
3889 fetch (sd, &code->dst, &rd))
3892 res = UEXTSHORT ((UEXTSHORT (ea) * UEXTSHORT (rd)));
3894 /* Don't set Z or N. */
3895 if (store (sd, &code->dst, res))
3900 case O (O_MULU, SL): /* mulu.l */
3901 if (fetch (sd, &code->src, &ea) ||
3902 fetch (sd, &code->dst, &rd))
3907 /* Don't set Z or N. */
3908 if (store (sd, &code->dst, res))
3913 case O (O_MULUU, SL): /* mulu/u.l */
3914 if (fetch (sd, &code->src, &ea) ||
3915 fetch (sd, &code->dst, &rd))
3918 /* Compute upper 32 bits of the 64-bit result. */
3919 res = (((unsigned long long) (unsigned) ea) *
3920 ((unsigned long long) (unsigned) rd)) >> 32;
3922 /* Don't set Z or N. */
3923 if (store (sd, &code->dst, res))
3928 case O (O_MULXS, SB): /* mulxs.b */
3929 if (fetch (sd, &code->src, &ea) ||
3930 fetch (sd, &code->dst, &rd))
3934 res = ea * SEXTCHAR (rd);
3938 if (store (sd, &code->dst, res))
3943 case O (O_MULXS, SW): /* mulxs.w */
3944 if (fetch (sd, &code->src, &ea) ||
3945 fetch (sd, &code->dst, &rd))
3948 ea = SEXTSHORT (ea);
3949 res = ea * SEXTSHORT (rd & 0xffff);
3951 n = res & 0x80000000;
3952 nz = res & 0xffffffff;
3953 if (store (sd, &code->dst, res))
3958 case O (O_MULXU, SB): /* mulxu.b */
3959 if (fetch (sd, &code->src, &ea) ||
3960 fetch (sd, &code->dst, &rd))
3963 res = UEXTCHAR (ea) * UEXTCHAR (rd);
3965 if (store (sd, &code->dst, res))
3970 case O (O_MULXU, SW): /* mulxu.w */
3971 if (fetch (sd, &code->src, &ea) ||
3972 fetch (sd, &code->dst, &rd))
3975 res = UEXTSHORT (ea) * UEXTSHORT (rd);
3977 if (store (sd, &code->dst, res))
3982 case O (O_TAS, SB): /* tas (test and set) */
3983 if (!h8300sxmode) /* h8sx can use any register. */
3984 switch (code->src.reg)
3995 if (fetch (sd, &code->src, &res))
3997 if (store (sd, &code->src, res | 0x80))
4000 goto just_flags_log8;
4002 case O (O_DIVU, SW): /* divu.w */
4003 if (fetch (sd, &code->src, &ea) ||
4004 fetch (sd, &code->dst, &rd))
4010 res = (unsigned) (UEXTSHORT (rd) / UEXTSHORT (ea));
4014 if (store (sd, &code->dst, res))
4018 case O (O_DIVU, SL): /* divu.l */
4019 if (fetch (sd, &code->src, &ea) ||
4020 fetch (sd, &code->dst, &rd))
4023 n = ea & 0x80000000;
4024 nz = ea & 0xffffffff;
4026 res = (unsigned) rd / ea;
4030 if (store (sd, &code->dst, res))
4034 case O (O_DIVS, SW): /* divs.w */
4035 if (fetch (sd, &code->src, &ea) ||
4036 fetch (sd, &code->dst, &rd))
4041 res = SEXTSHORT (rd) / SEXTSHORT (ea);
4051 if (store (sd, &code->dst, res))
4055 case O (O_DIVS, SL): /* divs.l */
4056 if (fetch (sd, &code->src, &ea) ||
4057 fetch (sd, &code->dst, &rd))
4071 n = res & 0x80000000;
4072 if (store (sd, &code->dst, res))
4076 case O (O_DIVXU, SB): /* divxu.b */
4077 if (fetch (sd, &code->src, &ea) ||
4078 fetch (sd, &code->dst, &rd))
4081 rd = UEXTSHORT (rd);
4088 tmp = (unsigned) rd % ea;
4089 res = (unsigned) rd / ea;
4097 if (store (sd, &code->dst, (res & 0xff) | (tmp << 8)))
4101 case O (O_DIVXU, SW): /* divxu.w */
4102 if (fetch (sd, &code->src, &ea) ||
4103 fetch (sd, &code->dst, &rd))
4106 ea = UEXTSHORT (ea);
4112 tmp = (unsigned) rd % ea;
4113 res = (unsigned) rd / ea;
4121 if (store (sd, &code->dst, (res & 0xffff) | (tmp << 16)))
4125 case O (O_DIVXS, SB): /* divxs.b */
4126 if (fetch (sd, &code->src, &ea) ||
4127 fetch (sd, &code->dst, &rd))
4130 rd = SEXTSHORT (rd);
4135 tmp = (int) rd % (int) ea;
4136 res = (int) rd / (int) ea;
4147 if (store (sd, &code->dst, (res & 0xff) | (tmp << 8)))
4151 case O (O_DIVXS, SW): /* divxs.w */
4152 if (fetch (sd, &code->src, &ea) ||
4153 fetch (sd, &code->dst, &rd))
4156 ea = SEXTSHORT (ea);
4160 tmp = (int) rd % (int) ea;
4161 res = (int) rd / (int) ea;
4171 n = res & 0x80000000;
4172 if (store (sd, &code->dst, (res & 0xffff) | (tmp << 16)))
4176 case O (O_EXTS, SW): /* exts.w, signed extend */
4177 if (fetch2 (sd, &code->dst, &rd))
4179 ea = rd & 0x80 ? -256 : 0;
4180 res = (rd & 0xff) + ea;
4183 case O (O_EXTS, SL): /* exts.l, signed extend */
4184 if (fetch2 (sd, &code->dst, &rd))
4186 if (code->src.type == X (OP_IMM, SL))
4188 if (fetch (sd, &code->src, &ea))
4191 if (ea == 2) /* exts.l #2, nn */
4193 /* Sign-extend from 8-bit to 32-bit. */
4194 ea = rd & 0x80 ? -256 : 0;
4195 res = (rd & 0xff) + ea;
4199 /* Sign-extend from 16-bit to 32-bit. */
4200 ea = rd & 0x8000 ? -65536 : 0;
4201 res = (rd & 0xffff) + ea;
4204 case O (O_EXTU, SW): /* extu.w, unsigned extend */
4205 if (fetch2 (sd, &code->dst, &rd))
4208 res = (rd & 0xff) + ea;
4211 case O (O_EXTU, SL): /* extu.l, unsigned extend */
4212 if (fetch2 (sd, &code->dst, &rd))
4214 if (code->src.type == X (OP_IMM, SL))
4216 if (fetch (sd, &code->src, &ea))
4219 if (ea == 2) /* extu.l #2, nn */
4221 /* Zero-extend from 8-bit to 32-bit. */
4223 res = (rd & 0xff) + ea;
4227 /* Zero-extend from 16-bit to 32-bit. */
4229 res = (rd & 0xffff) + ea;
4232 case O (O_NOP, SN): /* nop */
4235 case O (O_STM, SL): /* stm, store to memory */
4237 int nregs, firstreg, i;
4239 nregs = GET_MEMORY_B (pc + 1);
4242 firstreg = code->src.reg;
4244 for (i = firstreg; i <= firstreg + nregs; i++)
4246 h8_set_reg (sd, SP_REGNUM, h8_get_reg (sd, SP_REGNUM) - 4);
4247 SET_MEMORY_L (h8_get_reg (sd, SP_REGNUM), h8_get_reg (sd, i));
4252 case O (O_LDM, SL): /* ldm, load from memory */
4253 case O (O_RTEL, SN): /* rte/l, ldm plus rte */
4254 case O (O_RTSL, SN): /* rts/l, ldm plus rts */
4256 int nregs, firstreg, i;
4258 nregs = ((GET_MEMORY_B (pc + 1) >> 4) & 0xf);
4259 firstreg = code->dst.reg & 0xf;
4260 for (i = firstreg; i >= firstreg - nregs; i--)
4262 h8_set_reg (sd, i, GET_MEMORY_L (h8_get_reg (sd, SP_REGNUM)));
4263 h8_set_reg (sd, SP_REGNUM, h8_get_reg (sd, SP_REGNUM) + 4);
4266 switch (code->opcode) {
4267 case O (O_RTEL, SN):
4269 case O (O_RTSL, SN):
4278 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4279 res = GET_B_REG (code->src.reg); /* FIXME fetch? */
4280 if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4281 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4282 res = res; /* Value added == 0. */
4283 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) &&
4284 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4285 res = res + 0x6; /* Value added == 6. */
4286 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4287 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4288 res = res + 0x6; /* Value added == 6. */
4289 else if (!c && (10 <= (res >> 4) && (res >> 4) <= 15) &&
4290 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4291 res = res + 0x60; /* Value added == 60. */
4292 else if (!c && (9 <= (res >> 4) && (res >> 4) <= 15) &&
4293 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4294 res = res + 0x66; /* Value added == 66. */
4295 else if (!c && (10 <= (res >> 4) && (res >> 4) <= 15) &&
4296 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4297 res = res + 0x66; /* Value added == 66. */
4298 else if ( c && (1 <= (res >> 4) && (res >> 4) <= 2) &&
4299 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4300 res = res + 0x60; /* Value added == 60. */
4301 else if ( c && (1 <= (res >> 4) && (res >> 4) <= 2) &&
4302 !h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
4303 res = res + 0x66; /* Value added == 66. */
4304 else if (c && (1 <= (res >> 4) && (res >> 4) <= 3) &&
4305 h && (0 <= (res & 0xf) && (res & 0xf) <= 3))
4306 res = res + 0x66; /* Value added == 66. */
4311 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4312 res = GET_B_REG (code->src.reg); /* FIXME fetch, fetch2... */
4313 if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
4314 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4315 res = res; /* Value added == 0. */
4316 else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) &&
4317 h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
4318 res = res + 0xfa; /* Value added == 0xfa. */
4319 else if ( c && (7 <= (res >> 4) && (res >> 4) <= 15) &&
4320 !h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
4321 res = res + 0xa0; /* Value added == 0xa0. */
4322 else if (c && (6 <= (res >> 4) && (res >> 4) <= 15) &&
4323 h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
4324 res = res + 0x9a; /* Value added == 0x9a. */
4330 sim_engine_set_run_state (sd, sim_stopped, SIGILL);
4335 sim_io_printf (sd, "sim_resume: internal error.\n");
4336 sim_engine_set_run_state (sd, sim_stopped, SIGILL);
4340 if (code->dst.type == X (OP_CCR, SB) ||
4341 code->dst.type == X (OP_CCR, SW))
4343 h8_set_ccr (sd, res);
4346 else if (h8300smode &&
4347 (code->dst.type == X (OP_EXR, SB) ||
4348 code->dst.type == X (OP_EXR, SW)))
4350 h8_set_exr (sd, res);
4351 if (h8300smode) /* Get exr. */
4353 trace = (h8_get_exr (sd) >> 7) & 1;
4354 intMask = h8_get_exr (sd) & 7;
4363 /* When a branch works */
4364 if (fetch (sd, &code->src, &res))
4366 if (res & 1) /* bad address */
4368 pc = code->next_pc + res;
4371 /* Set the cond codes from res */
4374 /* Set the flags after an 8 bit inc/dec operation */
4378 v = (rd & 0x7f) == 0x7f;
4381 /* Set the flags after an 16 bit inc/dec operation */
4385 v = (rd & 0x7fff) == 0x7fff;
4388 /* Set the flags after an 32 bit inc/dec operation */
4390 n = res & 0x80000000;
4391 nz = res & 0xffffffff;
4392 v = (rd & 0x7fffffff) == 0x7fffffff;
4396 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4399 if (store2 (sd, &code->dst, rd))
4404 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4407 if (store2 (sd, &code->dst, rd))
4412 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4413 n = (rd & 0x80000000);
4414 nz = rd & 0xffffffff;
4415 if (store2 (sd, &code->dst, rd))
4420 if (store2 (sd, &code->dst, res))
4424 /* flags after a 32bit logical operation */
4425 n = res & 0x80000000;
4426 nz = res & 0xffffffff;
4431 if (store2 (sd, &code->dst, res))
4435 /* flags after a 16bit logical operation */
4442 if (store2 (sd, &code->dst, res))
4452 if (store2 (sd, &code->dst, res))
4459 switch (code->opcode / 4)
4463 v = ((rd & 0x80) == (ea & 0x80)
4464 && (rd & 0x80) != (res & 0x80));
4469 v = ((rd & 0x80) != (-ea & 0x80)
4470 && (rd & 0x80) != (res & 0x80));
4477 break; /* No effect on v flag. */
4482 if (store2 (sd, &code->dst, res))
4488 c = (res & 0x10000);
4489 switch (code->opcode / 4)
4493 v = ((rd & 0x8000) == (ea & 0x8000)
4494 && (rd & 0x8000) != (res & 0x8000));
4499 v = ((rd & 0x8000) != (-ea & 0x8000)
4500 && (rd & 0x8000) != (res & 0x8000));
4509 if (store2 (sd, &code->dst, res))
4513 n = res & 0x80000000;
4514 nz = res & 0xffffffff;
4515 switch (code->opcode / 4)
4519 v = ((rd & 0x80000000) == (ea & 0x80000000)
4520 && (rd & 0x80000000) != (res & 0x80000000));
4521 c = ((unsigned) res < (unsigned) rd) ||
4522 ((unsigned) res < (unsigned) ea);
4527 v = ((rd & 0x80000000) != (-ea & 0x80000000)
4528 && (rd & 0x80000000) != (res & 0x80000000));
4529 c = (unsigned) rd < (unsigned) -ea;
4532 v = (rd == 0x80000000);
4539 if ((res = h8_get_delayed_branch (sd)) != 0)
4542 h8_set_delayed_branch (sd, 0);
4549 if (--poll_count < 0)
4551 poll_count = POLL_QUIT_INTERVAL;
4552 if ((*sim_callback->poll_quit) != NULL
4553 && (*sim_callback->poll_quit) (sim_callback))
4554 sim_engine_set_run_state (sd, sim_stopped, SIGINT);
4556 sim_engine_get_run_state (sd, &reason, &sigrc);
4557 } while (reason == sim_running);
4559 h8_set_ticks (sd, h8_get_ticks (sd) + get_now () - tick_start);
4560 h8_set_cycles (sd, h8_get_cycles (sd) + cycles);
4561 h8_set_insts (sd, h8_get_insts (sd) + insts);
4566 h8_set_exr (sd, (trace<<7) | intMask);
4568 h8_set_mask (sd, oldmask);
4572 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
4579 for (i = 0; i < size; i++)
4581 if (addr < memory_size)
4583 h8_set_memory (sd, addr + i, buffer[i]);
4584 h8_set_cache_idx (sd, addr + i, 0);
4588 h8_set_eightbit (sd, (addr + i) & 0xff, buffer[i]);
4595 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
4600 if (addr < memory_size)
4601 memcpy (buffer, h8_get_memory_buf (sd) + addr, size);
4603 memcpy (buffer, h8_get_eightbit_buf (sd) + (addr & 0xff), size);
4609 sim_store_register (SIM_DESC sd, int rn, unsigned char *value, int length)
4614 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
4615 shortval = (value[0] << 8) | (value[1]);
4616 intval = h8300hmode ? longval : shortval;
4622 if(h8300_normal_mode)
4623 h8_set_pc (sd, shortval); /* PC for Normal mode is 2 bytes */
4625 h8_set_pc (sd, intval);
4628 sim_io_printf (sd, "sim_store_register: bad regnum %d.\n", rn);
4637 h8_set_reg (sd, rn, intval);
4640 h8_set_ccr (sd, intval);
4643 h8_set_exr (sd, intval);
4646 h8_set_sbr (sd, intval);
4649 h8_set_vbr (sd, intval);
4652 h8_set_mach (sd, intval);
4655 h8_set_macl (sd, intval);
4658 h8_set_cycles (sd, longval);
4662 h8_set_insts (sd, longval);
4666 h8_set_ticks (sd, longval);
4673 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
4680 if (!h8300smode && rn >= EXR_REGNUM)
4685 sim_io_printf (sd, "sim_fetch_register: bad regnum %d.\n", rn);
4689 v = h8_get_ccr (sd);
4692 v = h8_get_exr (sd);
4698 v = h8_get_sbr (sd);
4701 v = h8_get_vbr (sd);
4704 v = h8_get_mach (sd);
4707 v = h8_get_macl (sd);
4717 v = h8_get_reg (sd, rn);
4720 v = h8_get_cycles (sd);
4724 v = h8_get_ticks (sd);
4728 v = h8_get_insts (sd);
4732 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4733 if ((h8300hmode || longreg) && !(rn == PC_REGNUM && h8300_normal_mode))
4749 set_simcache_size (SIM_DESC sd, int n)
4752 free (sd->sim_cache);
4755 sd->sim_cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
4756 memset (sd->sim_cache, 0, sizeof (decoded_inst) * n);
4757 sd->sim_cache_size = n;
4762 sim_info (SIM_DESC sd, int verbose)
4764 double timetaken = (double) h8_get_ticks (sd) / (double) now_persec ();
4765 double virttime = h8_get_cycles (sd) / 10.0e6;
4767 sim_io_printf (sd, "\n\n#instructions executed %10d\n", h8_get_insts (sd));
4768 sim_io_printf (sd, "#cycles (v approximate) %10d\n", h8_get_cycles (sd));
4769 sim_io_printf (sd, "#real time taken %10.4f\n", timetaken);
4770 sim_io_printf (sd, "#virtual time taken %10.4f\n", virttime);
4771 if (timetaken != 0.0)
4772 sim_io_printf (sd, "#simulation ratio %10.4f\n", virttime / timetaken);
4773 sim_io_printf (sd, "#compiles %10d\n", h8_get_compiles (sd));
4774 sim_io_printf (sd, "#cache size %10d\n", sd->sim_cache_size);
4777 /* This to be conditional on `what' (aka `verbose'),
4778 however it was never passed as non-zero. */
4782 for (i = 0; i < O_LAST; i++)
4784 if (h8_get_stats (sd, i))
4785 sim_io_printf (sd, "%d: %d\n", i, h8_get_stats (sd, i));
4791 /* Indicate whether the cpu is an H8/300 or H8/300H.
4792 FLAG is non-zero for the H8/300H. */
4795 set_h8300h (unsigned long machine)
4797 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4798 This function being replaced by a sim_open:ARGV configuration
4801 h8300hmode = h8300smode = h8300sxmode = h8300_normal_mode = 0;
4803 if (machine == bfd_mach_h8300sx || machine == bfd_mach_h8300sxn)
4806 if (machine == bfd_mach_h8300s || machine == bfd_mach_h8300sn || h8300sxmode)
4809 if (machine == bfd_mach_h8300h || machine == bfd_mach_h8300hn || h8300smode)
4812 if(machine == bfd_mach_h8300hn || machine == bfd_mach_h8300sn || machine == bfd_mach_h8300sxn)
4813 h8300_normal_mode = 1;
4817 h8300_pc_get (sim_cpu *cpu)
4823 h8300_pc_set (sim_cpu *cpu, sim_cia pc)
4828 /* Cover function of sim_state_free to free the cpu buffers as well. */
4831 free_state (SIM_DESC sd)
4833 if (STATE_MODULES (sd) != NULL)
4834 sim_module_uninstall (sd);
4836 /* Fixme: free buffers in _sim_cpu. */
4837 sim_state_free (sd);
4841 sim_open (SIM_OPEN_KIND kind,
4842 struct host_callback_struct *callback,
4850 sd = sim_state_alloc (kind, callback);
4852 /* The cpu data is kept in a separately allocated chunk of memory. */
4853 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
4859 cpu = STATE_CPU (sd, 0);
4860 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
4861 sim_state_initialize (sd, cpu);
4862 /* sim_cpu object is new, so some initialization is needed. */
4863 init_pointers_needed = 1;
4865 /* For compatibility (FIXME: is this right?). */
4866 current_alignment = NONSTRICT_ALIGNMENT;
4867 current_target_byte_order = BIG_ENDIAN;
4869 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
4875 /* getopt will print the error message so we just have to exit if
4876 this fails. FIXME: Hmmm... in the case of gdb we need getopt
4877 to call print_filtered. */
4878 if (sim_parse_args (sd, argv) != SIM_RC_OK)
4880 /* Uninstall the modules to avoid memory leaks,
4881 file descriptor leaks, etc. */
4886 /* Check for/establish the a reference program image. */
4887 if (sim_analyze_program (sd,
4888 (STATE_PROG_ARGV (sd) != NULL
4889 ? *STATE_PROG_ARGV (sd)
4890 : NULL), abfd) != SIM_RC_OK)
4896 /* Establish any remaining configuration options. */
4897 if (sim_config (sd) != SIM_RC_OK)
4903 if (sim_post_argv_init (sd) != SIM_RC_OK)
4905 /* Uninstall the modules to avoid memory leaks,
4906 file descriptor leaks, etc. */
4911 /* CPU specific initialization. */
4912 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
4914 SIM_CPU *cpu = STATE_CPU (sd, i);
4916 CPU_PC_FETCH (cpu) = h8300_pc_get;
4917 CPU_PC_STORE (cpu) = h8300_pc_set;
4920 /* sim_hw_configure (sd); */
4922 /* FIXME: Much of the code in sim_load can be moved here. */
4927 /* Called by gdb to load a program into memory. */
4930 sim_load (SIM_DESC sd, const char *prog, bfd *abfd, int from_tty)
4934 /* FIXME: The code below that sets a specific variant of the H8/300
4935 being simulated should be moved to sim_open(). */
4937 /* See if the file is for the H8/300 or H8/300H. */
4938 /* ??? This may not be the most efficient way. The z8k simulator
4939 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4943 prog_bfd = bfd_openr (prog, NULL);
4944 if (prog_bfd != NULL)
4946 /* Set the cpu type. We ignore failure from bfd_check_format
4947 and bfd_openr as sim_load_file checks too. */
4948 if (bfd_check_format (prog_bfd, bfd_object))
4950 set_h8300h (bfd_get_mach (prog_bfd));
4954 /* If we're using gdb attached to the simulator, then we have to
4955 reallocate memory for the simulator.
4957 When gdb first starts, it calls fetch_registers (among other
4958 functions), which in turn calls init_pointers, which allocates
4961 The problem is when we do that, we don't know whether we're
4962 debugging an H8/300 or H8/300H program.
4964 This is the first point at which we can make that determination,
4965 so we just reallocate memory now; this will also allow us to handle
4966 switching between H8/300 and H8/300H programs without exiting
4969 if (h8300smode && !h8300_normal_mode)
4970 memory_size = H8300S_MSIZE;
4971 else if (h8300hmode && !h8300_normal_mode)
4972 memory_size = H8300H_MSIZE;
4974 memory_size = H8300_MSIZE;
4976 if (h8_get_memory_buf (sd))
4977 free (h8_get_memory_buf (sd));
4978 if (h8_get_cache_idx_buf (sd))
4979 free (h8_get_cache_idx_buf (sd));
4980 if (h8_get_eightbit_buf (sd))
4981 free (h8_get_eightbit_buf (sd));
4983 h8_set_memory_buf (sd, (unsigned char *)
4984 calloc (sizeof (char), memory_size));
4985 h8_set_cache_idx_buf (sd, (unsigned short *)
4986 calloc (sizeof (short), memory_size));
4987 sd->memory_size = memory_size;
4988 h8_set_eightbit_buf (sd, (unsigned char *) calloc (sizeof (char), 256));
4990 /* `msize' must be a power of two. */
4991 if ((memory_size & (memory_size - 1)) != 0)
4993 sim_io_printf (sd, "sim_load: bad memory size.\n");
4996 h8_set_mask (sd, memory_size - 1);
4998 if (sim_load_file (sd, STATE_MY_NAME (sd), STATE_CALLBACK (sd), prog,
4999 prog_bfd, STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG,
5003 /* Close the bfd if we opened it. */
5004 if (abfd == NULL && prog_bfd != NULL)
5005 bfd_close (prog_bfd);
5009 /* Close the bfd if we opened it. */
5010 if (abfd == NULL && prog_bfd != NULL)
5011 bfd_close (prog_bfd);
5016 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
5023 h8_set_pc (sd, bfd_get_start_address (abfd));
5027 /* Command Line support. */
5030 /* Counting the no. of commandline arguments. */
5031 for (no_of_args = 0; argv[no_of_args] != NULL; no_of_args++)
5034 /* Allocating memory for the argv pointers. */
5035 h8_set_command_line (sd, (char **) malloc ((sizeof (char *))
5036 * (no_of_args + 1)));
5038 for (i = 0; i < no_of_args; i++)
5040 /* Copying the argument string. */
5041 h8_set_cmdline_arg (sd, i, (char *) strdup (argv[i]));
5043 h8_set_cmdline_arg (sd, i, NULL);