1 /* Simulator for the FT32 processor
3 Copyright (C) 2008-2017 Free Software Foundation, Inc.
4 Contributed by FTDI <support@ftdichip.com>
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
28 #include "gdb/callback.h"
29 #include "libiberty.h"
30 #include "gdb/remote-sim.h"
33 #include "sim-options.h"
35 #include "opcode/ft32.h"
38 * FT32 is a Harvard architecture: RAM and code occupy
39 * different address spaces.
41 * sim and gdb model FT32 memory by adding 0x800000 to RAM
42 * addresses. This means that sim/gdb can treat all addresses
45 * The address space looks like:
47 * 00000 start of code memory
48 * 3ffff end of code memory
53 #define RAM_BIAS 0x800000 /* Bias added to RAM addresses. */
56 ft32_extract_unsigned_integer (unsigned char *addr, int len)
60 unsigned char *startaddr = (unsigned char *) addr;
61 unsigned char *endaddr = startaddr + len;
63 /* Start at the most significant end of the integer, and work towards
64 the least significant. */
67 for (p = endaddr; p > startaddr;)
68 retval = (retval << 8) | * -- p;
74 ft32_store_unsigned_integer (unsigned char *addr, int len, unsigned long val)
77 unsigned char *startaddr = (unsigned char *)addr;
78 unsigned char *endaddr = startaddr + len;
80 for (p = startaddr; p < endaddr; p++)
88 * Align EA according to its size DW.
89 * The FT32 ignores the low bit of a 16-bit addresss,
90 * and the low two bits of a 32-bit address.
92 static uint32_t ft32_align (uint32_t dw, uint32_t ea)
108 /* Read an item from memory address EA, sized DW. */
110 ft32_read_item (SIM_DESC sd, int dw, uint32_t ea)
112 sim_cpu *cpu = STATE_CPU (sd, 0);
113 address_word cia = CPU_PC_GET (cpu);
117 ea = ft32_align (dw, ea);
121 return sim_core_read_aligned_1 (cpu, cia, read_map, ea);
123 return sim_core_read_aligned_2 (cpu, cia, read_map, ea);
125 return sim_core_read_aligned_4 (cpu, cia, read_map, ea);
131 /* Write item V to memory address EA, sized DW. */
133 ft32_write_item (SIM_DESC sd, int dw, uint32_t ea, uint32_t v)
135 sim_cpu *cpu = STATE_CPU (sd, 0);
136 address_word cia = CPU_PC_GET (cpu);
139 ea = ft32_align (dw, ea);
143 sim_core_write_aligned_1 (cpu, cia, write_map, ea, v);
146 sim_core_write_aligned_2 (cpu, cia, write_map, ea, v);
149 sim_core_write_aligned_4 (cpu, cia, write_map, ea, v);
157 sim_engine_halt (sd, cpu, NULL, insnpc, sim_signalled, SIM_SIGILL)
159 static uint32_t cpu_mem_read (SIM_DESC sd, uint32_t dw, uint32_t ea)
161 sim_cpu *cpu = STATE_CPU (sd, 0);
162 uint32_t insnpc = cpu->state.pc;
169 /* Simulate some IO devices */
175 /* Read the simulator cycle timer. */
176 return cpu->state.cycles / 100;
178 sim_io_eprintf (sd, "Illegal IO read address %08x, pc %#x\n",
183 return ft32_read_item (sd, dw, RAM_BIAS + ea);
186 static void cpu_mem_write (SIM_DESC sd, uint32_t dw, uint32_t ea, uint32_t d)
188 sim_cpu *cpu = STATE_CPU (sd, 0);
192 /* Simulate some IO devices */
200 /* Unlock the PM write port */
201 cpu->state.pm_unlock = (d == 0x1337f7d1);
204 /* Set the PM write address register */
205 cpu->state.pm_addr = d;
208 if (cpu->state.pm_unlock)
211 ft32_write_item (sd, dw, cpu->state.pm_addr, d);
212 cpu->state.pm_addr += 4;
217 sim_engine_halt (sd, cpu, NULL, cpu->state.pc, sim_exited, cpu->state.regs[0]);
220 sim_io_printf (sd, "Debug write %08x\n", d);
223 sim_io_eprintf (sd, "Unknown IO write %08x to to %08x\n", d, ea);
227 ft32_write_item (sd, dw, RAM_BIAS + ea, d);
230 #define GET_BYTE(ea) cpu_mem_read (sd, 0, (ea))
231 #define PUT_BYTE(ea, d) cpu_mem_write (sd, 0, (ea), (d))
233 /* LSBS (n) is a mask of the least significant N bits. */
234 #define LSBS(n) ((1U << (n)) - 1)
236 static void ft32_push (SIM_DESC sd, uint32_t v)
238 sim_cpu *cpu = STATE_CPU (sd, 0);
239 cpu->state.regs[FT32_HARD_SP] -= 4;
240 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
241 cpu_mem_write (sd, 2, cpu->state.regs[FT32_HARD_SP], v);
244 static uint32_t ft32_pop (SIM_DESC sd)
246 sim_cpu *cpu = STATE_CPU (sd, 0);
247 uint32_t r = cpu_mem_read (sd, 2, cpu->state.regs[FT32_HARD_SP]);
248 cpu->state.regs[FT32_HARD_SP] += 4;
249 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
253 /* Extract the low SIZ bits of N as an unsigned number. */
254 static int nunsigned (int siz, int n)
256 return n & LSBS (siz);
259 /* Extract the low SIZ bits of N as a signed number. */
260 static int nsigned (int siz, int n)
262 int shift = (sizeof (int) * 8) - siz;
263 return (n << shift) >> shift;
266 /* Signed division N / D, matching hw behavior for (MIN_INT, -1). */
267 static uint32_t ft32sdiv (uint32_t n, uint32_t d)
269 if (n == 0x80000000UL && d == 0xffffffffUL)
272 return (uint32_t)((int)n / (int)d);
275 /* Signed modulus N % D, matching hw behavior for (MIN_INT, -1). */
276 static uint32_t ft32smod (uint32_t n, uint32_t d)
278 if (n == 0x80000000UL && d == 0xffffffffUL)
281 return (uint32_t)((int)n % (int)d);
284 /* Circular rotate right N by B bits. */
285 static uint32_t ror (uint32_t n, uint32_t b)
288 return (n >> b) | (n << (32 - b));
291 /* Implement the BINS machine instruction.
292 See FT32 Programmer's Reference for details. */
293 static uint32_t bins (uint32_t d, uint32_t f, uint32_t len, uint32_t pos)
295 uint32_t bitmask = LSBS (len) << pos;
296 return (d & ~bitmask) | ((f << pos) & bitmask);
299 /* Implement the FLIP machine instruction.
300 See FT32 Programmer's Reference for details. */
301 static uint32_t flip (uint32_t x, uint32_t b)
304 x = (x & 0x55555555) << 1 | (x & 0xAAAAAAAA) >> 1;
306 x = (x & 0x33333333) << 2 | (x & 0xCCCCCCCC) >> 2;
308 x = (x & 0x0F0F0F0F) << 4 | (x & 0xF0F0F0F0) >> 4;
310 x = (x & 0x00FF00FF) << 8 | (x & 0xFF00FF00) >> 8;
312 x = (x & 0x0000FFFF) << 16 | (x & 0xFFFF0000) >> 16;
317 step_once (SIM_DESC sd)
319 sim_cpu *cpu = STATE_CPU (sd, 0);
320 address_word cia = CPU_PC_GET (cpu);
346 inst = ft32_read_item (sd, 2, cpu->state.pc);
347 cpu->state.cycles += 1;
349 if ((STATE_ARCHITECTURE (sd)->mach == bfd_mach_ft32b)
350 && ft32_decode_shortcode (cpu->state.pc, inst, sc))
352 if ((cpu->state.pc & 3) == 0)
361 /* Handle "call 8" (which is FT32's "break" equivalent) here. */
362 if (inst == 0x00340002)
364 sim_engine_halt (sd, cpu, NULL,
366 sim_stopped, SIM_SIGTRAP);
370 dw = (inst >> FT32_FLD_DW_BIT) & LSBS (FT32_FLD_DW_SIZ);
371 cb = (inst >> FT32_FLD_CB_BIT) & LSBS (FT32_FLD_CB_SIZ);
372 r_d = (inst >> FT32_FLD_R_D_BIT) & LSBS (FT32_FLD_R_D_SIZ);
373 cr = (inst >> FT32_FLD_CR_BIT) & LSBS (FT32_FLD_CR_SIZ);
374 cv = (inst >> FT32_FLD_CV_BIT) & LSBS (FT32_FLD_CV_SIZ);
375 bt = (inst >> FT32_FLD_BT_BIT) & LSBS (FT32_FLD_BT_SIZ);
376 r_1 = (inst >> FT32_FLD_R_1_BIT) & LSBS (FT32_FLD_R_1_SIZ);
377 rimm = (inst >> FT32_FLD_RIMM_BIT) & LSBS (FT32_FLD_RIMM_SIZ);
378 r_2 = (inst >> FT32_FLD_R_2_BIT) & LSBS (FT32_FLD_R_2_SIZ);
379 k20 = nsigned (20, (inst >> FT32_FLD_K20_BIT) & LSBS (FT32_FLD_K20_SIZ));
380 pa = (inst >> FT32_FLD_PA_BIT) & LSBS (FT32_FLD_PA_SIZ);
381 aa = (inst >> FT32_FLD_AA_BIT) & LSBS (FT32_FLD_AA_SIZ);
382 k16 = (inst >> FT32_FLD_K16_BIT) & LSBS (FT32_FLD_K16_SIZ);
383 k15 = (inst >> FT32_FLD_K15_BIT) & LSBS (FT32_FLD_K15_SIZ);
388 al = (inst >> FT32_FLD_AL_BIT) & LSBS (FT32_FLD_AL_SIZ);
390 r_1v = cpu->state.regs[r_1];
391 rimmv = (rimm & 0x400) ? nsigned (10, rimm) : cpu->state.regs[rimm & 0x1f];
393 bit_pos = rimmv & 31;
394 bit_len = 0xf & (rimmv >> 5);
398 upper = (inst >> 27);
400 insnpc = cpu->state.pc;
401 cpu->state.pc += isize;
407 int take = (cr == 3) || ((1 & (cpu->state.regs[28 + cr] >> cb)) == cv);
410 cpu->state.cycles += 1;
412 ft32_push (sd, cpu->state.pc); /* this is a call. */
413 if (upper == FT32_PAT_TOC)
414 cpu->state.pc = pa << 2;
416 cpu->state.pc = cpu->state.regs[r_2];
417 if (cpu->state.pc == 0x8)
429 case 0x0: result = r_1v + rimmv; break;
430 case 0x1: result = ror (r_1v, rimmv); break;
431 case 0x2: result = r_1v - rimmv; break;
432 case 0x3: result = (r_1v << 10) | (1023 & rimmv); break;
433 case 0x4: result = r_1v & rimmv; break;
434 case 0x5: result = r_1v | rimmv; break;
435 case 0x6: result = r_1v ^ rimmv; break;
436 case 0x7: result = ~(r_1v ^ rimmv); break;
437 case 0x8: result = r_1v << rimmv; break;
438 case 0x9: result = r_1v >> rimmv; break;
439 case 0xa: result = (int32_t)r_1v >> rimmv; break;
440 case 0xb: result = bins (r_1v, rimmv >> 10, bit_len, bit_pos); break;
441 case 0xc: result = nsigned (bit_len, r_1v >> bit_pos); break;
442 case 0xd: result = nunsigned (bit_len, r_1v >> bit_pos); break;
443 case 0xe: result = flip (r_1v, rimmv); break;
445 sim_io_eprintf (sd, "Unhandled alu %#x\n", al);
448 if (upper == FT32_PAT_ALUOP)
449 cpu->state.regs[r_d] = result;
469 case 0: dwsiz = 7; dwmask = 0xffU; break;
470 case 1: dwsiz = 15; dwmask = 0xffffU; break;
471 case 2: dwsiz = 31; dwmask = 0xffffffffU; break;
474 zero = (0 == (result & dwmask));
475 sign = 1 & (result >> dwsiz);
476 ahi = 1 & (r_1v >> dwsiz);
477 bhi = 1 & (rimmv >> dwsiz);
478 overflow = (sign != ahi) & (ahi == !bhi);
484 case 0x0: carry = 1 & ((ra + rb) >> bit); break;
485 case 0x2: carry = 1 & ((ra - rb) >> bit); break;
486 default: carry = 0; break;
488 above = (!carry & !zero);
489 greater = (sign == overflow) & !zero;
490 greatereq = (sign == overflow);
492 cpu->state.regs[r_d] = (
505 cpu->state.regs[r_d] = k20;
509 cpu->state.regs[r_d] = ft32_read_item (sd, dw, pa << 2);
510 cpu->state.cycles += 1;
514 cpu->state.regs[r_d] = ft32_read_item (sd, dw, cpu->state.regs[r_1] + k15);
515 cpu->state.cycles += 1;
519 cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]);
523 cpu_mem_write (sd, dw, cpu->state.regs[r_d] + k15, cpu->state.regs[r_1]);
527 cpu->state.regs[r_d] = cpu_mem_read (sd, dw, aa);
528 cpu->state.cycles += 1;
532 cpu->state.regs[r_d] = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15);
533 cpu->state.cycles += 1;
539 tmp = cpu_mem_read (sd, dw, aa);
540 cpu_mem_write (sd, dw, aa, cpu->state.regs[r_d]);
541 cpu->state.regs[r_d] = tmp;
542 cpu->state.cycles += 1;
549 tmp = cpu_mem_read (sd, dw, cpu->state.regs[r_1] + k15);
550 cpu_mem_write (sd, dw, cpu->state.regs[r_1] + k15, cpu->state.regs[r_d]);
551 cpu->state.regs[r_d] = tmp;
552 cpu->state.cycles += 1;
557 ft32_push (sd, r_1v);
561 ft32_push (sd, cpu->state.regs[r_d]);
562 cpu->state.regs[r_d] = cpu->state.regs[FT32_HARD_SP];
563 cpu->state.regs[FT32_HARD_SP] -= k16;
564 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
567 case FT32_PAT_UNLINK:
568 cpu->state.regs[FT32_HARD_SP] = cpu->state.regs[r_d];
569 cpu->state.regs[FT32_HARD_SP] &= 0xffff;
570 cpu->state.regs[r_d] = ft32_pop (sd);
574 cpu->state.cycles += 1;
575 cpu->state.regs[r_d] = ft32_pop (sd);
578 case FT32_PAT_RETURN:
579 cpu->state.pc = ft32_pop (sd);
586 cpu->state.regs[r_d] = r_1v / rimmv;
589 cpu->state.regs[r_d] = r_1v % rimmv;
592 cpu->state.regs[r_d] = ft32sdiv (r_1v, rimmv);
595 cpu->state.regs[r_d] = ft32smod (r_1v, rimmv);
600 /* strcmp instruction. */
604 while ((GET_BYTE (a + i) != 0) &&
605 (GET_BYTE (a + i) == GET_BYTE (b + i)))
607 cpu->state.regs[r_d] = GET_BYTE (a + i) - GET_BYTE (b + i);
613 /* memcpy instruction. */
615 uint32_t dst = cpu->state.regs[r_d];
617 for (i = 0; i < (rimmv & 0x7fff); i++)
618 PUT_BYTE (dst + i, GET_BYTE (src + i));
623 /* strlen instruction. */
626 for (i = 0; GET_BYTE (src + i) != 0; i++)
628 cpu->state.regs[r_d] = i;
633 /* memset instruction. */
634 uint32_t dst = cpu->state.regs[r_d];
636 for (i = 0; i < (rimmv & 0x7fff); i++)
637 PUT_BYTE (dst + i, r_1v);
641 cpu->state.regs[r_d] = r_1v * rimmv;
644 cpu->state.regs[r_d] = ((uint64_t)r_1v * (uint64_t)rimmv) >> 32;
648 /* stpcpy instruction. */
650 uint32_t dst = cpu->state.regs[r_d];
652 for (i = 0; GET_BYTE (src + i) != 0; i++)
653 PUT_BYTE (dst + i, GET_BYTE (src + i));
654 PUT_BYTE (dst + i, 0);
655 cpu->state.regs[r_d] = dst + i;
660 /* streamout instruction. */
662 uint32_t src = cpu->state.regs[r_1];
663 for (i = 0; i < rimmv; i += (1 << dw))
667 cpu->state.regs[r_d],
668 cpu_mem_read (sd, dw, src));
674 sim_io_eprintf (sd, "Unhandled ffu %#x at %08x\n", al, insnpc);
680 sim_io_eprintf (sd, "Unhandled pattern %d at %08x\n", upper, insnpc);
690 sim_engine_run (SIM_DESC sd,
691 int next_cpu_nr, /* ignore */
692 int nr_cpus, /* ignore */
693 int siggnal) /* ignore */
697 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
699 cpu = STATE_CPU (sd, 0);
704 if (sim_events_tick (sd))
705 sim_events_process (sd);
710 ft32_lookup_register (SIM_CPU *cpu, int nr)
712 /* Handle the register number translation here.
713 * Sim registers are 0-31.
714 * Other tools (gcc, gdb) use:
721 if ((nr < 0) || (nr > 32))
723 sim_io_eprintf (CPU_STATE (cpu), "unknown register %i\n", nr);
730 return &cpu->state.regs[FT32_HARD_FP];
732 return &cpu->state.regs[FT32_HARD_SP];
734 return &cpu->state.regs[FT32_HARD_CC];
736 return &cpu->state.pc;
738 return &cpu->state.regs[nr - 2];
743 ft32_reg_store (SIM_CPU *cpu,
745 unsigned char *memory,
748 if (0 <= rn && rn <= 32)
751 *ft32_lookup_register (cpu, rn) = ft32_extract_unsigned_integer (memory, 4);
760 ft32_reg_fetch (SIM_CPU *cpu,
762 unsigned char *memory,
765 if (0 <= rn && rn <= 32)
768 ft32_store_unsigned_integer (memory, 4, *ft32_lookup_register (cpu, rn));
777 ft32_pc_get (SIM_CPU *cpu)
779 return cpu->state.pc;
783 ft32_pc_set (SIM_CPU *cpu, sim_cia newpc)
785 cpu->state.pc = newpc;
788 /* Cover function of sim_state_free to free the cpu buffers as well. */
791 free_state (SIM_DESC sd)
793 if (STATE_MODULES (sd) != NULL)
794 sim_module_uninstall (sd);
795 sim_cpu_free_all (sd);
800 sim_open (SIM_OPEN_KIND kind,
807 SIM_DESC sd = sim_state_alloc (kind, cb);
809 /* The cpu data is kept in a separately allocated chunk of memory. */
810 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
816 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
822 /* The parser will print an error message for us, so we silently return. */
823 if (sim_parse_args (sd, argv) != SIM_RC_OK)
829 /* Allocate external memory if none specified by user.
830 Use address 4 here in case the user wanted address 0 unmapped. */
831 if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
833 sim_do_command (sd, "memory region 0x00000000,0x40000");
834 sim_do_command (sd, "memory region 0x800000,0x10000");
837 /* Check for/establish the reference program image. */
838 if (sim_analyze_program (sd,
839 (STATE_PROG_ARGV (sd) != NULL
840 ? *STATE_PROG_ARGV (sd)
841 : NULL), abfd) != SIM_RC_OK)
847 /* Configure/verify the target byte order and other runtime
848 configuration options. */
849 if (sim_config (sd) != SIM_RC_OK)
855 if (sim_post_argv_init (sd) != SIM_RC_OK)
861 /* CPU specific initialization. */
862 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
864 SIM_CPU *cpu = STATE_CPU (sd, i);
866 CPU_REG_FETCH (cpu) = ft32_reg_fetch;
867 CPU_REG_STORE (cpu) = ft32_reg_store;
868 CPU_PC_FETCH (cpu) = ft32_pc_get;
869 CPU_PC_STORE (cpu) = ft32_pc_set;
876 sim_create_inferior (SIM_DESC sd,
882 sim_cpu *cpu = STATE_CPU (sd, 0);
886 addr = bfd_get_start_address (abfd);
890 /* Standalone mode (i.e. `run`) will take care of the argv for us in
891 sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
892 with `gdb`), we need to handle it because the user can change the
893 argv on the fly via gdb's 'run'. */
894 if (STATE_PROG_ARGV (sd) != argv)
896 freeargv (STATE_PROG_ARGV (sd));
897 STATE_PROG_ARGV (sd) = dupargv (argv);
899 cpu->state.regs[FT32_HARD_SP] = addr;
900 cpu->state.num_i = 0;
901 cpu->state.cycles = 0;
902 cpu->state.next_tick_cycle = 100000;