1 /* frv simulator support code
2 Copyright (C) 1998-2015 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Main header for the frv. */
22 #define USING_SIM_BASE_H /* FIXME: quick hack */
24 struct _sim_cpu; /* FIXME: should be in sim-basics.h */
25 typedef struct _sim_cpu SIM_CPU;
27 /* Set the mask of unsupported traces. */
29 (~(TRACE_alu | TRACE_decode | TRACE_memory | TRACE_model | TRACE_fpu \
30 | TRACE_branch | TRACE_debug))
32 /* sim-basics.h includes config.h but cgen-types.h must be included before
33 sim-basics.h and cgen-types.h needs config.h. */
37 #include "sim-basics.h"
38 #include "cgen-types.h"
43 #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) \
44 frv_sim_engine_halt_hook ((SD), (LAST_CPU), (CIA))
46 #define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA) 0
52 #include "registers.h"
55 void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia);
57 /* The _sim_cpu struct. */
60 /* sim/common cpu base. */
63 /* Static parts of cgen. */
66 /* CPU specific parts go here.
67 Note that in files that don't need to access these pieces WANT_CPU_FOO
68 won't be defined and thus these parts won't appear. This is ok in the
69 sense that things work. It is a source of bugs though.
70 One has to of course be careful to not take the size of this
71 struct and no structure members accessed in non-cpu specific files can
72 go after here. Oh for a better language. */
73 #if defined (WANT_CPU_FRVBF)
74 FRVBF_CPU_DATA cpu_data;
76 /* Control information for registers */
77 FRV_REGISTER_CONTROL register_control;
78 #define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control)
81 #define CPU_VLIW(cpu) (& (cpu)->vliw)
84 #define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache)
87 #define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache)
89 FRV_PROFILE_STATE profile_state;
90 #define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state)
93 #define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state)
96 #define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address)
99 #define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length)
102 #define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag)
103 #define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag)
106 #define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag)
108 unsigned long elf_flags;
109 #define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags)
110 #endif /* defined (WANT_CPU_FRVBF) */
113 /* The sim_state struct. */
116 sim_cpu *cpu[MAX_NR_PROCESSORS];
118 CGEN_STATE cgen_state;
125 /* Catch address exceptions. */
126 extern SIM_CORE_SIGNAL_FN frv_core_signal;
127 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
128 frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
131 /* Default memory size. */
132 #define FRV_DEFAULT_MEM_SIZE 0x800000 /* 8M */