1 /* Profiling definitions for the FRV simulator
2 Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of the GNU Simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* This struct defines the state of profiling. All fields are of general
25 use to all machines. */
28 long vliw_insns; /* total number of VLIW insns. */
29 long vliw_wait; /* number of cycles that the current VLIW insn must wait. */
30 long post_wait; /* number of cycles that post processing in the current
31 VLIW insn must wait. */
32 long vliw_cycles;/* number of cycles used by current VLIW insn. */
34 int past_first_p; /* Not the first insns in the VLIW */
36 /* Register latencies. Must be signed since they can be temporarily
38 int gr_busy[64]; /* Cycles until GR is available. */
39 int fr_busy[64]; /* Cycles until FR is available. */
40 int acc_busy[64]; /* Cycles until FR is available. */
41 int ccr_busy[8]; /* Cycles until ICC/FCC is available. */
42 int idiv_busy[2]; /* Cycles until integer division unit is available. */
43 int fdiv_busy[2]; /* Cycles until float division unit is available. */
44 int fsqrt_busy[2]; /* Cycles until square root unit is available. */
45 int branch_penalty; /* Cycles until branch is complete. */
47 int gr_latency[64]; /* Cycles until target GR is available. */
48 int fr_latency[64]; /* Cycles until target FR is available. */
49 int acc_latency[64]; /* Cycles until target FR is available. */
50 int ccr_latency[8]; /* Cycles until target ICC/FCC is available. */
52 /* Some registers are busy for a shorter number of cycles than normal
53 depending on how they are used next. the xxx_busy_adjust arrays keep track
54 of how many cycles to adjust down.
56 int fr_busy_adjust[64];
57 int acc_busy_adjust[64];
59 /* Register flags. Each bit represents one register. */
63 /* Keep track of the total queued post-processing time required before a
64 resource is available. This is applied to the resource's latency once all
65 pending loads for the resource are completed. */
68 int branch_hint; /* hint field from branch insn. */
69 USI branch_address; /* Address of predicted branch. */
70 USI insn_fetch_address;/* Address of sequential insns fetched. */
72 /* We need to know when the first branch of a vliw insn is taken, so that
73 we don't consider the remaining branches in the vliw insn. */
74 int vliw_branch_taken;
76 /* Keep track of the maximum load stall for each VLIW insn. */
79 /* Need to know if all cache entries are affected by various cache
81 int all_cache_entries;
84 #define DUAL_REG(reg) ((reg) >= 0 && (reg) < 63 ? (reg) + 1 : -1)
85 #define DUAL_DOUBLE(reg) ((reg) >= 0 && (reg) < 61 ? (reg) + 2 : -1)
87 /* Top up the latency of the given GR by the given number of cycles. */
88 void update_GR_latency (SIM_CPU *, INT, int);
89 void update_GRdouble_latency (SIM_CPU *, INT, int);
90 void update_GR_latency_for_load (SIM_CPU *, INT, int);
91 void update_GRdouble_latency_for_load (SIM_CPU *, INT, int);
92 void update_GR_latency_for_swap (SIM_CPU *, INT, int);
93 void update_FR_latency (SIM_CPU *, INT, int);
94 void update_FRdouble_latency (SIM_CPU *, INT, int);
95 void update_FR_latency_for_load (SIM_CPU *, INT, int);
96 void update_FRdouble_latency_for_load (SIM_CPU *, INT, int);
97 void decrease_ACC_busy (SIM_CPU *, INT, int);
98 void decrease_FR_busy (SIM_CPU *, INT, int);
99 void decrease_GR_busy (SIM_CPU *, INT, int);
100 void increase_FR_busy (SIM_CPU *, INT, int);
101 void update_ACC_latency (SIM_CPU *, INT, int);
102 void update_CCR_latency (SIM_CPU *, INT, int);
103 void update_idiv_resource_latency (SIM_CPU *, INT, int);
104 void update_fdiv_resource_latency (SIM_CPU *, INT, int);
105 void update_fsqrt_resource_latency (SIM_CPU *, INT, int);
106 void update_branch_penalty (SIM_CPU *, int);
107 void update_ACC_ptime (SIM_CPU *, INT, int);
108 void vliw_wait_for_GR (SIM_CPU *, INT);
109 void vliw_wait_for_GRdouble (SIM_CPU *, INT);
110 void vliw_wait_for_FR (SIM_CPU *, INT);
111 void vliw_wait_for_FRdouble (SIM_CPU *, INT);
112 void vliw_wait_for_CCR (SIM_CPU *, INT);
113 void vliw_wait_for_ACC (SIM_CPU *, INT);
114 void vliw_wait_for_idiv_resource (SIM_CPU *, INT);
115 void vliw_wait_for_fdiv_resource (SIM_CPU *, INT);
116 void vliw_wait_for_fsqrt_resource (SIM_CPU *, INT);
117 void load_wait_for_GR (SIM_CPU *, INT);
118 void load_wait_for_FR (SIM_CPU *, INT);
119 void load_wait_for_GRdouble (SIM_CPU *, INT);
120 void load_wait_for_FRdouble (SIM_CPU *, INT);
121 void enforce_full_fr_latency (SIM_CPU *, INT);
122 int post_wait_for_FR (SIM_CPU *, INT);
123 int post_wait_for_FRdouble (SIM_CPU *, INT);
124 int post_wait_for_ACC (SIM_CPU *, INT);
125 int post_wait_for_CCR (SIM_CPU *, INT);
126 int post_wait_for_fdiv (SIM_CPU *, INT);
127 int post_wait_for_fsqrt (SIM_CPU *, INT);
129 void trace_vliw_wait_cycles (SIM_CPU *);
130 void handle_resource_wait (SIM_CPU *);
132 void request_cache_load (SIM_CPU *, INT, int, int);
133 void request_cache_flush (SIM_CPU *, FRV_CACHE *, int);
134 void request_cache_invalidate (SIM_CPU *, FRV_CACHE *, int);
135 void request_cache_preload (SIM_CPU *, FRV_CACHE *, int);
136 void request_cache_unlock (SIM_CPU *, FRV_CACHE *, int);
137 int load_pending_for_register (SIM_CPU *, int, int, int);
139 void set_use_is_gr_complex (SIM_CPU *, INT);
140 void set_use_not_gr_complex (SIM_CPU *, INT);
141 int use_is_gr_complex (SIM_CPU *, INT);
147 } FRV_INSN_FETCH_BUFFER;
149 extern FRV_INSN_FETCH_BUFFER frv_insn_fetch_buffer[];
151 PROFILE_INFO_CPU_CALLBACK_FN frv_profile_info;
154 /* Simulator specific profile bits begin here. */
155 /* Profile caches. */
156 PROFILE_CACHE_IDX = PROFILE_NEXT_IDX,
157 /* Profile parallelization. */
161 /* Masks so WITH_PROFILE can have symbolic values.
162 The case choice here is on purpose. The lowercase parts are args to
164 #define PROFILE_cache (1 << PROFILE_INSN_IDX)
165 #define PROFILE_parallel (1 << PROFILE_INSN_IDX)
167 /* Preprocessor macros to simplify tests of WITH_PROFILE. */
168 #define WITH_PROFILE_CACHE_P (WITH_PROFILE & PROFILE_insn)
169 #define WITH_PROFILE_PARALLEL_P (WITH_PROFILE & PROFILE_insn)
171 #define FRV_COUNT_CYCLES(cpu, condition) \
172 ((PROFILE_MODEL_P (cpu) && (condition)) || frv_interrupt_state.timer.enabled)
174 /* Modelling support. */
175 extern int frv_save_profile_model_p;
177 extern enum FRV_INSN_MODELING {
178 FRV_INSN_NO_MODELING = 0,
179 FRV_INSN_MODEL_PASS_1,
180 FRV_INSN_MODEL_PASS_2,
181 FRV_INSN_MODEL_WRITEBACK
185 frv_model_advance_cycles (SIM_CPU *, int);
187 frv_model_trace_wait_cycles (SIM_CPU *, int, const char *);
189 /* Register types for queued load requests. */
190 #define REGTYPE_NONE 0
192 #define REGTYPE_ACC 2
194 #endif /* PROFILE_H */