1 /* frv simulator fr500 dependent profiling code.
3 Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
6 This file is part of the GNU simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License along
19 with this program; if not, write to the Free Software Foundation, Inc.,
20 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #define WANT_CPU_FRVBF
29 #if WITH_PROFILE_MODEL_P
32 #include "profile-fr500.h"
34 /* Initialize cycle counting for an insn.
35 FIRST_P is non-zero if this is the first insn in a set of parallel
38 fr500_model_insn_before (SIM_CPU *cpu, int first_p)
42 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
43 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
44 ps->cur_gr_complex = ps->prev_gr_complex;
45 d->cur_fpop = d->prev_fpop;
46 d->cur_media = d->prev_media;
47 d->cur_cc_complex = d->prev_cc_complex;
51 /* Record the cycles computed for an insn.
52 LAST_P is non-zero if this is the last insn in a set of parallel insns,
53 and we update the total cycle count.
54 CYCLES is the cycle count of the insn. */
56 fr500_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
60 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
61 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
62 ps->prev_gr_complex = ps->cur_gr_complex;
63 d->prev_fpop = d->cur_fpop;
64 d->prev_media = d->cur_media;
65 d->prev_cc_complex = d->cur_cc_complex;
70 set_use_is_fpop (SIM_CPU *cpu, INT fr)
72 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
73 fr500_reset_fr_flags (cpu, (fr));
74 d->cur_fpop |= (((DI)1) << (fr));
78 set_use_not_fpop (SIM_CPU *cpu, INT fr)
80 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
81 d->cur_fpop &= ~(((DI)1) << (fr));
85 use_is_fpop (SIM_CPU *cpu, INT fr)
87 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
88 return d->prev_fpop & (((DI)1) << (fr));
92 set_use_is_media ( SIM_CPU *cpu, INT fr)
94 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
95 fr500_reset_fr_flags (cpu, (fr));
96 d->cur_media |= (((DI)1) << (fr));
100 set_use_not_media (SIM_CPU *cpu, INT fr)
102 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
103 d->cur_media &= ~(((DI)1) << (fr));
107 use_is_media (SIM_CPU *cpu, INT fr)
109 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
110 return d->prev_media & (((DI)1) << (fr));
114 set_use_is_cc_complex (SIM_CPU *cpu, INT cc)
116 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
117 fr500_reset_cc_flags (cpu, cc);
118 d->cur_cc_complex |= (((DI)1) << (cc));
122 set_use_not_cc_complex (SIM_CPU *cpu, INT cc)
124 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
125 d->cur_cc_complex &= ~(((DI)1) << (cc));
129 use_is_cc_complex (SIM_CPU *cpu, INT cc)
131 MODEL_FR500_DATA *d = CPU_MODEL_DATA (cpu);
132 return d->prev_cc_complex & (((DI)1) << (cc));
136 fr500_reset_fr_flags (SIM_CPU *cpu, INT fr)
138 set_use_not_fpop (cpu, fr);
139 set_use_not_media (cpu, fr);
143 fr500_reset_cc_flags (SIM_CPU *cpu, INT cc)
145 set_use_not_cc_complex (cpu, cc);
148 /* Latency of floating point registers may be less than recorded when followed
149 by another floating point insn. */
151 adjust_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
154 /* If the registers were previously used in a floating point op,
155 then their latency will be less than previously recorded.
156 See Table 13-13 in the LSI. */
158 if (use_is_fpop (cpu, in_FRi))
159 decrease_FR_busy (cpu, in_FRi, cycles);
161 enforce_full_fr_latency (cpu, in_FRi);
163 if (in_FRj >= 0 && in_FRj != in_FRi)
164 if (use_is_fpop (cpu, in_FRj))
165 decrease_FR_busy (cpu, in_FRj, cycles);
167 enforce_full_fr_latency (cpu, in_FRj);
169 if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj)
170 if (use_is_fpop (cpu, out_FRk))
171 decrease_FR_busy (cpu, out_FRk, cycles);
173 enforce_full_fr_latency (cpu, out_FRk);
176 /* Latency of floating point registers may be less than recorded when followed
177 by another floating point insn. */
179 adjust_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
182 /* If the registers were previously used in a floating point op,
183 then their latency will be less than previously recorded.
184 See Table 13-13 in the LSI. */
185 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
186 if (in_FRi >= 0) ++in_FRi;
187 if (in_FRj >= 0) ++in_FRj;
188 if (out_FRk >= 0) ++out_FRk;
189 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
192 /* Latency of floating point registers is less than recorded when followed
193 by another floating point insn. */
195 restore_float_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
198 /* If the registers were previously used in a floating point op,
199 then their latency will be less than previously recorded.
200 See Table 13-13 in the LSI. */
201 if (in_FRi >= 0 && use_is_fpop (cpu, in_FRi))
202 increase_FR_busy (cpu, in_FRi, cycles);
203 if (in_FRj != in_FRi && use_is_fpop (cpu, in_FRj))
204 increase_FR_busy (cpu, in_FRj, cycles);
205 if (out_FRk != in_FRi && out_FRk != in_FRj && use_is_fpop (cpu, out_FRk))
206 increase_FR_busy (cpu, out_FRk, cycles);
209 /* Latency of floating point registers is less than recorded when followed
210 by another floating point insn. */
212 restore_double_register_busy (SIM_CPU *cpu, INT in_FRi, INT in_FRj, INT out_FRk,
215 /* If the registers were previously used in a floating point op,
216 then their latency will be less than previously recorded.
217 See Table 13-13 in the LSI. */
218 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
219 if (in_FRi >= 0) ++in_FRi;
220 if (in_FRj >= 0) ++in_FRj;
221 if (out_FRk >= 0) ++out_FRk;
222 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, cycles);
226 frvbf_model_fr500_u_exec (SIM_CPU *cpu, const IDESC *idesc,
227 int unit_num, int referenced)
229 return idesc->timing->units[unit_num].done;
233 frvbf_model_fr500_u_integer (SIM_CPU *cpu, const IDESC *idesc,
234 int unit_num, int referenced,
235 INT in_GRi, INT in_GRj, INT out_GRk,
240 if (model_insn == FRV_INSN_MODEL_PASS_1)
242 /* icc0-icc4 are the upper 4 fields of the CCR. */
246 /* The entire VLIW insn must wait if there is a dependency on a register
247 which is not ready yet.
248 The latency of the registers may be less than previously recorded,
249 depending on how they were used previously.
250 See Table 13-8 in the LSI. */
251 if (in_GRi != out_GRk && in_GRi >= 0)
253 if (use_is_gr_complex (cpu, in_GRi))
254 decrease_GR_busy (cpu, in_GRi, 1);
256 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
258 if (use_is_gr_complex (cpu, in_GRj))
259 decrease_GR_busy (cpu, in_GRj, 1);
261 vliw_wait_for_GR (cpu, in_GRi);
262 vliw_wait_for_GR (cpu, in_GRj);
263 vliw_wait_for_GR (cpu, out_GRk);
264 vliw_wait_for_CCR (cpu, out_ICCi_1);
265 handle_resource_wait (cpu);
266 load_wait_for_GR (cpu, in_GRi);
267 load_wait_for_GR (cpu, in_GRj);
268 load_wait_for_GR (cpu, out_GRk);
269 trace_vliw_wait_cycles (cpu);
273 /* GRk is available immediately to the next VLIW insn as is ICCi_1. */
274 cycles = idesc->timing->units[unit_num].done;
279 frvbf_model_fr500_u_imul (SIM_CPU *cpu, const IDESC *idesc,
280 int unit_num, int referenced,
281 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
284 /* icc0-icc4 are the upper 4 fields of the CCR. */
288 if (model_insn == FRV_INSN_MODEL_PASS_1)
290 /* The entire VLIW insn must wait if there is a dependency on a register
291 which is not ready yet.
292 The latency of the registers may be less than previously recorded,
293 depending on how they were used previously.
294 See Table 13-8 in the LSI. */
295 if (in_GRi != out_GRk && in_GRi >= 0)
297 if (use_is_gr_complex (cpu, in_GRi))
298 decrease_GR_busy (cpu, in_GRi, 1);
300 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
302 if (use_is_gr_complex (cpu, in_GRj))
303 decrease_GR_busy (cpu, in_GRj, 1);
305 vliw_wait_for_GR (cpu, in_GRi);
306 vliw_wait_for_GR (cpu, in_GRj);
307 vliw_wait_for_GRdouble (cpu, out_GRk);
308 vliw_wait_for_CCR (cpu, out_ICCi_1);
309 handle_resource_wait (cpu);
310 load_wait_for_GR (cpu, in_GRi);
311 load_wait_for_GR (cpu, in_GRj);
312 load_wait_for_GRdouble (cpu, out_GRk);
313 trace_vliw_wait_cycles (cpu);
317 /* GRk has a latency of 2 cycles. */
318 cycles = idesc->timing->units[unit_num].done;
319 update_GRdouble_latency (cpu, out_GRk, cycles + 2);
320 set_use_is_gr_complex (cpu, out_GRk);
321 set_use_is_gr_complex (cpu, out_GRk + 1);
323 /* ICCi_1 has a latency of 1 cycle. */
324 update_CCR_latency (cpu, out_ICCi_1, cycles + 1);
330 frvbf_model_fr500_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
331 int unit_num, int referenced,
332 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
338 /* icc0-icc4 are the upper 4 fields of the CCR. */
342 vliw = CPU_VLIW (cpu);
343 slot = vliw->next_slot - 1;
344 slot = (*vliw->current_vliw)[slot] - UNIT_I0;
346 if (model_insn == FRV_INSN_MODEL_PASS_1)
348 /* The entire VLIW insn must wait if there is a dependency on a register
349 which is not ready yet.
350 The latency of the registers may be less than previously recorded,
351 depending on how they were used previously.
352 See Table 13-8 in the LSI. */
353 if (in_GRi != out_GRk && in_GRi >= 0)
355 if (use_is_gr_complex (cpu, in_GRi))
356 decrease_GR_busy (cpu, in_GRi, 1);
358 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
360 if (use_is_gr_complex (cpu, in_GRj))
361 decrease_GR_busy (cpu, in_GRj, 1);
363 vliw_wait_for_GR (cpu, in_GRi);
364 vliw_wait_for_GR (cpu, in_GRj);
365 vliw_wait_for_GR (cpu, out_GRk);
366 vliw_wait_for_CCR (cpu, out_ICCi_1);
367 vliw_wait_for_idiv_resource (cpu, slot);
368 handle_resource_wait (cpu);
369 load_wait_for_GR (cpu, in_GRi);
370 load_wait_for_GR (cpu, in_GRj);
371 load_wait_for_GR (cpu, out_GRk);
372 trace_vliw_wait_cycles (cpu);
376 /* GRk has a latency of 19 cycles! */
377 cycles = idesc->timing->units[unit_num].done;
378 update_GR_latency (cpu, out_GRk, cycles + 19);
379 set_use_is_gr_complex (cpu, out_GRk);
381 /* ICCi_1 has a latency of 19 cycles. */
382 update_CCR_latency (cpu, out_ICCi_1, cycles + 19);
383 set_use_is_cc_complex (cpu, out_ICCi_1);
385 /* the idiv resource has a latency of 18 cycles! */
386 update_idiv_resource_latency (cpu, slot, cycles + 18);
392 frvbf_model_fr500_u_branch (SIM_CPU *cpu, const IDESC *idesc,
393 int unit_num, int referenced,
394 INT in_GRi, INT in_GRj,
395 INT in_ICCi_2, INT in_FCCi_2)
398 FRV_PROFILE_STATE *ps;
400 if (model_insn == FRV_INSN_MODEL_PASS_1)
402 /* icc0-icc4 are the upper 4 fields of the CCR. */
406 /* The entire VLIW insn must wait if there is a dependency on a register
407 which is not ready yet.
408 The latency of the registers may be less than previously recorded,
409 depending on how they were used previously.
410 See Table 13-8 in the LSI. */
413 if (use_is_gr_complex (cpu, in_GRi))
414 decrease_GR_busy (cpu, in_GRi, 1);
416 if (in_GRj != in_GRi && in_GRj >= 0)
418 if (use_is_gr_complex (cpu, in_GRj))
419 decrease_GR_busy (cpu, in_GRj, 1);
421 vliw_wait_for_GR (cpu, in_GRi);
422 vliw_wait_for_GR (cpu, in_GRj);
423 vliw_wait_for_CCR (cpu, in_ICCi_2);
424 vliw_wait_for_CCR (cpu, in_FCCi_2);
425 handle_resource_wait (cpu);
426 load_wait_for_GR (cpu, in_GRi);
427 load_wait_for_GR (cpu, in_GRj);
428 trace_vliw_wait_cycles (cpu);
432 /* When counting branches taken or not taken, don't consider branches after
433 the first taken branch in a vliw insn. */
434 ps = CPU_PROFILE_STATE (cpu);
435 if (! ps->vliw_branch_taken)
437 /* (1 << 4): The pc is the 5th element in inputs, outputs.
438 ??? can be cleaned up */
439 PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
440 int taken = (referenced & (1 << 4)) != 0;
443 ++PROFILE_MODEL_TAKEN_COUNT (p);
444 ps->vliw_branch_taken = 1;
447 ++PROFILE_MODEL_UNTAKEN_COUNT (p);
450 cycles = idesc->timing->units[unit_num].done;
455 frvbf_model_fr500_u_trap (SIM_CPU *cpu, const IDESC *idesc,
456 int unit_num, int referenced,
457 INT in_GRi, INT in_GRj,
458 INT in_ICCi_2, INT in_FCCi_2)
461 FRV_PROFILE_STATE *ps;
463 if (model_insn == FRV_INSN_MODEL_PASS_1)
465 /* icc0-icc4 are the upper 4 fields of the CCR. */
469 /* The entire VLIW insn must wait if there is a dependency on a register
470 which is not ready yet.
471 The latency of the registers may be less than previously recorded,
472 depending on how they were used previously.
473 See Table 13-8 in the LSI. */
476 if (use_is_gr_complex (cpu, in_GRi))
477 decrease_GR_busy (cpu, in_GRi, 1);
479 if (in_GRj != in_GRi && in_GRj >= 0)
481 if (use_is_gr_complex (cpu, in_GRj))
482 decrease_GR_busy (cpu, in_GRj, 1);
484 vliw_wait_for_GR (cpu, in_GRi);
485 vliw_wait_for_GR (cpu, in_GRj);
486 vliw_wait_for_CCR (cpu, in_ICCi_2);
487 vliw_wait_for_CCR (cpu, in_FCCi_2);
488 handle_resource_wait (cpu);
489 load_wait_for_GR (cpu, in_GRi);
490 load_wait_for_GR (cpu, in_GRj);
491 trace_vliw_wait_cycles (cpu);
495 cycles = idesc->timing->units[unit_num].done;
500 frvbf_model_fr500_u_check (SIM_CPU *cpu, const IDESC *idesc,
501 int unit_num, int referenced,
502 INT in_ICCi_3, INT in_FCCi_3)
505 FRV_PROFILE_STATE *ps;
507 if (model_insn == FRV_INSN_MODEL_PASS_1)
509 /* icc0-icc4 are the upper 4 fields of the CCR. */
513 /* The entire VLIW insn must wait if there is a dependency on a register
514 which is not ready yet. */
515 vliw_wait_for_CCR (cpu, in_ICCi_3);
516 vliw_wait_for_CCR (cpu, in_FCCi_3);
517 handle_resource_wait (cpu);
518 trace_vliw_wait_cycles (cpu);
522 cycles = idesc->timing->units[unit_num].done;
527 frvbf_model_fr500_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
528 int unit_num, int referenced,
529 INT out_GRkhi, INT out_GRklo)
533 if (model_insn == FRV_INSN_MODEL_PASS_1)
535 /* The entire VLIW insn must wait if there is a dependency on a GR
536 which is not ready yet. */
537 vliw_wait_for_GR (cpu, out_GRkhi);
538 vliw_wait_for_GR (cpu, out_GRklo);
539 handle_resource_wait (cpu);
540 load_wait_for_GR (cpu, out_GRkhi);
541 load_wait_for_GR (cpu, out_GRklo);
542 trace_vliw_wait_cycles (cpu);
546 /* GRk is available immediately to the next VLIW insn. */
547 cycles = idesc->timing->units[unit_num].done;
549 set_use_not_gr_complex (cpu, out_GRkhi);
550 set_use_not_gr_complex (cpu, out_GRklo);
556 frvbf_model_fr500_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
557 int unit_num, int referenced,
558 INT in_GRi, INT in_GRj,
559 INT out_GRk, INT out_GRdoublek)
563 if (model_insn == FRV_INSN_MODEL_PASS_1)
565 /* The entire VLIW insn must wait if there is a dependency on a register
566 which is not ready yet.
567 The latency of the registers may be less than previously recorded,
568 depending on how they were used previously.
569 See Table 13-8 in the LSI. */
570 if (in_GRi != out_GRk && in_GRi != out_GRdoublek
571 && in_GRi != out_GRdoublek + 1 && in_GRi >= 0)
573 if (use_is_gr_complex (cpu, in_GRi))
574 decrease_GR_busy (cpu, in_GRi, 1);
576 if (in_GRj != in_GRi && in_GRj != out_GRk && in_GRj != out_GRdoublek
577 && in_GRj != out_GRdoublek + 1 && in_GRj >= 0)
580 if (use_is_gr_complex (cpu, in_GRj))
581 decrease_GR_busy (cpu, in_GRj, 1);
583 vliw_wait_for_GR (cpu, in_GRi);
584 vliw_wait_for_GR (cpu, in_GRj);
585 vliw_wait_for_GR (cpu, out_GRk);
586 vliw_wait_for_GRdouble (cpu, out_GRdoublek);
587 handle_resource_wait (cpu);
588 load_wait_for_GR (cpu, in_GRi);
589 load_wait_for_GR (cpu, in_GRj);
590 load_wait_for_GR (cpu, out_GRk);
591 load_wait_for_GRdouble (cpu, out_GRdoublek);
592 trace_vliw_wait_cycles (cpu);
596 cycles = idesc->timing->units[unit_num].done;
598 /* The latency of GRk for a load will depend on how long it takes to retrieve
599 the the data from the cache or memory. */
600 update_GR_latency_for_load (cpu, out_GRk, cycles);
601 update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
603 set_use_is_gr_complex (cpu, out_GRk);
604 set_use_is_gr_complex (cpu, out_GRdoublek);
605 set_use_is_gr_complex (cpu, out_GRdoublek + 1);
611 frvbf_model_fr500_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
612 int unit_num, int referenced,
613 INT in_GRi, INT in_GRj,
614 INT in_GRk, INT in_GRdoublek)
618 if (model_insn == FRV_INSN_MODEL_PASS_1)
620 /* The entire VLIW insn must wait if there is a dependency on a register
621 which is not ready yet.
622 The latency of the registers may be less than previously recorded,
623 depending on how they were used previously.
624 See Table 13-8 in the LSI. */
627 if (use_is_gr_complex (cpu, in_GRi))
628 decrease_GR_busy (cpu, in_GRi, 1);
630 if (in_GRj != in_GRi && in_GRj >= 0)
632 if (use_is_gr_complex (cpu, in_GRj))
633 decrease_GR_busy (cpu, in_GRj, 1);
635 if (in_GRk != in_GRi && in_GRk != in_GRj && in_GRk >= 0)
637 if (use_is_gr_complex (cpu, in_GRk))
638 decrease_GR_busy (cpu, in_GRk, 1);
640 if (in_GRdoublek != in_GRi && in_GRdoublek != in_GRj
641 && in_GRdoublek + 1 != in_GRi && in_GRdoublek + 1 != in_GRj
642 && in_GRdoublek >= 0)
644 if (use_is_gr_complex (cpu, in_GRdoublek))
645 decrease_GR_busy (cpu, in_GRdoublek, 1);
646 if (use_is_gr_complex (cpu, in_GRdoublek + 1))
647 decrease_GR_busy (cpu, in_GRdoublek + 1, 1);
649 vliw_wait_for_GR (cpu, in_GRi);
650 vliw_wait_for_GR (cpu, in_GRj);
651 vliw_wait_for_GR (cpu, in_GRk);
652 vliw_wait_for_GRdouble (cpu, in_GRdoublek);
653 handle_resource_wait (cpu);
654 load_wait_for_GR (cpu, in_GRi);
655 load_wait_for_GR (cpu, in_GRj);
656 load_wait_for_GR (cpu, in_GRk);
657 load_wait_for_GRdouble (cpu, in_GRdoublek);
658 trace_vliw_wait_cycles (cpu);
662 cycles = idesc->timing->units[unit_num].done;
668 frvbf_model_fr500_u_gr_r_store (SIM_CPU *cpu, const IDESC *idesc,
669 int unit_num, int referenced,
670 INT in_GRi, INT in_GRj,
671 INT in_GRk, INT in_GRdoublek)
673 int cycles = frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced,
674 in_GRi, in_GRj, in_GRk,
677 if (model_insn == FRV_INSN_MODEL_PASS_2)
679 if (CPU_RSTR_INVALIDATE(cpu))
680 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
687 frvbf_model_fr500_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
688 int unit_num, int referenced,
689 INT in_GRi, INT in_GRj,
690 INT out_FRk, INT out_FRdoublek)
694 if (model_insn == FRV_INSN_MODEL_PASS_1)
696 /* The entire VLIW insn must wait if there is a dependency on a register
697 which is not ready yet.
698 The latency of the registers may be less than previously recorded,
699 depending on how they were used previously.
700 See Table 13-8 in the LSI. */
703 if (use_is_gr_complex (cpu, in_GRi))
704 decrease_GR_busy (cpu, in_GRi, 1);
706 if (in_GRj != in_GRi && in_GRj >= 0)
708 if (use_is_gr_complex (cpu, in_GRj))
709 decrease_GR_busy (cpu, in_GRj, 1);
713 if (use_is_media (cpu, out_FRk))
714 decrease_FR_busy (cpu, out_FRk, 1);
716 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
718 if (out_FRdoublek >= 0)
720 if (use_is_media (cpu, out_FRdoublek))
721 decrease_FR_busy (cpu, out_FRdoublek, 1);
723 adjust_float_register_busy (cpu, -1, -1, out_FRdoublek, 1);
724 if (use_is_media (cpu, out_FRdoublek + 1))
725 decrease_FR_busy (cpu, out_FRdoublek + 1, 1);
727 adjust_float_register_busy (cpu, -1, -1, out_FRdoublek + 1, 1);
729 vliw_wait_for_GR (cpu, in_GRi);
730 vliw_wait_for_GR (cpu, in_GRj);
731 vliw_wait_for_FR (cpu, out_FRk);
732 vliw_wait_for_FRdouble (cpu, out_FRdoublek);
733 handle_resource_wait (cpu);
734 load_wait_for_GR (cpu, in_GRi);
735 load_wait_for_GR (cpu, in_GRj);
736 load_wait_for_FR (cpu, out_FRk);
737 load_wait_for_FRdouble (cpu, out_FRdoublek);
738 trace_vliw_wait_cycles (cpu);
742 cycles = idesc->timing->units[unit_num].done;
744 /* The latency of FRk for a load will depend on how long it takes to retrieve
745 the the data from the cache or memory. */
746 update_FR_latency_for_load (cpu, out_FRk, cycles);
747 update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles);
749 fr500_reset_fr_flags (cpu, out_FRk);
755 frvbf_model_fr500_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
756 int unit_num, int referenced,
757 INT in_GRi, INT in_GRj,
758 INT in_FRk, INT in_FRdoublek)
762 if (model_insn == FRV_INSN_MODEL_PASS_1)
764 /* The entire VLIW insn must wait if there is a dependency on a register
765 which is not ready yet.
766 The latency of the registers may be less than previously recorded,
767 depending on how they were used previously.
768 See Table 13-8 in the LSI. */
771 if (use_is_gr_complex (cpu, in_GRi))
772 decrease_GR_busy (cpu, in_GRi, 1);
774 if (in_GRj != in_GRi && in_GRj >= 0)
776 if (use_is_gr_complex (cpu, in_GRj))
777 decrease_GR_busy (cpu, in_GRj, 1);
781 if (use_is_media (cpu, in_FRk))
782 decrease_FR_busy (cpu, in_FRk, 1);
784 adjust_float_register_busy (cpu, -1, -1, in_FRk, 1);
786 if (in_FRdoublek >= 0)
788 if (use_is_media (cpu, in_FRdoublek))
789 decrease_FR_busy (cpu, in_FRdoublek, 1);
791 adjust_float_register_busy (cpu, -1, -1, in_FRdoublek, 1);
792 if (use_is_media (cpu, in_FRdoublek + 1))
793 decrease_FR_busy (cpu, in_FRdoublek + 1, 1);
795 adjust_float_register_busy (cpu, -1, -1, in_FRdoublek + 1, 1);
797 vliw_wait_for_GR (cpu, in_GRi);
798 vliw_wait_for_GR (cpu, in_GRj);
799 vliw_wait_for_FR (cpu, in_FRk);
800 vliw_wait_for_FRdouble (cpu, in_FRdoublek);
801 handle_resource_wait (cpu);
802 load_wait_for_GR (cpu, in_GRi);
803 load_wait_for_GR (cpu, in_GRj);
804 load_wait_for_FR (cpu, in_FRk);
805 load_wait_for_FRdouble (cpu, in_FRdoublek);
806 trace_vliw_wait_cycles (cpu);
810 cycles = idesc->timing->units[unit_num].done;
816 frvbf_model_fr500_u_fr_r_store (SIM_CPU *cpu, const IDESC *idesc,
817 int unit_num, int referenced,
818 INT in_GRi, INT in_GRj,
819 INT in_FRk, INT in_FRdoublek)
821 int cycles = frvbf_model_fr500_u_fr_store (cpu, idesc, unit_num, referenced,
822 in_GRi, in_GRj, in_FRk,
825 if (model_insn == FRV_INSN_MODEL_PASS_2)
827 if (CPU_RSTR_INVALIDATE(cpu))
828 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
835 frvbf_model_fr500_u_swap (SIM_CPU *cpu, const IDESC *idesc,
836 int unit_num, int referenced,
837 INT in_GRi, INT in_GRj, INT out_GRk)
841 if (model_insn == FRV_INSN_MODEL_PASS_1)
843 /* The entire VLIW insn must wait if there is a dependency on a register
844 which is not ready yet.
845 The latency of the registers may be less than previously recorded,
846 depending on how they were used previously.
847 See Table 13-8 in the LSI. */
848 if (in_GRi != out_GRk && in_GRi >= 0)
850 if (use_is_gr_complex (cpu, in_GRi))
851 decrease_GR_busy (cpu, in_GRi, 1);
853 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0)
855 if (use_is_gr_complex (cpu, in_GRj))
856 decrease_GR_busy (cpu, in_GRj, 1);
858 vliw_wait_for_GR (cpu, in_GRi);
859 vliw_wait_for_GR (cpu, in_GRj);
860 vliw_wait_for_GR (cpu, out_GRk);
861 handle_resource_wait (cpu);
862 load_wait_for_GR (cpu, in_GRi);
863 load_wait_for_GR (cpu, in_GRj);
864 load_wait_for_GR (cpu, out_GRk);
865 trace_vliw_wait_cycles (cpu);
869 cycles = idesc->timing->units[unit_num].done;
871 /* The latency of GRk will depend on how long it takes to swap
872 the the data from the cache or memory. */
873 update_GR_latency_for_swap (cpu, out_GRk, cycles);
874 set_use_is_gr_complex (cpu, out_GRk);
880 frvbf_model_fr500_u_fr2fr (SIM_CPU *cpu, const IDESC *idesc,
881 int unit_num, int referenced,
882 INT in_FRj, INT out_FRk)
886 if (model_insn == FRV_INSN_MODEL_PASS_1)
888 /* The entire VLIW insn must wait if there is a dependency on a register
889 which is not ready yet. */
892 if (use_is_media (cpu, in_FRj))
893 decrease_FR_busy (cpu, in_FRj, 1);
895 adjust_float_register_busy (cpu, -1, in_FRj, -1, 1);
897 if (out_FRk >= 0 && out_FRk != in_FRj)
899 if (use_is_media (cpu, out_FRk))
900 decrease_FR_busy (cpu, out_FRk, 1);
902 adjust_float_register_busy (cpu, -1, -1, out_FRk, 1);
904 vliw_wait_for_FR (cpu, in_FRj);
905 vliw_wait_for_FR (cpu, out_FRk);
906 handle_resource_wait (cpu);
907 load_wait_for_FR (cpu, in_FRj);
908 load_wait_for_FR (cpu, out_FRk);
909 trace_vliw_wait_cycles (cpu);
913 /* The latency of FRj is 3 cycles. */
914 cycles = idesc->timing->units[unit_num].done;
915 update_FR_latency (cpu, out_FRk, cycles + 3);
921 frvbf_model_fr500_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
922 int unit_num, int referenced,
923 INT in_FRk, INT out_GRj)
927 if (model_insn == FRV_INSN_MODEL_PASS_1)
929 /* The entire VLIW insn must wait if there is a dependency on a register
930 which is not ready yet. */
933 if (use_is_media (cpu, in_FRk))
934 decrease_FR_busy (cpu, in_FRk, 1);
936 adjust_float_register_busy (cpu, -1, in_FRk, -1, 1);
938 vliw_wait_for_FR (cpu, in_FRk);
939 vliw_wait_for_GR (cpu, out_GRj);
940 handle_resource_wait (cpu);
941 load_wait_for_FR (cpu, in_FRk);
942 load_wait_for_GR (cpu, out_GRj);
943 trace_vliw_wait_cycles (cpu);
947 /* The latency of GRj is 2 cycles. */
948 cycles = idesc->timing->units[unit_num].done;
949 update_GR_latency (cpu, out_GRj, cycles + 2);
950 set_use_is_gr_complex (cpu, out_GRj);
956 frvbf_model_fr500_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
957 int unit_num, int referenced,
958 INT in_spr, INT out_GRj)
962 if (model_insn == FRV_INSN_MODEL_PASS_1)
964 /* The entire VLIW insn must wait if there is a dependency on a register
965 which is not ready yet.
966 SPR registers appear to have no latency effects. */
967 vliw_wait_for_GR (cpu, out_GRj);
968 handle_resource_wait (cpu);
969 load_wait_for_GR (cpu, out_GRj);
970 trace_vliw_wait_cycles (cpu);
974 cycles = idesc->timing->units[unit_num].done;
976 #if 0 /* no latency? */
977 /* The latency of GRj is 2 cycles. */
978 update_GR_latency (cpu, out_GRj, cycles + 2);
985 frvbf_model_fr500_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
986 int unit_num, int referenced,
987 INT in_GRj, INT out_FRk)
991 if (model_insn == FRV_INSN_MODEL_PASS_1)
993 /* The entire VLIW insn must wait if there is a dependency on a register
994 which is not ready yet.
995 The latency of the registers may be less than previously recorded,
996 depending on how they were used previously.
997 See Table 13-8 in the LSI. */
1000 if (use_is_gr_complex (cpu, in_GRj))
1001 decrease_GR_busy (cpu, in_GRj, 1);
1005 if (use_is_media (cpu, out_FRk))
1006 decrease_FR_busy (cpu, out_FRk, 1);
1008 adjust_float_register_busy (cpu, -1, out_FRk, -1, 1);
1010 vliw_wait_for_GR (cpu, in_GRj);
1011 vliw_wait_for_FR (cpu, out_FRk);
1012 handle_resource_wait (cpu);
1013 load_wait_for_GR (cpu, in_GRj);
1014 load_wait_for_FR (cpu, out_FRk);
1015 trace_vliw_wait_cycles (cpu);
1019 /* The latency of FRk is 2 cycles. */
1020 cycles = idesc->timing->units[unit_num].done;
1021 update_FR_latency (cpu, out_FRk, cycles + 2);
1023 /* Mark this use of the register as NOT a floating point op. */
1024 fr500_reset_fr_flags (cpu, out_FRk);
1030 frvbf_model_fr500_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
1031 int unit_num, int referenced,
1032 INT in_GRj, INT out_spr)
1036 if (model_insn == FRV_INSN_MODEL_PASS_1)
1038 /* The entire VLIW insn must wait if there is a dependency on a register
1039 which is not ready yet.
1040 The latency of the registers may be less than previously recorded,
1041 depending on how they were used previously.
1042 See Table 13-8 in the LSI. */
1045 if (use_is_gr_complex (cpu, in_GRj))
1046 decrease_GR_busy (cpu, in_GRj, 1);
1048 vliw_wait_for_GR (cpu, in_GRj);
1049 handle_resource_wait (cpu);
1050 load_wait_for_GR (cpu, in_GRj);
1051 trace_vliw_wait_cycles (cpu);
1055 cycles = idesc->timing->units[unit_num].done;
1058 /* The latency of spr is ? cycles. */
1059 update_SPR_latency (cpu, out_spr, cycles + ?);
1066 frvbf_model_fr500_u_ici (SIM_CPU *cpu, const IDESC *idesc,
1067 int unit_num, int referenced,
1068 INT in_GRi, INT in_GRj)
1072 if (model_insn == FRV_INSN_MODEL_PASS_1)
1074 /* The entire VLIW insn must wait if there is a dependency on a register
1075 which is not ready yet.
1076 The latency of the registers may be less than previously recorded,
1077 depending on how they were used previously.
1078 See Table 13-8 in the LSI. */
1081 if (use_is_gr_complex (cpu, in_GRi))
1082 decrease_GR_busy (cpu, in_GRi, 1);
1084 if (in_GRj != in_GRi && in_GRj >= 0)
1086 if (use_is_gr_complex (cpu, in_GRj))
1087 decrease_GR_busy (cpu, in_GRj, 1);
1089 vliw_wait_for_GR (cpu, in_GRi);
1090 vliw_wait_for_GR (cpu, in_GRj);
1091 handle_resource_wait (cpu);
1092 load_wait_for_GR (cpu, in_GRi);
1093 load_wait_for_GR (cpu, in_GRj);
1094 trace_vliw_wait_cycles (cpu);
1098 cycles = idesc->timing->units[unit_num].done;
1099 request_cache_invalidate (cpu, CPU_INSN_CACHE (cpu), cycles);
1104 frvbf_model_fr500_u_dci (SIM_CPU *cpu, const IDESC *idesc,
1105 int unit_num, int referenced,
1106 INT in_GRi, INT in_GRj)
1110 if (model_insn == FRV_INSN_MODEL_PASS_1)
1112 /* The entire VLIW insn must wait if there is a dependency on a register
1113 which is not ready yet.
1114 The latency of the registers may be less than previously recorded,
1115 depending on how they were used previously.
1116 See Table 13-8 in the LSI. */
1119 if (use_is_gr_complex (cpu, in_GRi))
1120 decrease_GR_busy (cpu, in_GRi, 1);
1122 if (in_GRj != in_GRi && in_GRj >= 0)
1124 if (use_is_gr_complex (cpu, in_GRj))
1125 decrease_GR_busy (cpu, in_GRj, 1);
1127 vliw_wait_for_GR (cpu, in_GRi);
1128 vliw_wait_for_GR (cpu, in_GRj);
1129 handle_resource_wait (cpu);
1130 load_wait_for_GR (cpu, in_GRi);
1131 load_wait_for_GR (cpu, in_GRj);
1132 trace_vliw_wait_cycles (cpu);
1136 cycles = idesc->timing->units[unit_num].done;
1137 request_cache_invalidate (cpu, CPU_DATA_CACHE (cpu), cycles);
1142 frvbf_model_fr500_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
1143 int unit_num, int referenced,
1144 INT in_GRi, INT in_GRj)
1148 if (model_insn == FRV_INSN_MODEL_PASS_1)
1150 /* The entire VLIW insn must wait if there is a dependency on a register
1151 which is not ready yet.
1152 The latency of the registers may be less than previously recorded,
1153 depending on how they were used previously.
1154 See Table 13-8 in the LSI. */
1157 if (use_is_gr_complex (cpu, in_GRi))
1158 decrease_GR_busy (cpu, in_GRi, 1);
1160 if (in_GRj != in_GRi && in_GRj >= 0)
1162 if (use_is_gr_complex (cpu, in_GRj))
1163 decrease_GR_busy (cpu, in_GRj, 1);
1165 vliw_wait_for_GR (cpu, in_GRi);
1166 vliw_wait_for_GR (cpu, in_GRj);
1167 handle_resource_wait (cpu);
1168 load_wait_for_GR (cpu, in_GRi);
1169 load_wait_for_GR (cpu, in_GRj);
1170 trace_vliw_wait_cycles (cpu);
1174 cycles = idesc->timing->units[unit_num].done;
1175 request_cache_flush (cpu, CPU_DATA_CACHE (cpu), cycles);
1180 frvbf_model_fr500_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
1181 int unit_num, int referenced,
1182 INT in_GRi, INT in_GRj)
1186 if (model_insn == FRV_INSN_MODEL_PASS_1)
1188 /* The entire VLIW insn must wait if there is a dependency on a register
1189 which is not ready yet.
1190 The latency of the registers may be less than previously recorded,
1191 depending on how they were used previously.
1192 See Table 13-8 in the LSI. */
1195 if (use_is_gr_complex (cpu, in_GRi))
1196 decrease_GR_busy (cpu, in_GRi, 1);
1198 if (in_GRj != in_GRi && in_GRj >= 0)
1200 if (use_is_gr_complex (cpu, in_GRj))
1201 decrease_GR_busy (cpu, in_GRj, 1);
1203 vliw_wait_for_GR (cpu, in_GRi);
1204 vliw_wait_for_GR (cpu, in_GRj);
1205 handle_resource_wait (cpu);
1206 load_wait_for_GR (cpu, in_GRi);
1207 load_wait_for_GR (cpu, in_GRj);
1208 trace_vliw_wait_cycles (cpu);
1212 cycles = idesc->timing->units[unit_num].done;
1213 request_cache_preload (cpu, CPU_INSN_CACHE (cpu), cycles);
1218 frvbf_model_fr500_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
1219 int unit_num, int referenced,
1220 INT in_GRi, INT in_GRj)
1224 if (model_insn == FRV_INSN_MODEL_PASS_1)
1226 /* The entire VLIW insn must wait if there is a dependency on a register
1227 which is not ready yet.
1228 The latency of the registers may be less than previously recorded,
1229 depending on how they were used previously.
1230 See Table 13-8 in the LSI. */
1233 if (use_is_gr_complex (cpu, in_GRi))
1234 decrease_GR_busy (cpu, in_GRi, 1);
1236 if (in_GRj != in_GRi && in_GRj >= 0)
1238 if (use_is_gr_complex (cpu, in_GRj))
1239 decrease_GR_busy (cpu, in_GRj, 1);
1241 vliw_wait_for_GR (cpu, in_GRi);
1242 vliw_wait_for_GR (cpu, in_GRj);
1243 handle_resource_wait (cpu);
1244 load_wait_for_GR (cpu, in_GRi);
1245 load_wait_for_GR (cpu, in_GRj);
1246 trace_vliw_wait_cycles (cpu);
1250 cycles = idesc->timing->units[unit_num].done;
1251 request_cache_preload (cpu, CPU_DATA_CACHE (cpu), cycles);
1256 frvbf_model_fr500_u_icul (SIM_CPU *cpu, const IDESC *idesc,
1257 int unit_num, int referenced,
1258 INT in_GRi, INT in_GRj)
1262 if (model_insn == FRV_INSN_MODEL_PASS_1)
1264 /* The entire VLIW insn must wait if there is a dependency on a register
1265 which is not ready yet.
1266 The latency of the registers may be less than previously recorded,
1267 depending on how they were used previously.
1268 See Table 13-8 in the LSI. */
1271 if (use_is_gr_complex (cpu, in_GRi))
1272 decrease_GR_busy (cpu, in_GRi, 1);
1274 if (in_GRj != in_GRi && in_GRj >= 0)
1276 if (use_is_gr_complex (cpu, in_GRj))
1277 decrease_GR_busy (cpu, in_GRj, 1);
1279 vliw_wait_for_GR (cpu, in_GRi);
1280 vliw_wait_for_GR (cpu, in_GRj);
1281 handle_resource_wait (cpu);
1282 load_wait_for_GR (cpu, in_GRi);
1283 load_wait_for_GR (cpu, in_GRj);
1284 trace_vliw_wait_cycles (cpu);
1288 cycles = idesc->timing->units[unit_num].done;
1289 request_cache_unlock (cpu, CPU_INSN_CACHE (cpu), cycles);
1294 frvbf_model_fr500_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
1295 int unit_num, int referenced,
1296 INT in_GRi, INT in_GRj)
1300 if (model_insn == FRV_INSN_MODEL_PASS_1)
1302 /* The entire VLIW insn must wait if there is a dependency on a register
1303 which is not ready yet.
1304 The latency of the registers may be less than previously recorded,
1305 depending on how they were used previously.
1306 See Table 13-8 in the LSI. */
1309 if (use_is_gr_complex (cpu, in_GRi))
1310 decrease_GR_busy (cpu, in_GRi, 1);
1312 if (in_GRj != in_GRi && in_GRj >= 0)
1314 if (use_is_gr_complex (cpu, in_GRj))
1315 decrease_GR_busy (cpu, in_GRj, 1);
1317 vliw_wait_for_GR (cpu, in_GRi);
1318 vliw_wait_for_GR (cpu, in_GRj);
1319 handle_resource_wait (cpu);
1320 load_wait_for_GR (cpu, in_GRi);
1321 load_wait_for_GR (cpu, in_GRj);
1322 trace_vliw_wait_cycles (cpu);
1326 cycles = idesc->timing->units[unit_num].done;
1327 request_cache_unlock (cpu, CPU_DATA_CACHE (cpu), cycles);
1331 /* Top up the post-processing time of the given FR by the given number of
1334 update_FR_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
1338 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
1339 /* If a load is pending on this register, then add the cycles to
1340 the post processing time for this register. Otherwise apply it
1341 directly to the latency of the register. */
1342 if (! load_pending_for_register (cpu, out_FR, 1, REGTYPE_FR))
1344 int *fr = ps->fr_latency;
1345 fr[out_FR] += cycles;
1348 ps->fr_ptime[out_FR] += cycles;
1353 update_FRdouble_ptime (SIM_CPU *cpu, INT out_FR, int cycles)
1357 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu);
1358 /* If a load is pending on this register, then add the cycles to
1359 the post processing time for this register. Otherwise apply it
1360 directly to the latency of the register. */
1361 if (! load_pending_for_register (cpu, out_FR, 2, REGTYPE_FR))
1363 int *fr = ps->fr_latency;
1364 fr[out_FR] += cycles;
1366 fr[out_FR + 1] += cycles;
1370 ps->fr_ptime[out_FR] += cycles;
1372 ps->fr_ptime[out_FR + 1] += cycles;
1378 frvbf_model_fr500_u_float_arith (SIM_CPU *cpu, const IDESC *idesc,
1379 int unit_num, int referenced,
1380 INT in_FRi, INT in_FRj,
1381 INT in_FRdoublei, INT in_FRdoublej,
1382 INT out_FRk, INT out_FRdoublek)
1385 FRV_PROFILE_STATE *ps;
1387 if (model_insn == FRV_INSN_MODEL_PASS_1)
1390 /* The preprocessing can execute right away. */
1391 cycles = idesc->timing->units[unit_num].done;
1393 /* The post processing must wait if there is a dependency on a FR
1394 which is not ready yet. */
1395 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1396 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1398 ps = CPU_PROFILE_STATE (cpu);
1399 ps->post_wait = cycles;
1400 post_wait_for_FR (cpu, in_FRi);
1401 post_wait_for_FR (cpu, in_FRj);
1402 post_wait_for_FR (cpu, out_FRk);
1403 post_wait_for_FRdouble (cpu, in_FRdoublei);
1404 post_wait_for_FRdouble (cpu, in_FRdoublej);
1405 post_wait_for_FRdouble (cpu, out_FRdoublek);
1406 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1407 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1410 /* The latency of FRk will be at least the latency of the other inputs. */
1411 update_FR_latency (cpu, out_FRk, ps->post_wait);
1412 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1414 /* Once initiated, post-processing will take 3 cycles. */
1415 update_FR_ptime (cpu, out_FRk, 3);
1416 update_FRdouble_ptime (cpu, out_FRdoublek, 3);
1418 /* Mark this use of the register as a floating point op. */
1420 set_use_is_fpop (cpu, out_FRk);
1421 if (out_FRdoublek >= 0)
1423 set_use_is_fpop (cpu, out_FRdoublek);
1424 if (out_FRdoublek < 63)
1425 set_use_is_fpop (cpu, out_FRdoublek + 1);
1432 frvbf_model_fr500_u_float_dual_arith (SIM_CPU *cpu, const IDESC *idesc,
1433 int unit_num, int referenced,
1434 INT in_FRi, INT in_FRj,
1435 INT in_FRdoublei, INT in_FRdoublej,
1436 INT out_FRk, INT out_FRdoublek)
1445 FRV_PROFILE_STATE *ps;
1447 if (model_insn == FRV_INSN_MODEL_PASS_1)
1450 /* The preprocessing can execute right away. */
1451 cycles = idesc->timing->units[unit_num].done;
1453 /* The post processing must wait if there is a dependency on a FR
1454 which is not ready yet. */
1455 dual_FRi = DUAL_REG (in_FRi);
1456 dual_FRj = DUAL_REG (in_FRj);
1457 dual_FRk = DUAL_REG (out_FRk);
1458 dual_FRdoublei = DUAL_DOUBLE (in_FRdoublei);
1459 dual_FRdoublej = DUAL_DOUBLE (in_FRdoublej);
1460 dual_FRdoublek = DUAL_DOUBLE (out_FRdoublek);
1462 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1463 adjust_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1);
1464 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1466 adjust_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej,
1468 ps = CPU_PROFILE_STATE (cpu);
1469 ps->post_wait = cycles;
1470 post_wait_for_FR (cpu, in_FRi);
1471 post_wait_for_FR (cpu, in_FRj);
1472 post_wait_for_FR (cpu, out_FRk);
1473 post_wait_for_FR (cpu, dual_FRi);
1474 post_wait_for_FR (cpu, dual_FRj);
1475 post_wait_for_FR (cpu, dual_FRk);
1476 post_wait_for_FRdouble (cpu, in_FRdoublei);
1477 post_wait_for_FRdouble (cpu, in_FRdoublej);
1478 post_wait_for_FRdouble (cpu, out_FRdoublek);
1479 post_wait_for_FRdouble (cpu, dual_FRdoublei);
1480 post_wait_for_FRdouble (cpu, dual_FRdoublej);
1481 post_wait_for_FRdouble (cpu, dual_FRdoublek);
1482 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1483 restore_float_register_busy (cpu, dual_FRi, dual_FRj, dual_FRk, 1);
1484 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, out_FRdoublek,
1486 restore_double_register_busy (cpu, dual_FRdoublei, dual_FRdoublej,
1489 /* The latency of FRk will be at least the latency of the other inputs. */
1490 update_FR_latency (cpu, out_FRk, ps->post_wait);
1491 update_FR_latency (cpu, dual_FRk, ps->post_wait);
1492 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1493 update_FRdouble_latency (cpu, dual_FRdoublek, ps->post_wait);
1495 /* Once initiated, post-processing will take 3 cycles. */
1496 update_FR_ptime (cpu, out_FRk, 3);
1497 update_FR_ptime (cpu, dual_FRk, 3);
1498 update_FRdouble_ptime (cpu, out_FRdoublek, 3);
1499 update_FRdouble_ptime (cpu, dual_FRdoublek, 3);
1501 /* Mark this use of the register as a floating point op. */
1503 set_use_is_fpop (cpu, out_FRk);
1505 set_use_is_fpop (cpu, dual_FRk);
1506 if (out_FRdoublek >= 0)
1508 set_use_is_fpop (cpu, out_FRdoublek);
1509 if (out_FRdoublek < 63)
1510 set_use_is_fpop (cpu, out_FRdoublek + 1);
1512 if (dual_FRdoublek >= 0)
1514 set_use_is_fpop (cpu, dual_FRdoublek);
1515 if (dual_FRdoublek < 63)
1516 set_use_is_fpop (cpu, dual_FRdoublek + 1);
1523 frvbf_model_fr500_u_float_div (SIM_CPU *cpu, const IDESC *idesc,
1524 int unit_num, int referenced,
1525 INT in_FRi, INT in_FRj, INT out_FRk)
1530 FRV_PROFILE_STATE *ps;
1532 if (model_insn == FRV_INSN_MODEL_PASS_1)
1535 cycles = idesc->timing->units[unit_num].done;
1537 /* The post processing must wait if there is a dependency on a FR
1538 which is not ready yet. */
1539 adjust_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1540 ps = CPU_PROFILE_STATE (cpu);
1541 ps->post_wait = cycles;
1542 post_wait_for_FR (cpu, in_FRi);
1543 post_wait_for_FR (cpu, in_FRj);
1544 post_wait_for_FR (cpu, out_FRk);
1545 vliw = CPU_VLIW (cpu);
1546 slot = vliw->next_slot - 1;
1547 slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
1548 post_wait_for_fdiv (cpu, slot);
1549 restore_float_register_busy (cpu, in_FRi, in_FRj, out_FRk, 1);
1551 /* The latency of FRk will be at least the latency of the other inputs. */
1552 /* Once initiated, post-processing will take 10 cycles. */
1553 update_FR_latency (cpu, out_FRk, ps->post_wait);
1554 update_FR_ptime (cpu, out_FRk, 10);
1556 /* The latency of the fdiv unit will be at least the latency of the other
1557 inputs. Once initiated, post-processing will take 9 cycles. */
1558 update_fdiv_resource_latency (cpu, slot, ps->post_wait + 9);
1560 /* Mark this use of the register as a floating point op. */
1561 set_use_is_fpop (cpu, out_FRk);
1567 frvbf_model_fr500_u_float_sqrt (SIM_CPU *cpu, const IDESC *idesc,
1568 int unit_num, int referenced,
1569 INT in_FRj, INT in_FRdoublej,
1570 INT out_FRk, INT out_FRdoublek)
1575 FRV_PROFILE_STATE *ps;
1577 if (model_insn == FRV_INSN_MODEL_PASS_1)
1580 cycles = idesc->timing->units[unit_num].done;
1582 /* The post processing must wait if there is a dependency on a FR
1583 which is not ready yet. */
1584 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1585 adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1586 ps = CPU_PROFILE_STATE (cpu);
1587 ps->post_wait = cycles;
1588 post_wait_for_FR (cpu, in_FRj);
1589 post_wait_for_FR (cpu, out_FRk);
1590 post_wait_for_FRdouble (cpu, in_FRdoublej);
1591 post_wait_for_FRdouble (cpu, out_FRdoublek);
1592 vliw = CPU_VLIW (cpu);
1593 slot = vliw->next_slot - 1;
1594 slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
1595 post_wait_for_fsqrt (cpu, slot);
1596 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1597 restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1599 /* The latency of FRk will be at least the latency of the other inputs. */
1600 update_FR_latency (cpu, out_FRk, ps->post_wait);
1601 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1603 /* Once initiated, post-processing will take 15 cycles. */
1604 update_FR_ptime (cpu, out_FRk, 15);
1605 update_FRdouble_ptime (cpu, out_FRdoublek, 15);
1607 /* The latency of the sqrt unit will be the latency of the other
1608 inputs plus 14 cycles. */
1609 update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);
1611 /* Mark this use of the register as a floating point op. */
1613 set_use_is_fpop (cpu, out_FRk);
1614 if (out_FRdoublek >= 0)
1616 set_use_is_fpop (cpu, out_FRdoublek);
1617 if (out_FRdoublek < 63)
1618 set_use_is_fpop (cpu, out_FRdoublek + 1);
1625 frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU *cpu, const IDESC *idesc,
1626 int unit_num, int referenced,
1627 INT in_FRj, INT out_FRk)
1634 FRV_PROFILE_STATE *ps;
1636 if (model_insn == FRV_INSN_MODEL_PASS_1)
1639 cycles = idesc->timing->units[unit_num].done;
1641 /* The post processing must wait if there is a dependency on a FR
1642 which is not ready yet. */
1643 dual_FRj = DUAL_REG (in_FRj);
1644 dual_FRk = DUAL_REG (out_FRk);
1645 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1646 adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1647 ps = CPU_PROFILE_STATE (cpu);
1648 ps->post_wait = cycles;
1649 post_wait_for_FR (cpu, in_FRj);
1650 post_wait_for_FR (cpu, out_FRk);
1651 post_wait_for_FR (cpu, dual_FRj);
1652 post_wait_for_FR (cpu, dual_FRk);
1654 vliw = CPU_VLIW (cpu);
1655 slot = vliw->next_slot - 1;
1656 slot = (*vliw->current_vliw)[slot] - UNIT_FM0;
1657 post_wait_for_fsqrt (cpu, slot);
1658 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1659 restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1661 /* The latency of FRk will be at least the latency of the other inputs. */
1662 update_FR_latency (cpu, out_FRk, ps->post_wait);
1663 update_FR_latency (cpu, dual_FRk, ps->post_wait);
1665 /* Once initiated, post-processing will take 15 cycles. */
1666 update_FR_ptime (cpu, out_FRk, 15);
1667 update_FR_ptime (cpu, dual_FRk, 15);
1669 /* The latency of the sqrt unit will be at least the latency of the other
1671 update_fsqrt_resource_latency (cpu, slot, ps->post_wait + 14);
1673 /* Mark this use of the register as a floating point op. */
1675 set_use_is_fpop (cpu, out_FRk);
1677 set_use_is_fpop (cpu, dual_FRk);
1683 frvbf_model_fr500_u_float_compare (SIM_CPU *cpu, const IDESC *idesc,
1684 int unit_num, int referenced,
1685 INT in_FRi, INT in_FRj,
1686 INT in_FRdoublei, INT in_FRdoublej,
1690 FRV_PROFILE_STATE *ps;
1692 if (model_insn == FRV_INSN_MODEL_PASS_1)
1695 /* The preprocessing can execute right away. */
1696 cycles = idesc->timing->units[unit_num].done;
1698 /* The post processing must wait if there is a dependency on a FR
1699 which is not ready yet. */
1700 adjust_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1);
1701 ps = CPU_PROFILE_STATE (cpu);
1702 ps->post_wait = cycles;
1703 post_wait_for_FR (cpu, in_FRi);
1704 post_wait_for_FR (cpu, in_FRj);
1705 post_wait_for_FRdouble (cpu, in_FRdoublei);
1706 post_wait_for_FRdouble (cpu, in_FRdoublej);
1707 post_wait_for_CCR (cpu, out_FCCi_2);
1708 restore_double_register_busy (cpu, in_FRdoublei, in_FRdoublej, -1, 1);
1710 /* The latency of FCCi_2 will be the latency of the other inputs plus 3
1712 update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);
1718 frvbf_model_fr500_u_float_dual_compare (SIM_CPU *cpu, const IDESC *idesc,
1719 int unit_num, int referenced,
1720 INT in_FRi, INT in_FRj,
1727 FRV_PROFILE_STATE *ps;
1729 if (model_insn == FRV_INSN_MODEL_PASS_1)
1732 /* The preprocessing can execute right away. */
1733 cycles = idesc->timing->units[unit_num].done;
1735 /* The post processing must wait if there is a dependency on a FR
1736 which is not ready yet. */
1737 ps = CPU_PROFILE_STATE (cpu);
1738 ps->post_wait = cycles;
1739 dual_FRi = DUAL_REG (in_FRi);
1740 dual_FRj = DUAL_REG (in_FRj);
1741 dual_FCCi_2 = out_FCCi_2 + 1;
1742 adjust_float_register_busy (cpu, in_FRi, in_FRj, -1, 1);
1743 adjust_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1);
1744 post_wait_for_FR (cpu, in_FRi);
1745 post_wait_for_FR (cpu, in_FRj);
1746 post_wait_for_FR (cpu, dual_FRi);
1747 post_wait_for_FR (cpu, dual_FRj);
1748 post_wait_for_CCR (cpu, out_FCCi_2);
1749 post_wait_for_CCR (cpu, dual_FCCi_2);
1750 restore_float_register_busy (cpu, in_FRi, in_FRj, -1, 1);
1751 restore_float_register_busy (cpu, dual_FRi, dual_FRj, -1, 1);
1753 /* The latency of FCCi_2 will be the latency of the other inputs plus 3
1755 update_CCR_latency (cpu, out_FCCi_2, ps->post_wait + 3);
1756 update_CCR_latency (cpu, dual_FCCi_2, ps->post_wait + 3);
1762 frvbf_model_fr500_u_float_convert (SIM_CPU *cpu, const IDESC *idesc,
1763 int unit_num, int referenced,
1764 INT in_FRj, INT in_FRintj, INT in_FRdoublej,
1765 INT out_FRk, INT out_FRintk,
1769 FRV_PROFILE_STATE *ps;
1771 if (model_insn == FRV_INSN_MODEL_PASS_1)
1774 /* The preprocessing can execute right away. */
1775 cycles = idesc->timing->units[unit_num].done;
1777 /* The post processing must wait if there is a dependency on a FR
1778 which is not ready yet. */
1779 ps = CPU_PROFILE_STATE (cpu);
1780 ps->post_wait = cycles;
1781 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1782 adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1783 adjust_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1784 post_wait_for_FR (cpu, in_FRj);
1785 post_wait_for_FR (cpu, in_FRintj);
1786 post_wait_for_FRdouble (cpu, in_FRdoublej);
1787 post_wait_for_FR (cpu, out_FRk);
1788 post_wait_for_FR (cpu, out_FRintk);
1789 post_wait_for_FRdouble (cpu, out_FRdoublek);
1790 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1791 restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1792 restore_double_register_busy (cpu, -1, in_FRdoublej, out_FRdoublek, 1);
1794 /* The latency of FRk will be at least the latency of the other inputs. */
1795 update_FR_latency (cpu, out_FRk, ps->post_wait);
1796 update_FR_latency (cpu, out_FRintk, ps->post_wait);
1797 update_FRdouble_latency (cpu, out_FRdoublek, ps->post_wait);
1799 /* Once initiated, post-processing will take 3 cycles. */
1800 update_FR_ptime (cpu, out_FRk, 3);
1801 update_FR_ptime (cpu, out_FRintk, 3);
1802 update_FRdouble_ptime (cpu, out_FRdoublek, 3);
1804 /* Mark this use of the register as a floating point op. */
1806 set_use_is_fpop (cpu, out_FRk);
1807 if (out_FRintk >= 0)
1808 set_use_is_fpop (cpu, out_FRintk);
1809 if (out_FRdoublek >= 0)
1811 set_use_is_fpop (cpu, out_FRdoublek);
1812 set_use_is_fpop (cpu, out_FRdoublek + 1);
1819 frvbf_model_fr500_u_float_dual_convert (SIM_CPU *cpu, const IDESC *idesc,
1820 int unit_num, int referenced,
1821 INT in_FRj, INT in_FRintj,
1822 INT out_FRk, INT out_FRintk)
1829 FRV_PROFILE_STATE *ps;
1831 if (model_insn == FRV_INSN_MODEL_PASS_1)
1834 /* The preprocessing can execute right away. */
1835 cycles = idesc->timing->units[unit_num].done;
1837 /* The post processing must wait if there is a dependency on a FR
1838 which is not ready yet. */
1839 ps = CPU_PROFILE_STATE (cpu);
1840 ps->post_wait = cycles;
1841 dual_FRj = DUAL_REG (in_FRj);
1842 dual_FRintj = DUAL_REG (in_FRintj);
1843 dual_FRk = DUAL_REG (out_FRk);
1844 dual_FRintk = DUAL_REG (out_FRintk);
1845 adjust_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1846 adjust_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1847 adjust_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1848 adjust_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1);
1849 post_wait_for_FR (cpu, in_FRj);
1850 post_wait_for_FR (cpu, in_FRintj);
1851 post_wait_for_FR (cpu, out_FRk);
1852 post_wait_for_FR (cpu, out_FRintk);
1853 post_wait_for_FR (cpu, dual_FRj);
1854 post_wait_for_FR (cpu, dual_FRintj);
1855 post_wait_for_FR (cpu, dual_FRk);
1856 post_wait_for_FR (cpu, dual_FRintk);
1857 restore_float_register_busy (cpu, -1, in_FRj, out_FRk, 1);
1858 restore_float_register_busy (cpu, -1, dual_FRj, dual_FRk, 1);
1859 restore_float_register_busy (cpu, -1, in_FRintj, out_FRintk, 1);
1860 restore_float_register_busy (cpu, -1, dual_FRintj, dual_FRintk, 1);
1862 /* The latency of FRk will be at least the latency of the other inputs. */
1863 update_FR_latency (cpu, out_FRk, ps->post_wait);
1864 update_FR_latency (cpu, out_FRintk, ps->post_wait);
1865 update_FR_latency (cpu, dual_FRk, ps->post_wait);
1866 update_FR_latency (cpu, dual_FRintk, ps->post_wait);
1868 /* Once initiated, post-processing will take 3 cycles. */
1869 update_FR_ptime (cpu, out_FRk, 3);
1870 update_FR_ptime (cpu, out_FRintk, 3);
1871 update_FR_ptime (cpu, dual_FRk, 3);
1872 update_FR_ptime (cpu, dual_FRintk, 3);
1874 /* Mark this use of the register as a floating point op. */
1876 set_use_is_fpop (cpu, out_FRk);
1877 if (out_FRintk >= 0)
1878 set_use_is_fpop (cpu, out_FRintk);
1884 frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc,
1885 int unit_num, int referenced,
1886 INT in_FRi, INT in_FRj, INT in_ACC40Si, INT in_ACCGi,
1888 INT out_ACC40Sk, INT out_ACC40Uk, INT out_ACCGk)
1891 FRV_PROFILE_STATE *ps;
1892 const CGEN_INSN *insn;
1895 int busy_adjustment[] = {0, 0, 0};
1899 if (model_insn == FRV_INSN_MODEL_PASS_1)
1902 /* The preprocessing can execute right away. */
1903 cycles = idesc->timing->units[unit_num].done;
1905 ps = CPU_PROFILE_STATE (cpu);
1906 insn = idesc->idata;
1908 /* If the previous use of the registers was a media op,
1909 then their latency will be less than previously recorded.
1910 See Table 13-13 in the LSI. */
1913 if (use_is_media (cpu, in_FRi))
1915 busy_adjustment[0] = 2;
1916 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
1919 enforce_full_fr_latency (cpu, in_FRi);
1921 if (in_FRj >= 0 && in_FRj != in_FRi)
1923 if (use_is_media (cpu, in_FRj))
1925 busy_adjustment[1] = 2;
1926 decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
1929 enforce_full_fr_latency (cpu, in_FRj);
1931 if (out_FRk >= 0 && out_FRk != in_FRi && out_FRk != in_FRj)
1933 if (use_is_media (cpu, out_FRk))
1935 busy_adjustment[2] = 2;
1936 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
1939 enforce_full_fr_latency (cpu, out_FRk);
1942 /* The post processing must wait if there is a dependency on a FR
1943 which is not ready yet. */
1944 ps->post_wait = cycles;
1945 post_wait_for_FR (cpu, in_FRi);
1946 post_wait_for_FR (cpu, in_FRj);
1947 post_wait_for_FR (cpu, out_FRk);
1948 post_wait_for_ACC (cpu, in_ACC40Si);
1949 post_wait_for_ACC (cpu, in_ACCGi);
1950 post_wait_for_ACC (cpu, out_ACC40Sk);
1951 post_wait_for_ACC (cpu, out_ACC40Uk);
1952 post_wait_for_ACC (cpu, out_ACCGk);
1954 /* Restore the busy cycles of the registers we used. */
1957 fr[in_FRi] += busy_adjustment[0];
1959 fr[in_FRj] += busy_adjustment[1];
1961 fr[out_FRk] += busy_adjustment[2];
1963 /* The latency of tht output register will be at least the latency of the
1964 other inputs. Once initiated, post-processing will take 3 cycles. */
1967 update_FR_latency (cpu, out_FRk, ps->post_wait);
1968 update_FR_ptime (cpu, out_FRk, 3);
1969 /* Mark this use of the register as a media op. */
1970 set_use_is_media (cpu, out_FRk);
1972 /* The latency of tht output accumulator will be at least the latency of the
1973 other inputs. Once initiated, post-processing will take 1 cycle. */
1974 if (out_ACC40Sk >= 0)
1975 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
1976 if (out_ACC40Uk >= 0)
1977 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
1979 update_ACC_latency (cpu, out_ACCGk, ps->post_wait + 1);
1985 frvbf_model_fr500_u_media_quad_arith (SIM_CPU *cpu, const IDESC *idesc,
1986 int unit_num, int referenced,
1987 INT in_FRi, INT in_FRj,
1994 FRV_PROFILE_STATE *ps;
1995 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
1998 if (model_insn == FRV_INSN_MODEL_PASS_1)
2001 /* The preprocessing can execute right away. */
2002 cycles = idesc->timing->units[unit_num].done;
2004 ps = CPU_PROFILE_STATE (cpu);
2005 dual_FRi = DUAL_REG (in_FRi);
2006 dual_FRj = DUAL_REG (in_FRj);
2007 dual_FRk = DUAL_REG (out_FRk);
2009 /* If the previous use of the registers was a media op,
2010 then their latency will be less than previously recorded.
2011 See Table 13-13 in the LSI. */
2012 if (use_is_media (cpu, in_FRi))
2014 busy_adjustment[0] = 2;
2015 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2018 enforce_full_fr_latency (cpu, in_FRi);
2019 if (dual_FRi >= 0 && use_is_media (cpu, dual_FRi))
2021 busy_adjustment[1] = 2;
2022 decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]);
2025 enforce_full_fr_latency (cpu, dual_FRi);
2026 if (in_FRj != in_FRi)
2028 if (use_is_media (cpu, in_FRj))
2030 busy_adjustment[2] = 2;
2031 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
2034 enforce_full_fr_latency (cpu, in_FRj);
2035 if (dual_FRj >= 0 && use_is_media (cpu, dual_FRj))
2037 busy_adjustment[3] = 2;
2038 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]);
2041 enforce_full_fr_latency (cpu, dual_FRj + 1);
2043 if (out_FRk != in_FRi && out_FRk != in_FRj)
2045 if (use_is_media (cpu, out_FRk))
2047 busy_adjustment[4] = 2;
2048 decrease_FR_busy (cpu, out_FRk, busy_adjustment[4]);
2051 enforce_full_fr_latency (cpu, out_FRk);
2052 if (dual_FRk >= 0 && use_is_media (cpu, dual_FRk))
2054 busy_adjustment[5] = 2;
2055 decrease_FR_busy (cpu, dual_FRk, busy_adjustment[5]);
2058 enforce_full_fr_latency (cpu, dual_FRk);
2061 /* The post processing must wait if there is a dependency on a FR
2062 which is not ready yet. */
2063 ps->post_wait = cycles;
2064 post_wait_for_FR (cpu, in_FRi);
2065 post_wait_for_FR (cpu, dual_FRi);
2066 post_wait_for_FR (cpu, in_FRj);
2067 post_wait_for_FR (cpu, dual_FRj);
2068 post_wait_for_FR (cpu, out_FRk);
2069 post_wait_for_FR (cpu, dual_FRk);
2071 /* Restore the busy cycles of the registers we used. */
2073 fr[in_FRi] += busy_adjustment[0];
2075 fr[dual_FRi] += busy_adjustment[1];
2076 fr[in_FRj] += busy_adjustment[2];
2078 fr[dual_FRj] += busy_adjustment[3];
2079 fr[out_FRk] += busy_adjustment[4];
2081 fr[dual_FRk] += busy_adjustment[5];
2083 /* The latency of tht output register will be at least the latency of the
2085 update_FR_latency (cpu, out_FRk, ps->post_wait);
2087 /* Once initiated, post-processing will take 3 cycles. */
2088 update_FR_ptime (cpu, out_FRk, 3);
2090 /* Mark this use of the register as a media op. */
2091 set_use_is_media (cpu, out_FRk);
2094 update_FR_latency (cpu, dual_FRk, ps->post_wait);
2095 update_FR_ptime (cpu, dual_FRk, 3);
2096 /* Mark this use of the register as a media op. */
2097 set_use_is_media (cpu, dual_FRk);
2104 frvbf_model_fr500_u_media_dual_mul (SIM_CPU *cpu, const IDESC *idesc,
2105 int unit_num, int referenced,
2106 INT in_FRi, INT in_FRj,
2107 INT out_ACC40Sk, INT out_ACC40Uk)
2112 FRV_PROFILE_STATE *ps;
2113 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2117 if (model_insn == FRV_INSN_MODEL_PASS_1)
2120 /* The preprocessing can execute right away. */
2121 cycles = idesc->timing->units[unit_num].done;
2123 ps = CPU_PROFILE_STATE (cpu);
2124 dual_ACC40Sk = DUAL_REG (out_ACC40Sk);
2125 dual_ACC40Uk = DUAL_REG (out_ACC40Uk);
2127 /* If the previous use of the registers was a media op,
2128 then their latency will be less than previously recorded.
2129 See Table 13-13 in the LSI. */
2130 if (use_is_media (cpu, in_FRi))
2132 busy_adjustment[0] = 2;
2133 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2136 enforce_full_fr_latency (cpu, in_FRi);
2137 if (in_FRj != in_FRi)
2139 if (use_is_media (cpu, in_FRj))
2141 busy_adjustment[1] = 2;
2142 decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]);
2145 enforce_full_fr_latency (cpu, in_FRj);
2147 if (out_ACC40Sk >= 0)
2149 busy_adjustment[2] = 1;
2150 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]);
2152 if (dual_ACC40Sk >= 0)
2154 busy_adjustment[3] = 1;
2155 decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]);
2157 if (out_ACC40Uk >= 0)
2159 busy_adjustment[4] = 1;
2160 decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]);
2162 if (dual_ACC40Uk >= 0)
2164 busy_adjustment[5] = 1;
2165 decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]);
2168 /* The post processing must wait if there is a dependency on a FR
2169 which is not ready yet. */
2170 ps->post_wait = cycles;
2171 post_wait_for_FR (cpu, in_FRi);
2172 post_wait_for_FR (cpu, in_FRj);
2173 post_wait_for_ACC (cpu, out_ACC40Sk);
2174 post_wait_for_ACC (cpu, dual_ACC40Sk);
2175 post_wait_for_ACC (cpu, out_ACC40Uk);
2176 post_wait_for_ACC (cpu, dual_ACC40Uk);
2178 /* Restore the busy cycles of the registers we used. */
2181 fr[in_FRi] += busy_adjustment[0];
2182 fr[in_FRj] += busy_adjustment[1];
2183 if (out_ACC40Sk >= 0)
2184 acc[out_ACC40Sk] += busy_adjustment[2];
2185 if (dual_ACC40Sk >= 0)
2186 acc[dual_ACC40Sk] += busy_adjustment[3];
2187 if (out_ACC40Uk >= 0)
2188 acc[out_ACC40Uk] += busy_adjustment[4];
2189 if (dual_ACC40Uk >= 0)
2190 acc[dual_ACC40Uk] += busy_adjustment[5];
2192 /* The latency of tht output register will be at least the latency of the
2193 other inputs. Once initiated, post-processing will take 1 cycle. */
2194 if (out_ACC40Sk >= 0)
2195 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2196 if (dual_ACC40Sk >= 0)
2197 update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1);
2198 if (out_ACC40Uk >= 0)
2199 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
2200 if (dual_ACC40Uk >= 0)
2201 update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1);
2207 frvbf_model_fr500_u_media_quad_mul (SIM_CPU *cpu, const IDESC *idesc,
2208 int unit_num, int referenced,
2209 INT in_FRi, INT in_FRj,
2210 INT out_ACC40Sk, INT out_ACC40Uk)
2221 FRV_PROFILE_STATE *ps;
2222 int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0};
2226 if (model_insn == FRV_INSN_MODEL_PASS_1)
2229 /* The preprocessing can execute right away. */
2230 cycles = idesc->timing->units[unit_num].done;
2232 FRi_1 = DUAL_REG (in_FRi);
2233 FRj_1 = DUAL_REG (in_FRj);
2234 ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
2235 ACC40Sk_2 = DUAL_REG (ACC40Sk_1);
2236 ACC40Sk_3 = DUAL_REG (ACC40Sk_2);
2237 ACC40Uk_1 = DUAL_REG (out_ACC40Uk);
2238 ACC40Uk_2 = DUAL_REG (ACC40Uk_1);
2239 ACC40Uk_3 = DUAL_REG (ACC40Uk_2);
2241 /* If the previous use of the registers was a media op,
2242 then their latency will be less than previously recorded.
2243 See Table 13-13 in the LSI. */
2244 ps = CPU_PROFILE_STATE (cpu);
2245 if (use_is_media (cpu, in_FRi))
2247 busy_adjustment[0] = 2;
2248 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2251 enforce_full_fr_latency (cpu, in_FRi);
2254 if (use_is_media (cpu, FRi_1))
2256 busy_adjustment[1] = 2;
2257 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
2260 enforce_full_fr_latency (cpu, FRi_1);
2262 if (in_FRj != in_FRi)
2264 if (use_is_media (cpu, in_FRj))
2266 busy_adjustment[2] = 2;
2267 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
2270 enforce_full_fr_latency (cpu, in_FRj);
2273 if (use_is_media (cpu, FRj_1))
2275 busy_adjustment[3] = 2;
2276 decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]);
2279 enforce_full_fr_latency (cpu, FRj_1);
2282 if (out_ACC40Sk >= 0)
2284 busy_adjustment[4] = 1;
2285 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
2289 busy_adjustment[5] = 1;
2290 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
2294 busy_adjustment[6] = 1;
2295 decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]);
2299 busy_adjustment[7] = 1;
2300 decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]);
2303 else if (out_ACC40Uk >= 0)
2305 busy_adjustment[4] = 1;
2306 decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]);
2310 busy_adjustment[5] = 1;
2311 decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]);
2315 busy_adjustment[6] = 1;
2316 decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]);
2320 busy_adjustment[7] = 1;
2321 decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]);
2325 /* The post processing must wait if there is a dependency on a FR
2326 which is not ready yet. */
2327 ps->post_wait = cycles;
2328 post_wait_for_FR (cpu, in_FRi);
2329 post_wait_for_FR (cpu, FRi_1);
2330 post_wait_for_FR (cpu, in_FRj);
2331 post_wait_for_FR (cpu, FRj_1);
2332 post_wait_for_ACC (cpu, out_ACC40Sk);
2333 post_wait_for_ACC (cpu, ACC40Sk_1);
2334 post_wait_for_ACC (cpu, ACC40Sk_2);
2335 post_wait_for_ACC (cpu, ACC40Sk_3);
2336 post_wait_for_ACC (cpu, out_ACC40Uk);
2337 post_wait_for_ACC (cpu, ACC40Uk_1);
2338 post_wait_for_ACC (cpu, ACC40Uk_2);
2339 post_wait_for_ACC (cpu, ACC40Uk_3);
2341 /* Restore the busy cycles of the registers we used. */
2344 fr[in_FRi] += busy_adjustment[0];
2346 fr[FRi_1] += busy_adjustment[1];
2347 fr[in_FRj] += busy_adjustment[2];
2349 fr[FRj_1] += busy_adjustment[3];
2350 if (out_ACC40Sk >= 0)
2352 acc[out_ACC40Sk] += busy_adjustment[4];
2354 acc[ACC40Sk_1] += busy_adjustment[5];
2356 acc[ACC40Sk_2] += busy_adjustment[6];
2358 acc[ACC40Sk_3] += busy_adjustment[7];
2360 else if (out_ACC40Uk >= 0)
2362 acc[out_ACC40Uk] += busy_adjustment[4];
2364 acc[ACC40Uk_1] += busy_adjustment[5];
2366 acc[ACC40Uk_2] += busy_adjustment[6];
2368 acc[ACC40Uk_3] += busy_adjustment[7];
2371 /* The latency of tht output register will be at least the latency of the
2372 other inputs. Once initiated, post-processing will take 1 cycle. */
2373 if (out_ACC40Sk >= 0)
2375 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2377 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
2379 update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1);
2381 update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1);
2383 else if (out_ACC40Uk >= 0)
2385 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1);
2387 update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1);
2389 update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1);
2391 update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1);
2398 frvbf_model_fr500_u_media_quad_complex (SIM_CPU *cpu, const IDESC *idesc,
2399 int unit_num, int referenced,
2400 INT in_FRi, INT in_FRj,
2407 FRV_PROFILE_STATE *ps;
2408 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2412 if (model_insn == FRV_INSN_MODEL_PASS_1)
2415 /* The preprocessing can execute right away. */
2416 cycles = idesc->timing->units[unit_num].done;
2418 FRi_1 = DUAL_REG (in_FRi);
2419 FRj_1 = DUAL_REG (in_FRj);
2420 ACC40Sk_1 = DUAL_REG (out_ACC40Sk);
2422 /* If the previous use of the registers was a media op,
2423 then their latency will be less than previously recorded.
2424 See Table 13-13 in the LSI. */
2425 ps = CPU_PROFILE_STATE (cpu);
2426 if (use_is_media (cpu, in_FRi))
2428 busy_adjustment[0] = 2;
2429 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2432 enforce_full_fr_latency (cpu, in_FRi);
2435 if (use_is_media (cpu, FRi_1))
2437 busy_adjustment[1] = 2;
2438 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
2441 enforce_full_fr_latency (cpu, FRi_1);
2443 if (in_FRj != in_FRi)
2445 if (use_is_media (cpu, in_FRj))
2447 busy_adjustment[2] = 2;
2448 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]);
2451 enforce_full_fr_latency (cpu, in_FRj);
2454 if (use_is_media (cpu, FRj_1))
2456 busy_adjustment[3] = 2;
2457 decrease_FR_busy (cpu, FRj_1, busy_adjustment[3]);
2460 enforce_full_fr_latency (cpu, FRj_1);
2463 if (out_ACC40Sk >= 0)
2465 busy_adjustment[4] = 1;
2466 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]);
2470 busy_adjustment[5] = 1;
2471 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]);
2475 /* The post processing must wait if there is a dependency on a FR
2476 which is not ready yet. */
2477 ps->post_wait = cycles;
2478 post_wait_for_FR (cpu, in_FRi);
2479 post_wait_for_FR (cpu, FRi_1);
2480 post_wait_for_FR (cpu, in_FRj);
2481 post_wait_for_FR (cpu, FRj_1);
2482 post_wait_for_ACC (cpu, out_ACC40Sk);
2483 post_wait_for_ACC (cpu, ACC40Sk_1);
2485 /* Restore the busy cycles of the registers we used. */
2488 fr[in_FRi] += busy_adjustment[0];
2490 fr[FRi_1] += busy_adjustment[1];
2491 fr[in_FRj] += busy_adjustment[2];
2493 fr[FRj_1] += busy_adjustment[3];
2494 if (out_ACC40Sk >= 0)
2496 acc[out_ACC40Sk] += busy_adjustment[4];
2498 acc[ACC40Sk_1] += busy_adjustment[5];
2501 /* The latency of tht output register will be at least the latency of the
2502 other inputs. Once initiated, post-processing will take 1 cycle. */
2503 if (out_ACC40Sk >= 0)
2505 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1);
2507 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1);
2514 frvbf_model_fr500_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
2515 int unit_num, int referenced,
2521 FRV_PROFILE_STATE *ps;
2522 int busy_adjustment[] = {0, 0, 0};
2525 if (model_insn == FRV_INSN_MODEL_PASS_1)
2528 /* The preprocessing can execute right away. */
2529 cycles = idesc->timing->units[unit_num].done;
2531 /* If the previous use of the registers was a media op,
2532 then their latency will be less than previously recorded.
2533 See Table 13-13 in the LSI. */
2534 dual_FRk = DUAL_REG (out_FRk);
2535 ps = CPU_PROFILE_STATE (cpu);
2536 if (use_is_media (cpu, in_FRi))
2538 busy_adjustment[0] = 2;
2539 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2542 enforce_full_fr_latency (cpu, in_FRi);
2543 if (out_FRk != in_FRi)
2545 if (use_is_media (cpu, out_FRk))
2547 busy_adjustment[1] = 2;
2548 decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]);
2551 enforce_full_fr_latency (cpu, out_FRk);
2553 if (dual_FRk >= 0 && dual_FRk != in_FRi)
2555 if (use_is_media (cpu, dual_FRk))
2557 busy_adjustment[2] = 2;
2558 decrease_FR_busy (cpu, dual_FRk, busy_adjustment[2]);
2561 enforce_full_fr_latency (cpu, dual_FRk);
2564 /* The post processing must wait if there is a dependency on a FR
2565 which is not ready yet. */
2566 ps->post_wait = cycles;
2567 post_wait_for_FR (cpu, in_FRi);
2568 post_wait_for_FR (cpu, out_FRk);
2569 post_wait_for_FR (cpu, dual_FRk);
2571 /* Restore the busy cycles of the registers we used. */
2573 fr[in_FRi] += busy_adjustment[0];
2574 fr[out_FRk] += busy_adjustment[1];
2576 fr[dual_FRk] += busy_adjustment[2];
2578 /* The latency of tht output register will be at least the latency of the
2579 other inputs. Once initiated, post-processing will take 3 cycles. */
2580 update_FR_latency (cpu, out_FRk, ps->post_wait);
2581 update_FR_ptime (cpu, out_FRk, 3);
2583 /* Mark this use of the register as a media op. */
2584 set_use_is_media (cpu, out_FRk);
2587 update_FR_latency (cpu, dual_FRk, ps->post_wait);
2588 update_FR_ptime (cpu, dual_FRk, 3);
2590 /* Mark this use of the register as a media op. */
2591 set_use_is_media (cpu, dual_FRk);
2598 frvbf_model_fr500_u_media_dual_unpack (SIM_CPU *cpu, const IDESC *idesc,
2599 int unit_num, int referenced,
2608 FRV_PROFILE_STATE *ps;
2609 int busy_adjustment[] = {0, 0, 0, 0, 0, 0};
2612 if (model_insn == FRV_INSN_MODEL_PASS_1)
2615 /* The preprocessing can execute right away. */
2616 cycles = idesc->timing->units[unit_num].done;
2618 FRi_1 = DUAL_REG (in_FRi);
2619 FRk_1 = DUAL_REG (out_FRk);
2620 FRk_2 = DUAL_REG (FRk_1);
2621 FRk_3 = DUAL_REG (FRk_2);
2623 /* If the previous use of the registers was a media op,
2624 then their latency will be less than previously recorded.
2625 See Table 13-13 in the LSI. */
2626 ps = CPU_PROFILE_STATE (cpu);
2627 if (use_is_media (cpu, in_FRi))
2629 busy_adjustment[0] = 2;
2630 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]);
2633 enforce_full_fr_latency (cpu, in_FRi);
2634 if (FRi_1 >= 0 && use_is_media (cpu, FRi_1))
2636 busy_adjustment[1] = 2;
2637 decrease_FR_busy (cpu, FRi_1, busy_adjustment[1]);
2640 enforce_full_fr_latency (cpu, FRi_1);
2641 if (out_FRk != in_FRi)
2643 if (use_is_media (cpu, out_FRk))
2645 busy_adjustment[2] = 2;
2646 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
2649 enforce_full_fr_latency (cpu, out_FRk);
2650 if (FRk_1 >= 0 && FRk_1 != in_FRi)
2652 if (use_is_media (cpu, FRk_1))
2654 busy_adjustment[3] = 2;
2655 decrease_FR_busy (cpu, FRk_1, busy_adjustment[3]);
2658 enforce_full_fr_latency (cpu, FRk_1);
2660 if (FRk_2 >= 0 && FRk_2 != in_FRi)
2662 if (use_is_media (cpu, FRk_2))
2664 busy_adjustment[4] = 2;
2665 decrease_FR_busy (cpu, FRk_2, busy_adjustment[4]);
2668 enforce_full_fr_latency (cpu, FRk_2);
2670 if (FRk_3 >= 0 && FRk_3 != in_FRi)
2672 if (use_is_media (cpu, FRk_3))
2674 busy_adjustment[5] = 2;
2675 decrease_FR_busy (cpu, FRk_3, busy_adjustment[5]);
2678 enforce_full_fr_latency (cpu, FRk_3);
2682 /* The post processing must wait if there is a dependency on a FR
2683 which is not ready yet. */
2684 ps->post_wait = cycles;
2685 post_wait_for_FR (cpu, in_FRi);
2686 post_wait_for_FR (cpu, FRi_1);
2687 post_wait_for_FR (cpu, out_FRk);
2688 post_wait_for_FR (cpu, FRk_1);
2689 post_wait_for_FR (cpu, FRk_2);
2690 post_wait_for_FR (cpu, FRk_3);
2692 /* Restore the busy cycles of the registers we used. */
2694 fr[in_FRi] += busy_adjustment[0];
2696 fr[FRi_1] += busy_adjustment[1];
2697 fr[out_FRk] += busy_adjustment[2];
2699 fr[FRk_1] += busy_adjustment[3];
2701 fr[FRk_2] += busy_adjustment[4];
2703 fr[FRk_3] += busy_adjustment[5];
2705 /* The latency of tht output register will be at least the latency of the
2706 other inputs. Once initiated, post-processing will take 3 cycles. */
2707 update_FR_latency (cpu, out_FRk, ps->post_wait);
2708 update_FR_ptime (cpu, out_FRk, 3);
2710 /* Mark this use of the register as a media op. */
2711 set_use_is_media (cpu, out_FRk);
2714 update_FR_latency (cpu, FRk_1, ps->post_wait);
2715 update_FR_ptime (cpu, FRk_1, 3);
2717 /* Mark this use of the register as a media op. */
2718 set_use_is_media (cpu, FRk_1);
2722 update_FR_latency (cpu, FRk_2, ps->post_wait);
2723 update_FR_ptime (cpu, FRk_2, 3);
2725 /* Mark this use of the register as a media op. */
2726 set_use_is_media (cpu, FRk_2);
2730 update_FR_latency (cpu, FRk_3, ps->post_wait);
2731 update_FR_ptime (cpu, FRk_3, 3);
2733 /* Mark this use of the register as a media op. */
2734 set_use_is_media (cpu, FRk_3);
2741 frvbf_model_fr500_u_media_dual_btoh (SIM_CPU *cpu, const IDESC *idesc,
2742 int unit_num, int referenced,
2746 return frvbf_model_fr500_u_media_dual_expand (cpu, idesc, unit_num,
2747 referenced, in_FRj, out_FRk);
2751 frvbf_model_fr500_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
2752 int unit_num, int referenced,
2758 FRV_PROFILE_STATE *ps;
2759 int busy_adjustment[] = {0, 0, 0};
2762 if (model_insn == FRV_INSN_MODEL_PASS_1)
2765 /* The preprocessing can execute right away. */
2766 cycles = idesc->timing->units[unit_num].done;
2768 /* If the previous use of the registers was a media op,
2769 then their latency will be less than previously recorded.
2770 See Table 13-13 in the LSI. */
2771 dual_FRj = DUAL_REG (in_FRj);
2772 ps = CPU_PROFILE_STATE (cpu);
2773 if (use_is_media (cpu, in_FRj))
2775 busy_adjustment[0] = 2;
2776 decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
2779 enforce_full_fr_latency (cpu, in_FRj);
2782 if (use_is_media (cpu, dual_FRj))
2784 busy_adjustment[1] = 2;
2785 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]);
2788 enforce_full_fr_latency (cpu, dual_FRj);
2790 if (out_FRk != in_FRj)
2792 if (use_is_media (cpu, out_FRk))
2794 busy_adjustment[2] = 2;
2795 decrease_FR_busy (cpu, out_FRk, busy_adjustment[2]);
2798 enforce_full_fr_latency (cpu, out_FRk);
2801 /* The post processing must wait if there is a dependency on a FR
2802 which is not ready yet. */
2803 ps->post_wait = cycles;
2804 post_wait_for_FR (cpu, in_FRj);
2805 post_wait_for_FR (cpu, dual_FRj);
2806 post_wait_for_FR (cpu, out_FRk);
2808 /* Restore the busy cycles of the registers we used. */
2810 fr[in_FRj] += busy_adjustment[0];
2812 fr[dual_FRj] += busy_adjustment[1];
2813 fr[out_FRk] += busy_adjustment[2];
2815 /* The latency of tht output register will be at least the latency of the
2817 update_FR_latency (cpu, out_FRk, ps->post_wait);
2819 /* Once initiated, post-processing will take 3 cycles. */
2820 update_FR_ptime (cpu, out_FRk, 3);
2822 /* Mark this use of the register as a media op. */
2823 set_use_is_media (cpu, out_FRk);
2829 frvbf_model_fr500_u_media_dual_btohe (SIM_CPU *cpu, const IDESC *idesc,
2830 int unit_num, int referenced,
2838 FRV_PROFILE_STATE *ps;
2839 int busy_adjustment[] = {0, 0, 0, 0, 0};
2842 if (model_insn == FRV_INSN_MODEL_PASS_1)
2845 /* The preprocessing can execute right away. */
2846 cycles = idesc->timing->units[unit_num].done;
2848 FRk_1 = DUAL_REG (out_FRk);
2849 FRk_2 = DUAL_REG (FRk_1);
2850 FRk_3 = DUAL_REG (FRk_2);
2852 /* If the previous use of the registers was a media op,
2853 then their latency will be less than previously recorded.
2854 See Table 13-13 in the LSI. */
2855 ps = CPU_PROFILE_STATE (cpu);
2856 if (use_is_media (cpu, in_FRj))
2858 busy_adjustment[0] = 2;
2859 decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]);
2862 enforce_full_fr_latency (cpu, in_FRj);
2863 if (out_FRk != in_FRj)
2865 if (use_is_media (cpu, out_FRk))
2867 busy_adjustment[1] = 2;
2868 decrease_FR_busy (cpu, out_FRk, busy_adjustment[1]);
2871 enforce_full_fr_latency (cpu, out_FRk);
2872 if (FRk_1 >= 0 && FRk_1 != in_FRj)
2874 if (use_is_media (cpu, FRk_1))
2876 busy_adjustment[2] = 2;
2877 decrease_FR_busy (cpu, FRk_1, busy_adjustment[2]);
2880 enforce_full_fr_latency (cpu, FRk_1);
2882 if (FRk_2 >= 0 && FRk_2 != in_FRj)
2884 if (use_is_media (cpu, FRk_2))
2886 busy_adjustment[3] = 2;
2887 decrease_FR_busy (cpu, FRk_2, busy_adjustment[3]);
2890 enforce_full_fr_latency (cpu, FRk_2);
2892 if (FRk_3 >= 0 && FRk_3 != in_FRj)
2894 if (use_is_media (cpu, FRk_3))
2896 busy_adjustment[4] = 2;
2897 decrease_FR_busy (cpu, FRk_3, busy_adjustment[4]);
2900 enforce_full_fr_latency (cpu, FRk_3);
2904 /* The post processing must wait if there is a dependency on a FR
2905 which is not ready yet. */
2906 ps->post_wait = cycles;
2907 post_wait_for_FR (cpu, in_FRj);
2908 post_wait_for_FR (cpu, out_FRk);
2909 post_wait_for_FR (cpu, FRk_1);
2910 post_wait_for_FR (cpu, FRk_2);
2911 post_wait_for_FR (cpu, FRk_3);
2913 /* Restore the busy cycles of the registers we used. */
2915 fr[in_FRj] += busy_adjustment[0];
2916 fr[out_FRk] += busy_adjustment[1];
2918 fr[FRk_1] += busy_adjustment[2];
2920 fr[FRk_2] += busy_adjustment[3];
2922 fr[FRk_3] += busy_adjustment[4];
2924 /* The latency of tht output register will be at least the latency of the
2925 other inputs. Once initiated, post-processing will take 3 cycles. */
2926 update_FR_latency (cpu, out_FRk, ps->post_wait);
2927 update_FR_ptime (cpu, out_FRk, 3);
2929 /* Mark this use of the register as a media op. */
2930 set_use_is_media (cpu, out_FRk);
2933 update_FR_latency (cpu, FRk_1, ps->post_wait);
2934 update_FR_ptime (cpu, FRk_1, 3);
2936 /* Mark this use of the register as a media op. */
2937 set_use_is_media (cpu, FRk_1);
2941 update_FR_latency (cpu, FRk_2, ps->post_wait);
2942 update_FR_ptime (cpu, FRk_2, 3);
2944 /* Mark this use of the register as a media op. */
2945 set_use_is_media (cpu, FRk_2);
2949 update_FR_latency (cpu, FRk_3, ps->post_wait);
2950 update_FR_ptime (cpu, FRk_3, 3);
2952 /* Mark this use of the register as a media op. */
2953 set_use_is_media (cpu, FRk_3);
2960 frvbf_model_fr500_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
2961 int unit_num, int referenced)
2964 if (model_insn == FRV_INSN_MODEL_PASS_1)
2967 /* Wait for ALL resources. */
2968 for (i = 0; i < 64; ++i)
2970 enforce_full_fr_latency (cpu, i);
2971 vliw_wait_for_GR (cpu, i);
2972 vliw_wait_for_FR (cpu, i);
2973 vliw_wait_for_ACC (cpu, i);
2975 for (i = 0; i < 8; ++i)
2976 vliw_wait_for_CCR (cpu, i);
2977 for (i = 0; i < 2; ++i)
2979 vliw_wait_for_idiv_resource (cpu, i);
2980 vliw_wait_for_fdiv_resource (cpu, i);
2981 vliw_wait_for_fsqrt_resource (cpu, i);
2983 handle_resource_wait (cpu);
2984 for (i = 0; i < 64; ++i)
2986 load_wait_for_GR (cpu, i);
2987 load_wait_for_FR (cpu, i);
2989 trace_vliw_wait_cycles (cpu);
2993 cycles = idesc->timing->units[unit_num].done;
2998 frvbf_model_fr500_u_membar (SIM_CPU *cpu, const IDESC *idesc,
2999 int unit_num, int referenced)
3002 if (model_insn == FRV_INSN_MODEL_PASS_1)
3005 /* Wait for ALL resources, except GR and ICC. */
3006 for (i = 0; i < 64; ++i)
3008 enforce_full_fr_latency (cpu, i);
3009 vliw_wait_for_FR (cpu, i);
3010 vliw_wait_for_ACC (cpu, i);
3012 for (i = 0; i < 4; ++i)
3013 vliw_wait_for_CCR (cpu, i);
3014 for (i = 0; i < 2; ++i)
3016 vliw_wait_for_idiv_resource (cpu, i);
3017 vliw_wait_for_fdiv_resource (cpu, i);
3018 vliw_wait_for_fsqrt_resource (cpu, i);
3020 handle_resource_wait (cpu);
3021 for (i = 0; i < 64; ++i)
3023 load_wait_for_FR (cpu, i);
3025 trace_vliw_wait_cycles (cpu);
3029 cycles = idesc->timing->units[unit_num].done;
3033 /* The frv machine is a fictional implementation of the fr500 which implements
3034 all frv architectural features. */
3036 frvbf_model_frv_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3037 int unit_num, int referenced)
3039 return idesc->timing->units[unit_num].done;
3042 /* The simple machine is a fictional implementation of the fr500 which
3043 implements limited frv architectural features. */
3045 frvbf_model_simple_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3046 int unit_num, int referenced)
3048 return idesc->timing->units[unit_num].done;
3051 /* The tomcat machine is models a prototype fr500 machine which had a few
3052 bugs and restrictions to work around. */
3054 frvbf_model_tomcat_u_exec (SIM_CPU *cpu, const IDESC *idesc,
3055 int unit_num, int referenced)
3057 return idesc->timing->units[unit_num].done;
3060 #endif /* WITH_PROFILE_MODEL_P */