1 /* frv simulator fr450 dependent profiling code.
3 Copyright (C) 2001, 2004, 2007 Free Software Foundation, Inc.
6 This file is part of the GNU simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License along
19 with this program; if not, write to the Free Software Foundation, Inc.,
20 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #define WANT_CPU_FRVBF
29 #if WITH_PROFILE_MODEL_P
32 #include "profile-fr400.h"
35 frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc,
36 int unit_num, int referenced)
38 return idesc->timing->units[unit_num].done;
42 frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc,
43 int unit_num, int referenced,
44 INT in_GRi, INT in_GRj, INT out_GRk,
47 /* Modelling for this unit is the same as for fr500. */
48 return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced,
49 in_GRi, in_GRj, out_GRk, out_ICCi_1);
53 frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc,
54 int unit_num, int referenced,
55 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
59 if (model_insn == FRV_INSN_MODEL_PASS_1)
61 /* Pass 1 is the same as for fr500. */
62 return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced,
63 in_GRi, in_GRj, out_GRk, out_ICCi_1);
66 /* icc0-icc4 are the upper 4 fields of the CCR. */
70 /* GRk and IACCi_1 have a latency of 1 cycle. */
71 cycles = idesc->timing->units[unit_num].done;
72 update_GRdouble_latency (cpu, out_GRk, cycles + 1);
73 update_CCR_latency (cpu, out_ICCi_1, cycles + 1);
79 frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
80 int unit_num, int referenced,
81 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
85 if (model_insn == FRV_INSN_MODEL_PASS_1)
87 /* Pass 1 is the same as for fr500. */
88 return frvbf_model_fr500_u_idiv (cpu, idesc, unit_num, referenced,
89 in_GRi, in_GRj, out_GRk, out_ICCi_1);
92 /* icc0-icc4 are the upper 4 fields of the CCR. */
96 /* GRk, ICCi_1 and the divider have a latency of 18 cycles */
97 cycles = idesc->timing->units[unit_num].done;
98 update_GR_latency (cpu, out_GRk, cycles + 18);
99 update_CCR_latency (cpu, out_ICCi_1, cycles + 18);
100 update_idiv_resource_latency (cpu, 0, cycles + 18);
106 frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc,
107 int unit_num, int referenced,
108 INT in_GRi, INT in_GRj,
109 INT in_ICCi_2, INT in_ICCi_3)
111 /* Modelling for this unit is the same as for fr400. */
112 return frvbf_model_fr400_u_branch (cpu, idesc, unit_num, referenced,
113 in_GRi, in_GRj, in_ICCi_2, in_ICCi_3);
117 frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc,
118 int unit_num, int referenced,
119 INT in_GRi, INT in_GRj,
120 INT in_ICCi_2, INT in_FCCi_2)
122 /* Modelling for this unit is the same as for fr500. */
123 return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced,
124 in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
128 frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc,
129 int unit_num, int referenced,
130 INT in_ICCi_3, INT in_FCCi_3)
132 /* Modelling for this unit is the same as for fr500. */
133 return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced,
134 in_ICCi_3, in_FCCi_3);
138 frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
139 int unit_num, int referenced,
140 INT out_GRkhi, INT out_GRklo)
142 /* Modelling for this unit is the same as for fr500. */
143 return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced,
144 out_GRkhi, out_GRklo);
148 frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
149 int unit_num, int referenced,
150 INT in_GRi, INT in_GRj,
151 INT out_GRk, INT out_GRdoublek)
155 if (model_insn == FRV_INSN_MODEL_PASS_1)
157 /* Pass 1 is the same as for fr500. */
158 return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced,
159 in_GRi, in_GRj, out_GRk,
163 cycles = idesc->timing->units[unit_num].done;
165 /* The latency of GRk for a load will depend on how long it takes to retrieve
166 the the data from the cache or memory. */
167 update_GR_latency_for_load (cpu, out_GRk, cycles);
168 update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
170 if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
172 /* GNER has a latency of 2 cycles. */
173 update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2);
174 update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2);
181 frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
182 int unit_num, int referenced,
183 INT in_GRi, INT in_GRj,
184 INT in_GRk, INT in_GRdoublek)
186 /* Modelling for this unit is the same as for fr500. */
187 return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced,
188 in_GRi, in_GRj, in_GRk, in_GRdoublek);
192 frvbf_model_fr450_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
193 int unit_num, int referenced,
194 INT in_GRi, INT in_GRj,
195 INT out_FRk, INT out_FRdoublek)
197 /* Modelling for this unit is the same as for fr400. */
198 return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced,
199 in_GRi, in_GRj, out_FRk, out_FRdoublek);
203 frvbf_model_fr450_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
204 int unit_num, int referenced,
205 INT in_GRi, INT in_GRj,
206 INT in_FRk, INT in_FRdoublek)
208 /* Modelling for this unit is the same as for fr400. */
209 return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced,
210 in_GRi, in_GRj, in_FRk, in_FRdoublek);
214 frvbf_model_fr450_u_swap (SIM_CPU *cpu, const IDESC *idesc,
215 int unit_num, int referenced,
216 INT in_GRi, INT in_GRj, INT out_GRk)
218 /* Modelling for this unit is the same as for fr500. */
219 return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced,
220 in_GRi, in_GRj, out_GRk);
224 frvbf_model_fr450_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
225 int unit_num, int referenced,
226 INT in_FRk, INT out_GRj)
230 if (model_insn == FRV_INSN_MODEL_PASS_1)
232 /* Pass 1 is the same as for fr400. */
233 return frvbf_model_fr500_u_fr2gr (cpu, idesc, unit_num, referenced,
237 /* The latency of GRj is 1 cycle. */
238 cycles = idesc->timing->units[unit_num].done;
239 update_GR_latency (cpu, out_GRj, cycles + 1);
245 frvbf_model_fr450_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
246 int unit_num, int referenced,
247 INT in_spr, INT out_GRj)
249 /* Modelling for this unit is the same as for fr500. */
250 return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced,
255 frvbf_model_fr450_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
256 int unit_num, int referenced,
257 INT in_GRj, INT out_FRk)
259 /* Modelling for this unit is the same as for fr400. */
260 return frvbf_model_fr400_u_gr2fr (cpu, idesc, unit_num, referenced,
265 frvbf_model_fr450_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
266 int unit_num, int referenced,
267 INT in_GRj, INT out_spr)
269 /* Modelling for this unit is the same as for fr500. */
270 return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced,
275 frvbf_model_fr450_u_media_1 (SIM_CPU *cpu, const IDESC *idesc,
276 int unit_num, int referenced,
277 INT in_FRi, INT in_FRj,
280 /* Modelling for this unit is the same as for fr400. */
281 return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced,
282 in_FRi, in_FRj, out_FRk);
286 frvbf_model_fr450_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc,
287 int unit_num, int referenced,
288 INT in_FRi, INT in_FRj,
291 /* Modelling for this unit is the same as for fr400. */
292 return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced,
293 in_FRi, in_FRj, out_FRk);
297 frvbf_model_fr450_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc,
298 int unit_num, int referenced,
299 INT out_FRkhi, INT out_FRklo)
301 /* Modelling for this unit is the same as for fr400. */
302 return frvbf_model_fr400_u_media_hilo (cpu, idesc, unit_num, referenced,
303 out_FRkhi, out_FRklo);
307 frvbf_model_fr450_u_media_2 (SIM_CPU *cpu, const IDESC *idesc,
308 int unit_num, int referenced,
309 INT in_FRi, INT in_FRj,
310 INT out_ACC40Sk, INT out_ACC40Uk)
312 /* Modelling for this unit is the same as for fr400. */
313 return frvbf_model_fr400_u_media_2 (cpu, idesc, unit_num, referenced,
314 in_FRi, in_FRj, out_ACC40Sk,
319 frvbf_model_fr450_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc,
320 int unit_num, int referenced,
321 INT in_FRi, INT in_FRj,
322 INT out_ACC40Sk, INT out_ACC40Uk)
324 /* Modelling for this unit is the same as for fr400. */
325 return frvbf_model_fr400_u_media_2_quad (cpu, idesc, unit_num, referenced,
326 in_FRi, in_FRj, out_ACC40Sk,
331 frvbf_model_fr450_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc,
332 int unit_num, int referenced,
333 INT in_ACC40Si, INT out_ACC40Sk)
335 /* Modelling for this unit is the same as for fr400. */
336 return frvbf_model_fr400_u_media_2_acc (cpu, idesc, unit_num, referenced,
337 in_ACC40Si, out_ACC40Sk);
341 frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
342 int unit_num, int referenced,
343 INT in_ACC40Si, INT out_ACC40Sk)
345 /* Modelling for this unit is the same as for fr400. */
346 return frvbf_model_fr400_u_media_2_acc_dual (cpu, idesc, unit_num,
347 referenced, in_ACC40Si,
352 frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc,
353 int unit_num, int referenced,
354 INT in_ACC40Si, INT out_ACC40Sk)
356 /* Modelling for this unit is the same as for fr400. */
357 return frvbf_model_fr400_u_media_2_add_sub (cpu, idesc, unit_num,
358 referenced, in_ACC40Si,
363 frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc,
364 int unit_num, int referenced,
365 INT in_ACC40Si, INT out_ACC40Sk)
367 /* Modelling for this unit is the same as for fr400. */
368 return frvbf_model_fr400_u_media_2_add_sub_dual (cpu, idesc, unit_num,
369 referenced, in_ACC40Si,
374 frvbf_model_fr450_u_media_3 (SIM_CPU *cpu, const IDESC *idesc,
375 int unit_num, int referenced,
376 INT in_FRi, INT in_FRj,
379 /* Modelling is the same as media unit 1. */
380 return frvbf_model_fr450_u_media_1 (cpu, idesc, unit_num, referenced,
381 in_FRi, in_FRj, out_FRk);
385 frvbf_model_fr450_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc,
386 int unit_num, int referenced,
387 INT in_FRi, INT out_FRk)
389 /* Modelling for this unit is the same as for fr400. */
390 return frvbf_model_fr400_u_media_3_dual (cpu, idesc, unit_num, referenced,
395 frvbf_model_fr450_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc,
396 int unit_num, int referenced,
397 INT in_FRi, INT in_FRj,
400 /* Modelling is the same as media unit 1. */
401 return frvbf_model_fr450_u_media_1_quad (cpu, idesc, unit_num, referenced,
402 in_FRi, in_FRj, out_FRk);
406 frvbf_model_fr450_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
407 int unit_num, int referenced,
408 INT in_ACC40Si, INT in_FRj,
409 INT out_ACC40Sk, INT out_FRk)
411 /* Modelling for this unit is the same as for fr400. */
412 return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced,
414 out_ACC40Sk, out_FRk);
418 frvbf_model_fr450_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc,
419 int unit_num, int referenced,
420 INT in_ACCGi, INT in_FRinti,
421 INT out_ACCGk, INT out_FRintk)
423 /* Modelling is the same as media-4 unit except use accumulator guards
424 as input instead of accumulators. */
425 return frvbf_model_fr450_u_media_4 (cpu, idesc, unit_num, referenced,
427 out_ACCGk, out_FRintk);
431 frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
432 int unit_num, int referenced,
433 INT in_ACC40Si, INT out_FRk)
435 /* Modelling for this unit is the same as for fr400. */
436 return frvbf_model_fr400_u_media_4_acc_dual (cpu, idesc, unit_num,
437 referenced, in_ACC40Si,
442 frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *cpu, const IDESC *idesc,
443 int unit_num, int referenced)
447 FRV_PROFILE_STATE *ps;
449 if (model_insn == FRV_INSN_MODEL_PASS_1)
452 /* The preprocessing can execute right away. */
453 cycles = idesc->timing->units[unit_num].done;
455 ps = CPU_PROFILE_STATE (cpu);
457 /* The post processing must wait for any pending ACC writes. */
458 ps->post_wait = cycles;
459 for (acc = 0; acc < 4; acc++)
460 post_wait_for_ACC (cpu, acc);
461 for (acc = 8; acc < 12; acc++)
462 post_wait_for_ACC (cpu, acc);
464 for (acc = 0; acc < 4; acc++)
466 update_ACC_latency (cpu, acc, ps->post_wait);
467 update_ACC_ptime (cpu, acc, 2);
469 for (acc = 8; acc < 12; acc++)
471 update_ACC_latency (cpu, acc, ps->post_wait);
472 update_ACC_ptime (cpu, acc, 2);
479 frvbf_model_fr450_u_media_6 (SIM_CPU *cpu, const IDESC *idesc,
480 int unit_num, int referenced,
481 INT in_FRi, INT out_FRk)
483 /* Modelling for this unit is the same as for fr400. */
484 return frvbf_model_fr400_u_media_6 (cpu, idesc, unit_num, referenced,
489 frvbf_model_fr450_u_media_7 (SIM_CPU *cpu, const IDESC *idesc,
490 int unit_num, int referenced,
491 INT in_FRinti, INT in_FRintj,
494 /* Modelling for this unit is the same as for fr400. */
495 return frvbf_model_fr400_u_media_7 (cpu, idesc, unit_num, referenced,
496 in_FRinti, in_FRintj, out_FCCk);
500 frvbf_model_fr450_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
501 int unit_num, int referenced,
505 /* Modelling for this unit is the same as for fr400. */
506 return frvbf_model_fr400_u_media_dual_expand (cpu, idesc, unit_num,
507 referenced, in_FRi, out_FRk);
511 frvbf_model_fr450_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
512 int unit_num, int referenced,
516 /* Modelling for this unit is the same as for fr400. */
517 return frvbf_model_fr400_u_media_dual_htob (cpu, idesc, unit_num,
518 referenced, in_FRj, out_FRk);
522 frvbf_model_fr450_u_ici (SIM_CPU *cpu, const IDESC *idesc,
523 int unit_num, int referenced,
524 INT in_GRi, INT in_GRj)
526 /* Modelling for this unit is the same as for fr500. */
527 return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced,
532 frvbf_model_fr450_u_dci (SIM_CPU *cpu, const IDESC *idesc,
533 int unit_num, int referenced,
534 INT in_GRi, INT in_GRj)
536 /* Modelling for this unit is the same as for fr500. */
537 return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced,
542 frvbf_model_fr450_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
543 int unit_num, int referenced,
544 INT in_GRi, INT in_GRj)
546 /* Modelling for this unit is the same as for fr500. */
547 return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced,
552 frvbf_model_fr450_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
553 int unit_num, int referenced,
554 INT in_GRi, INT in_GRj)
556 /* Modelling for this unit is the same as for fr500. */
557 return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced,
562 frvbf_model_fr450_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
563 int unit_num, int referenced,
564 INT in_GRi, INT in_GRj)
566 /* Modelling for this unit is the same as for fr500. */
567 return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced,
572 frvbf_model_fr450_u_icul (SIM_CPU *cpu, const IDESC *idesc,
573 int unit_num, int referenced,
574 INT in_GRi, INT in_GRj)
576 /* Modelling for this unit is the same as for fr500. */
577 return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced,
582 frvbf_model_fr450_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
583 int unit_num, int referenced,
584 INT in_GRi, INT in_GRj)
586 /* Modelling for this unit is the same as for fr500. */
587 return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced,
592 frvbf_model_fr450_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
593 int unit_num, int referenced)
595 /* Modelling for this unit is the same as for fr500. */
596 return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced);
600 frvbf_model_fr450_u_membar (SIM_CPU *cpu, const IDESC *idesc,
601 int unit_num, int referenced)
603 /* Modelling for this unit is the same as for fr500. */
604 return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced);
607 #endif /* WITH_PROFILE_MODEL_P */