1 /* frv simulator support code
2 Copyright (C) 1998, 1999, 2000, 2001, 2003, 2004 Free Software
4 Contributed by Red Hat.
6 This file is part of the GNU simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License along
19 with this program; if not, write to the Free Software Foundation, Inc.,
20 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23 #define WANT_CPU_FRVBF
28 #include "cgen-engine.h"
31 #include "gdb/sim-frv.h"
34 /* Maintain a flag in order to know when to write the address of the next
35 VLIW instruction into the LR register. Used by JMPL. JMPIL, and CALL
37 int frvbf_write_next_vliw_addr_to_LR;
39 /* The contents of BUF are in target byte order. */
41 frvbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
43 if (SIM_FRV_GR0_REGNUM <= rn && rn <= SIM_FRV_GR63_REGNUM)
45 int hi_available, lo_available;
46 int grn = rn - SIM_FRV_GR0_REGNUM;
48 frv_gr_registers_available (current_cpu, &hi_available, &lo_available);
50 if ((grn < 32 && !lo_available) || (grn >= 32 && !hi_available))
53 SETTSI (buf, GET_H_GR (grn));
55 else if (SIM_FRV_FR0_REGNUM <= rn && rn <= SIM_FRV_FR63_REGNUM)
57 int hi_available, lo_available;
58 int frn = rn - SIM_FRV_FR0_REGNUM;
60 frv_fr_registers_available (current_cpu, &hi_available, &lo_available);
62 if ((frn < 32 && !lo_available) || (frn >= 32 && !hi_available))
65 SETTSI (buf, GET_H_FR (frn));
67 else if (rn == SIM_FRV_PC_REGNUM)
68 SETTSI (buf, GET_H_PC ());
69 else if (SIM_FRV_SPR0_REGNUM <= rn && rn <= SIM_FRV_SPR4095_REGNUM)
71 /* Make sure the register is implemented. */
72 FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
73 int spr = rn - SIM_FRV_SPR0_REGNUM;
74 if (! control->spr[spr].implemented)
76 SETTSI (buf, GET_H_SPR (spr));
80 SETTSI (buf, 0xdeadbeef);
87 /* The contents of BUF are in target byte order. */
90 frvbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
92 if (SIM_FRV_GR0_REGNUM <= rn && rn <= SIM_FRV_GR63_REGNUM)
94 int hi_available, lo_available;
95 int grn = rn - SIM_FRV_GR0_REGNUM;
97 frv_gr_registers_available (current_cpu, &hi_available, &lo_available);
99 if ((grn < 32 && !lo_available) || (grn >= 32 && !hi_available))
102 SET_H_GR (grn, GETTSI (buf));
104 else if (SIM_FRV_FR0_REGNUM <= rn && rn <= SIM_FRV_FR63_REGNUM)
106 int hi_available, lo_available;
107 int frn = rn - SIM_FRV_FR0_REGNUM;
109 frv_fr_registers_available (current_cpu, &hi_available, &lo_available);
111 if ((frn < 32 && !lo_available) || (frn >= 32 && !hi_available))
114 SET_H_FR (frn, GETTSI (buf));
116 else if (rn == SIM_FRV_PC_REGNUM)
117 SET_H_PC (GETTSI (buf));
118 else if (SIM_FRV_SPR0_REGNUM <= rn && rn <= SIM_FRV_SPR4095_REGNUM)
120 /* Make sure the register is implemented. */
121 FRV_REGISTER_CONTROL *control = CPU_REGISTER_CONTROL (current_cpu);
122 int spr = rn - SIM_FRV_SPR0_REGNUM;
123 if (! control->spr[spr].implemented)
125 SET_H_SPR (spr, GETTSI (buf));
133 /* Cover fns to access the general registers. */
135 frvbf_h_gr_get_handler (SIM_CPU *current_cpu, UINT gr)
137 frv_check_gr_access (current_cpu, gr);
138 return CPU (h_gr[gr]);
142 frvbf_h_gr_set_handler (SIM_CPU *current_cpu, UINT gr, USI newval)
144 frv_check_gr_access (current_cpu, gr);
147 return; /* Storing into gr0 has no effect. */
149 CPU (h_gr[gr]) = newval;
152 /* Cover fns to access the floating point registers. */
154 frvbf_h_fr_get_handler (SIM_CPU *current_cpu, UINT fr)
156 frv_check_fr_access (current_cpu, fr);
157 return CPU (h_fr[fr]);
161 frvbf_h_fr_set_handler (SIM_CPU *current_cpu, UINT fr, SF newval)
163 frv_check_fr_access (current_cpu, fr);
164 CPU (h_fr[fr]) = newval;
167 /* Cover fns to access the general registers as double words. */
169 check_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask)
171 if (reg & align_mask)
173 SIM_DESC sd = CPU_STATE (current_cpu);
174 switch (STATE_ARCHITECTURE (sd)->mach)
176 /* Note: there is a discrepancy between V2.2 of the FR400
177 instruction manual and the various FR4xx LSI specs.
178 The former claims that unaligned registers cause a
179 register_exception while the latter say it's an
180 illegal_instruction. The LSI specs appear to be
181 correct; in fact, the FR4xx series is not documented
182 as having a register_exception. */
186 frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
188 case bfd_mach_frvtomcat:
191 frv_queue_register_exception_interrupt (current_cpu,
205 check_fr_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask)
207 if (reg & align_mask)
209 SIM_DESC sd = CPU_STATE (current_cpu);
210 switch (STATE_ARCHITECTURE (sd)->mach)
212 /* See comment in check_register_alignment(). */
216 frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
218 case bfd_mach_frvtomcat:
222 struct frv_fp_exception_info fp_info = {
223 FSR_NO_EXCEPTION, FTT_INVALID_FR
225 frv_queue_fp_exception_interrupt (current_cpu, & fp_info);
239 check_memory_alignment (SIM_CPU *current_cpu, SI address, int align_mask)
241 if (address & align_mask)
243 SIM_DESC sd = CPU_STATE (current_cpu);
244 switch (STATE_ARCHITECTURE (sd)->mach)
246 /* See comment in check_register_alignment(). */
249 frv_queue_data_access_error_interrupt (current_cpu, address);
251 case bfd_mach_frvtomcat:
254 frv_queue_mem_address_not_aligned_interrupt (current_cpu, address);
260 address &= ~align_mask;
267 frvbf_h_gr_double_get_handler (SIM_CPU *current_cpu, UINT gr)
272 return 0; /* gr0 is always 0. */
274 /* Check the register alignment. */
275 gr = check_register_alignment (current_cpu, gr, 1);
277 value = GET_H_GR (gr);
279 value |= (USI) GET_H_GR (gr + 1);
284 frvbf_h_gr_double_set_handler (SIM_CPU *current_cpu, UINT gr, DI newval)
287 return; /* Storing into gr0 has no effect. */
289 /* Check the register alignment. */
290 gr = check_register_alignment (current_cpu, gr, 1);
292 SET_H_GR (gr , (newval >> 32) & 0xffffffff);
293 SET_H_GR (gr + 1, (newval ) & 0xffffffff);
296 /* Cover fns to access the floating point register as double words. */
298 frvbf_h_fr_double_get_handler (SIM_CPU *current_cpu, UINT fr)
305 /* Check the register alignment. */
306 fr = check_fr_register_alignment (current_cpu, fr, 1);
308 if (CURRENT_HOST_BYTE_ORDER == LITTLE_ENDIAN)
310 value.as_sf[1] = GET_H_FR (fr);
311 value.as_sf[0] = GET_H_FR (fr + 1);
315 value.as_sf[0] = GET_H_FR (fr);
316 value.as_sf[1] = GET_H_FR (fr + 1);
323 frvbf_h_fr_double_set_handler (SIM_CPU *current_cpu, UINT fr, DF newval)
330 /* Check the register alignment. */
331 fr = check_fr_register_alignment (current_cpu, fr, 1);
333 value.as_df = newval;
334 if (CURRENT_HOST_BYTE_ORDER == LITTLE_ENDIAN)
336 SET_H_FR (fr , value.as_sf[1]);
337 SET_H_FR (fr + 1, value.as_sf[0]);
341 SET_H_FR (fr , value.as_sf[0]);
342 SET_H_FR (fr + 1, value.as_sf[1]);
346 /* Cover fns to access the floating point register as integer words. */
348 frvbf_h_fr_int_get_handler (SIM_CPU *current_cpu, UINT fr)
355 value.as_sf = GET_H_FR (fr);
360 frvbf_h_fr_int_set_handler (SIM_CPU *current_cpu, UINT fr, USI newval)
367 value.as_usi = newval;
368 SET_H_FR (fr, value.as_sf);
371 /* Cover fns to access the coprocessor registers as double words. */
373 frvbf_h_cpr_double_get_handler (SIM_CPU *current_cpu, UINT cpr)
377 /* Check the register alignment. */
378 cpr = check_register_alignment (current_cpu, cpr, 1);
380 value = GET_H_CPR (cpr);
382 value |= (USI) GET_H_CPR (cpr + 1);
387 frvbf_h_cpr_double_set_handler (SIM_CPU *current_cpu, UINT cpr, DI newval)
389 /* Check the register alignment. */
390 cpr = check_register_alignment (current_cpu, cpr, 1);
392 SET_H_CPR (cpr , (newval >> 32) & 0xffffffff);
393 SET_H_CPR (cpr + 1, (newval ) & 0xffffffff);
396 /* Cover fns to write registers as quad words. */
398 frvbf_h_gr_quad_set_handler (SIM_CPU *current_cpu, UINT gr, SI *newval)
401 return; /* Storing into gr0 has no effect. */
403 /* Check the register alignment. */
404 gr = check_register_alignment (current_cpu, gr, 3);
406 SET_H_GR (gr , newval[0]);
407 SET_H_GR (gr + 1, newval[1]);
408 SET_H_GR (gr + 2, newval[2]);
409 SET_H_GR (gr + 3, newval[3]);
413 frvbf_h_fr_quad_set_handler (SIM_CPU *current_cpu, UINT fr, SI *newval)
415 /* Check the register alignment. */
416 fr = check_fr_register_alignment (current_cpu, fr, 3);
418 SET_H_FR (fr , newval[0]);
419 SET_H_FR (fr + 1, newval[1]);
420 SET_H_FR (fr + 2, newval[2]);
421 SET_H_FR (fr + 3, newval[3]);
425 frvbf_h_cpr_quad_set_handler (SIM_CPU *current_cpu, UINT cpr, SI *newval)
427 /* Check the register alignment. */
428 cpr = check_register_alignment (current_cpu, cpr, 3);
430 SET_H_CPR (cpr , newval[0]);
431 SET_H_CPR (cpr + 1, newval[1]);
432 SET_H_CPR (cpr + 2, newval[2]);
433 SET_H_CPR (cpr + 3, newval[3]);
436 /* Cover fns to access the special purpose registers. */
438 frvbf_h_spr_get_handler (SIM_CPU *current_cpu, UINT spr)
440 /* Check access restrictions. */
441 frv_check_spr_read_access (current_cpu, spr);
446 return spr_psr_get_handler (current_cpu);
448 return spr_tbr_get_handler (current_cpu);
450 return spr_bpsr_get_handler (current_cpu);
452 return spr_ccr_get_handler (current_cpu);
454 return spr_cccr_get_handler (current_cpu);
459 return spr_sr_get_handler (current_cpu, spr);
462 return CPU (h_spr[spr]);
468 frvbf_h_spr_set_handler (SIM_CPU *current_cpu, UINT spr, USI newval)
470 FRV_REGISTER_CONTROL *control;
474 /* Check access restrictions. */
475 frv_check_spr_write_access (current_cpu, spr);
477 /* Only set those fields which are writeable. */
478 control = CPU_REGISTER_CONTROL (current_cpu);
479 mask = control->spr[spr].read_only_mask;
480 oldval = GET_H_SPR (spr);
482 newval = (newval & ~mask) | (oldval & mask);
484 /* Some registers are represented by individual components which are
485 referenced more often than the register itself. */
489 spr_psr_set_handler (current_cpu, newval);
492 spr_tbr_set_handler (current_cpu, newval);
495 spr_bpsr_set_handler (current_cpu, newval);
498 spr_ccr_set_handler (current_cpu, newval);
501 spr_cccr_set_handler (current_cpu, newval);
507 spr_sr_set_handler (current_cpu, spr, newval);
510 frv_cache_reconfigure (current_cpu, CPU_INSN_CACHE (current_cpu));
513 CPU (h_spr[spr]) = newval;
518 /* Cover fns to access the gr_hi and gr_lo registers. */
520 frvbf_h_gr_hi_get_handler (SIM_CPU *current_cpu, UINT gr)
522 return (GET_H_GR(gr) >> 16) & 0xffff;
526 frvbf_h_gr_hi_set_handler (SIM_CPU *current_cpu, UINT gr, UHI newval)
528 USI value = (GET_H_GR (gr) & 0xffff) | (newval << 16);
529 SET_H_GR (gr, value);
533 frvbf_h_gr_lo_get_handler (SIM_CPU *current_cpu, UINT gr)
535 return GET_H_GR(gr) & 0xffff;
539 frvbf_h_gr_lo_set_handler (SIM_CPU *current_cpu, UINT gr, UHI newval)
541 USI value = (GET_H_GR (gr) & 0xffff0000) | (newval & 0xffff);
542 SET_H_GR (gr, value);
545 /* Cover fns to access the tbr bits. */
547 spr_tbr_get_handler (SIM_CPU *current_cpu)
549 int tbr = ((GET_H_TBR_TBA () & 0xfffff) << 12) |
550 ((GET_H_TBR_TT () & 0xff) << 4);
556 spr_tbr_set_handler (SIM_CPU *current_cpu, USI newval)
560 SET_H_TBR_TBA ((tbr >> 12) & 0xfffff) ;
561 SET_H_TBR_TT ((tbr >> 4) & 0xff) ;
564 /* Cover fns to access the bpsr bits. */
566 spr_bpsr_get_handler (SIM_CPU *current_cpu)
568 int bpsr = ((GET_H_BPSR_BS () & 0x1) << 12) |
569 ((GET_H_BPSR_BET () & 0x1) );
575 spr_bpsr_set_handler (SIM_CPU *current_cpu, USI newval)
579 SET_H_BPSR_BS ((bpsr >> 12) & 1);
580 SET_H_BPSR_BET ((bpsr ) & 1);
583 /* Cover fns to access the psr bits. */
585 spr_psr_get_handler (SIM_CPU *current_cpu)
587 int psr = ((GET_H_PSR_IMPLE () & 0xf) << 28) |
588 ((GET_H_PSR_VER () & 0xf) << 24) |
589 ((GET_H_PSR_ICE () & 0x1) << 16) |
590 ((GET_H_PSR_NEM () & 0x1) << 14) |
591 ((GET_H_PSR_CM () & 0x1) << 13) |
592 ((GET_H_PSR_BE () & 0x1) << 12) |
593 ((GET_H_PSR_ESR () & 0x1) << 11) |
594 ((GET_H_PSR_EF () & 0x1) << 8) |
595 ((GET_H_PSR_EM () & 0x1) << 7) |
596 ((GET_H_PSR_PIL () & 0xf) << 3) |
597 ((GET_H_PSR_S () & 0x1) << 2) |
598 ((GET_H_PSR_PS () & 0x1) << 1) |
599 ((GET_H_PSR_ET () & 0x1) );
605 spr_psr_set_handler (SIM_CPU *current_cpu, USI newval)
607 /* The handler for PSR.S references the value of PSR.ESR, so set PSR.S
609 SET_H_PSR_S ((newval >> 2) & 1);
611 SET_H_PSR_IMPLE ((newval >> 28) & 0xf);
612 SET_H_PSR_VER ((newval >> 24) & 0xf);
613 SET_H_PSR_ICE ((newval >> 16) & 1);
614 SET_H_PSR_NEM ((newval >> 14) & 1);
615 SET_H_PSR_CM ((newval >> 13) & 1);
616 SET_H_PSR_BE ((newval >> 12) & 1);
617 SET_H_PSR_ESR ((newval >> 11) & 1);
618 SET_H_PSR_EF ((newval >> 8) & 1);
619 SET_H_PSR_EM ((newval >> 7) & 1);
620 SET_H_PSR_PIL ((newval >> 3) & 0xf);
621 SET_H_PSR_PS ((newval >> 1) & 1);
622 SET_H_PSR_ET ((newval ) & 1);
626 frvbf_h_psr_s_set_handler (SIM_CPU *current_cpu, BI newval)
628 /* If switching from user to supervisor mode, or vice-versa, then switch
629 the supervisor/user context. */
630 int psr_s = GET_H_PSR_S ();
631 if (psr_s != (newval & 1))
633 frvbf_switch_supervisor_user_context (current_cpu);
634 CPU (h_psr_s) = newval & 1;
638 /* Cover fns to access the ccr bits. */
640 spr_ccr_get_handler (SIM_CPU *current_cpu)
642 int ccr = ((GET_H_ICCR (H_ICCR_ICC3) & 0xf) << 28) |
643 ((GET_H_ICCR (H_ICCR_ICC2) & 0xf) << 24) |
644 ((GET_H_ICCR (H_ICCR_ICC1) & 0xf) << 20) |
645 ((GET_H_ICCR (H_ICCR_ICC0) & 0xf) << 16) |
646 ((GET_H_FCCR (H_FCCR_FCC3) & 0xf) << 12) |
647 ((GET_H_FCCR (H_FCCR_FCC2) & 0xf) << 8) |
648 ((GET_H_FCCR (H_FCCR_FCC1) & 0xf) << 4) |
649 ((GET_H_FCCR (H_FCCR_FCC0) & 0xf) );
655 spr_ccr_set_handler (SIM_CPU *current_cpu, USI newval)
659 SET_H_ICCR (H_ICCR_ICC3, (newval >> 28) & 0xf);
660 SET_H_ICCR (H_ICCR_ICC2, (newval >> 24) & 0xf);
661 SET_H_ICCR (H_ICCR_ICC1, (newval >> 20) & 0xf);
662 SET_H_ICCR (H_ICCR_ICC0, (newval >> 16) & 0xf);
663 SET_H_FCCR (H_FCCR_FCC3, (newval >> 12) & 0xf);
664 SET_H_FCCR (H_FCCR_FCC2, (newval >> 8) & 0xf);
665 SET_H_FCCR (H_FCCR_FCC1, (newval >> 4) & 0xf);
666 SET_H_FCCR (H_FCCR_FCC0, (newval ) & 0xf);
670 frvbf_set_icc_for_shift_right (
671 SIM_CPU *current_cpu, SI value, SI shift, QI icc
674 /* Set the C flag of the given icc to the logical OR of the bits shifted
676 int mask = (1 << shift) - 1;
677 if ((value & mask) != 0)
684 frvbf_set_icc_for_shift_left (
685 SIM_CPU *current_cpu, SI value, SI shift, QI icc
688 /* Set the V flag of the given icc to the logical OR of the bits shifted
690 int mask = ((1 << shift) - 1) << (32 - shift);
691 if ((value & mask) != 0)
697 /* Cover fns to access the cccr bits. */
699 spr_cccr_get_handler (SIM_CPU *current_cpu)
701 int cccr = ((GET_H_CCCR (H_CCCR_CC7) & 0x3) << 14) |
702 ((GET_H_CCCR (H_CCCR_CC6) & 0x3) << 12) |
703 ((GET_H_CCCR (H_CCCR_CC5) & 0x3) << 10) |
704 ((GET_H_CCCR (H_CCCR_CC4) & 0x3) << 8) |
705 ((GET_H_CCCR (H_CCCR_CC3) & 0x3) << 6) |
706 ((GET_H_CCCR (H_CCCR_CC2) & 0x3) << 4) |
707 ((GET_H_CCCR (H_CCCR_CC1) & 0x3) << 2) |
708 ((GET_H_CCCR (H_CCCR_CC0) & 0x3) );
714 spr_cccr_set_handler (SIM_CPU *current_cpu, USI newval)
718 SET_H_CCCR (H_CCCR_CC7, (newval >> 14) & 0x3);
719 SET_H_CCCR (H_CCCR_CC6, (newval >> 12) & 0x3);
720 SET_H_CCCR (H_CCCR_CC5, (newval >> 10) & 0x3);
721 SET_H_CCCR (H_CCCR_CC4, (newval >> 8) & 0x3);
722 SET_H_CCCR (H_CCCR_CC3, (newval >> 6) & 0x3);
723 SET_H_CCCR (H_CCCR_CC2, (newval >> 4) & 0x3);
724 SET_H_CCCR (H_CCCR_CC1, (newval >> 2) & 0x3);
725 SET_H_CCCR (H_CCCR_CC0, (newval ) & 0x3);
728 /* Cover fns to access the sr bits. */
730 spr_sr_get_handler (SIM_CPU *current_cpu, UINT spr)
732 /* If PSR.ESR is not set, then SR0-3 map onto SGR4-7 which will be GR4-7,
733 otherwise the correct mapping of USG4-7 or SGR4-7 will be in SR0-3. */
734 int psr_esr = GET_H_PSR_ESR ();
736 return GET_H_GR (4 + (spr - H_SPR_SR0));
738 return CPU (h_spr[spr]);
742 spr_sr_set_handler (SIM_CPU *current_cpu, UINT spr, USI newval)
744 /* If PSR.ESR is not set, then SR0-3 map onto SGR4-7 which will be GR4-7,
745 otherwise the correct mapping of USG4-7 or SGR4-7 will be in SR0-3. */
746 int psr_esr = GET_H_PSR_ESR ();
748 SET_H_GR (4 + (spr - H_SPR_SR0), newval);
750 CPU (h_spr[spr]) = newval;
753 /* Switch SR0-SR4 with GR4-GR7 if PSR.ESR is set. */
755 frvbf_switch_supervisor_user_context (SIM_CPU *current_cpu)
757 if (GET_H_PSR_ESR ())
759 /* We need to be in supervisor mode to swap the registers. Access the
760 PSR.S directly in order to avoid recursive context switches. */
762 int save_psr_s = CPU (h_psr_s);
764 for (i = 0; i < 4; ++i)
767 int spr = i + H_SPR_SR0;
768 SI tmp = GET_H_SPR (spr);
769 SET_H_SPR (spr, GET_H_GR (gr));
772 CPU (h_psr_s) = save_psr_s;
776 /* Handle load/store of quad registers. */
778 frvbf_load_quad_GR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI targ_ix)
783 /* Check memory alignment */
784 address = check_memory_alignment (current_cpu, address, 0xf);
786 /* If we need to count cycles, then the cache operation will be
787 initiated from the model profiling functions.
788 See frvbf_model_.... */
791 CPU_LOAD_ADDRESS (current_cpu) = address;
792 CPU_LOAD_LENGTH (current_cpu) = 16;
796 for (i = 0; i < 4; ++i)
798 value[i] = frvbf_read_mem_SI (current_cpu, pc, address);
801 sim_queue_fn_xi_write (current_cpu, frvbf_h_gr_quad_set_handler, targ_ix,
807 frvbf_store_quad_GR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI src_ix)
813 /* Check register and memory alignment. */
814 src_ix = check_register_alignment (current_cpu, src_ix, 3);
815 address = check_memory_alignment (current_cpu, address, 0xf);
817 for (i = 0; i < 4; ++i)
819 /* GR0 is always 0. */
823 value[i] = GET_H_GR (src_ix + i);
826 if (GET_HSR0_DCE (hsr0))
827 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value);
829 sim_queue_mem_xi_write (current_cpu, address, value);
833 frvbf_load_quad_FRint (SIM_CPU *current_cpu, PCADDR pc, SI address, SI targ_ix)
838 /* Check memory alignment */
839 address = check_memory_alignment (current_cpu, address, 0xf);
841 /* If we need to count cycles, then the cache operation will be
842 initiated from the model profiling functions.
843 See frvbf_model_.... */
846 CPU_LOAD_ADDRESS (current_cpu) = address;
847 CPU_LOAD_LENGTH (current_cpu) = 16;
851 for (i = 0; i < 4; ++i)
853 value[i] = frvbf_read_mem_SI (current_cpu, pc, address);
856 sim_queue_fn_xi_write (current_cpu, frvbf_h_fr_quad_set_handler, targ_ix,
862 frvbf_store_quad_FRint (SIM_CPU *current_cpu, PCADDR pc, SI address, SI src_ix)
868 /* Check register and memory alignment. */
869 src_ix = check_fr_register_alignment (current_cpu, src_ix, 3);
870 address = check_memory_alignment (current_cpu, address, 0xf);
872 for (i = 0; i < 4; ++i)
873 value[i] = GET_H_FR (src_ix + i);
876 if (GET_HSR0_DCE (hsr0))
877 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value);
879 sim_queue_mem_xi_write (current_cpu, address, value);
883 frvbf_load_quad_CPR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI targ_ix)
888 /* Check memory alignment */
889 address = check_memory_alignment (current_cpu, address, 0xf);
891 /* If we need to count cycles, then the cache operation will be
892 initiated from the model profiling functions.
893 See frvbf_model_.... */
896 CPU_LOAD_ADDRESS (current_cpu) = address;
897 CPU_LOAD_LENGTH (current_cpu) = 16;
901 for (i = 0; i < 4; ++i)
903 value[i] = frvbf_read_mem_SI (current_cpu, pc, address);
906 sim_queue_fn_xi_write (current_cpu, frvbf_h_cpr_quad_set_handler, targ_ix,
912 frvbf_store_quad_CPR (SIM_CPU *current_cpu, PCADDR pc, SI address, SI src_ix)
918 /* Check register and memory alignment. */
919 src_ix = check_register_alignment (current_cpu, src_ix, 3);
920 address = check_memory_alignment (current_cpu, address, 0xf);
922 for (i = 0; i < 4; ++i)
923 value[i] = GET_H_CPR (src_ix + i);
926 if (GET_HSR0_DCE (hsr0))
927 sim_queue_fn_mem_xi_write (current_cpu, frvbf_mem_set_XI, address, value);
929 sim_queue_mem_xi_write (current_cpu, address, value);
933 frvbf_signed_integer_divide (
934 SIM_CPU *current_cpu, SI arg1, SI arg2, int target_index, int non_excepting
937 enum frv_dtt dtt = FRV_DTT_NO_EXCEPTION;
938 if (arg1 == 0x80000000 && arg2 == -1)
940 /* 0x80000000/(-1) must result in 0x7fffffff when ISR.EDE is set
941 otherwise it may result in 0x7fffffff (sparc compatibility) or
942 0x80000000 (C language compatibility). */
944 dtt = FRV_DTT_OVERFLOW;
947 if (GET_ISR_EDE (isr))
948 sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, target_index,
951 sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, target_index,
953 frvbf_force_update (current_cpu); /* Force update of target register. */
956 dtt = FRV_DTT_DIVISION_BY_ZERO;
958 sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, target_index,
961 /* Check for exceptions. */
962 if (dtt != FRV_DTT_NO_EXCEPTION)
963 dtt = frvbf_division_exception (current_cpu, dtt, target_index,
965 if (non_excepting && dtt == FRV_DTT_NO_EXCEPTION)
967 /* Non excepting instruction. Clear the NE flag for the target
970 GET_NE_FLAGS (NE_flags, H_SPR_GNER0);
971 CLEAR_NE_FLAG (NE_flags, target_index);
972 SET_NE_FLAGS (H_SPR_GNER0, NE_flags);
977 frvbf_unsigned_integer_divide (
978 SIM_CPU *current_cpu, USI arg1, USI arg2, int target_index, int non_excepting
982 frvbf_division_exception (current_cpu, FRV_DTT_DIVISION_BY_ZERO,
983 target_index, non_excepting);
986 sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, target_index,
990 /* Non excepting instruction. Clear the NE flag for the target
993 GET_NE_FLAGS (NE_flags, H_SPR_GNER0);
994 CLEAR_NE_FLAG (NE_flags, target_index);
995 SET_NE_FLAGS (H_SPR_GNER0, NE_flags);
1000 /* Clear accumulators. */
1002 frvbf_clear_accumulators (SIM_CPU *current_cpu, SI acc_ix, int A)
1004 SIM_DESC sd = CPU_STATE (current_cpu);
1006 (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 7 :
1007 (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 7 :
1008 (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) ? 11 :
1009 (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 3 :
1011 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
1013 ps->mclracc_acc = acc_ix;
1015 if (A == 0 || acc_ix != 0) /* Clear 1 accumuator? */
1017 /* This instruction is a nop if the referenced accumulator is not
1019 if ((acc_ix & acc_mask) == acc_ix)
1020 sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, acc_ix, 0);
1024 /* Clear all implemented accumulators. */
1026 for (i = 0; i <= acc_mask; ++i)
1027 if ((i & acc_mask) == i)
1028 sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, i, 0);
1032 /* Functions to aid insn semantics. */
1034 /* Compute the result of the SCAN and SCANI insns after the shift and xor. */
1036 frvbf_scan_result (SIM_CPU *current_cpu, SI value)
1044 /* Find the position of the first non-zero bit.
1045 The loop will terminate since there is guaranteed to be at least one
1047 mask = 1 << (sizeof (mask) * 8 - 1);
1048 for (i = 0; (value & mask) == 0; ++i)
1054 /* Compute the result of the cut insns. */
1056 frvbf_cut (SIM_CPU *current_cpu, SI reg1, SI reg2, SI cut_point)
1061 result = reg1 << cut_point;
1062 result |= (reg2 >> (32 - cut_point)) & ((1 << cut_point) - 1);
1065 result = reg2 << (cut_point - 32);
1070 /* Compute the result of the cut insns. */
1072 frvbf_media_cut (SIM_CPU *current_cpu, DI acc, SI cut_point)
1074 /* The cut point is the lower 6 bits (signed) of what we are passed. */
1075 cut_point = cut_point << 26 >> 26;
1077 /* The cut_point is relative to bit 40 of 64 bits. */
1079 return (acc << (cut_point + 24)) >> 32;
1081 /* Extend the sign bit (bit 40) for negative cuts. */
1082 if (cut_point == -32)
1083 return (acc << 24) >> 63; /* Special case for full shiftout. */
1085 return (acc << 24) >> (32 + -cut_point);
1088 /* Compute the result of the cut insns. */
1090 frvbf_media_cut_ss (SIM_CPU *current_cpu, DI acc, SI cut_point)
1092 /* The cut point is the lower 6 bits (signed) of what we are passed. */
1093 cut_point = cut_point << 26 >> 26;
1097 /* The cut_point is relative to bit 40 of 64 bits. */
1098 DI shifted = acc << (cut_point + 24);
1099 DI unshifted = shifted >> (cut_point + 24);
1101 /* The result will be saturated if significant bits are shifted out. */
1102 if (unshifted != acc)
1110 /* The result will not be saturated, so use the code for the normal cut. */
1111 return frvbf_media_cut (current_cpu, acc, cut_point);
1114 /* Compute the result of int accumulator cut (SCUTSS). */
1116 frvbf_iacc_cut (SIM_CPU *current_cpu, DI acc, SI cut_point)
1120 /* The cut point is the lower 7 bits (signed) of what we are passed. */
1121 cut_point = cut_point << 25 >> 25;
1123 /* Conceptually, the operation is on a 128-bit sign-extension of ACC.
1124 The top bit of the return value corresponds to bit (63 - CUT_POINT)
1125 of this 128-bit value.
1127 Since we can't deal with 128-bit values very easily, convert the
1128 operation into an equivalent 64-bit one. */
1131 /* Avoid an undefined shift operation. */
1132 if (cut_point == -64)
1139 /* Get the shifted but unsaturated result. Set LOWER to the lowest
1140 32 bits of the result and UPPER to the result >> 31. */
1143 /* The cut loses the (32 - CUT_POINT) least significant bits.
1144 Round the result up if the most significant of these lost bits
1146 lower = acc >> (32 - cut_point);
1147 if (lower < 0x7fffffff)
1148 if (acc & LSBIT64 (32 - cut_point - 1))
1150 upper = lower >> 31;
1154 lower = acc << (cut_point - 32);
1155 upper = acc >> (63 - cut_point);
1158 /* Saturate the result. */
1167 /* Compute the result of shift-left-arithmetic-with-saturation (SLASS). */
1169 frvbf_shift_left_arith_saturate (SIM_CPU *current_cpu, SI arg1, SI arg2)
1173 /* FIXME: what to do with negative shift amt? */
1180 /* Signed shift by 31 or greater saturates by definition. */
1183 return (SI) 0x7fffffff;
1185 return (SI) 0x80000000;
1187 /* OK, arg2 is between 1 and 31. */
1188 neg_arg1 = (arg1 < 0);
1191 /* Check for sign bit change (saturation). */
1192 if (neg_arg1 && (arg1 >= 0))
1193 return (SI) 0x80000000;
1194 else if (!neg_arg1 && (arg1 < 0))
1195 return (SI) 0x7fffffff;
1196 } while (--arg2 > 0);
1201 /* Simulate the media custom insns. */
1203 frvbf_media_cop (SIM_CPU *current_cpu, int cop_num)
1205 /* The semantics of the insn are a nop, since it is implementation defined.
1206 We do need to check whether it's implemented and set up for MTRAP
1208 USI msr0 = GET_MSR (0);
1209 if (GET_MSR_EMCI (msr0) == 0)
1211 /* no interrupt queued at this time. */
1212 frv_set_mp_exception_registers (current_cpu, MTT_UNIMPLEMENTED_MPOP, 0);
1216 /* Simulate the media average (MAVEH) insn. */
1218 do_media_average (SIM_CPU *current_cpu, HI arg1, HI arg2)
1220 SIM_DESC sd = CPU_STATE (current_cpu);
1221 SI sum = (arg1 + arg2);
1222 HI result = sum >> 1;
1225 /* On fr4xx and fr550, check the rounding mode. On other machines
1226 rounding is always toward negative infinity and the result is
1227 already correctly rounded. */
1228 switch (STATE_ARCHITECTURE (sd)->mach)
1230 /* Need to check rounding mode. */
1231 case bfd_mach_fr400:
1232 case bfd_mach_fr450:
1233 case bfd_mach_fr550:
1234 /* Check whether rounding will be required. Rounding will be required
1235 if the sum is an odd number. */
1236 rounding_value = sum & 1;
1239 USI msr0 = GET_MSR (0);
1240 /* Check MSR0.SRDAV to determine which bits control the rounding. */
1241 if (GET_MSR_SRDAV (msr0))
1243 /* MSR0.RD controls rounding. */
1244 switch (GET_MSR_RD (msr0))
1247 /* Round to nearest. */
1252 /* Round toward 0. */
1257 /* Round toward positive infinity. */
1261 /* Round toward negative infinity. The result is already
1262 correctly rounded. */
1271 /* MSR0.RDAV controls rounding. If set, round toward positive
1272 infinity. Otherwise the result is already rounded correctly
1273 toward negative infinity. */
1274 if (GET_MSR_RDAV (msr0))
1287 frvbf_media_average (SIM_CPU *current_cpu, SI reg1, SI reg2)
1290 result = do_media_average (current_cpu, reg1 & 0xffff, reg2 & 0xffff);
1292 result |= do_media_average (current_cpu, (reg1 >> 16) & 0xffff,
1293 (reg2 >> 16) & 0xffff) << 16;
1297 /* Maintain a flag in order to know when to write the address of the next
1298 VLIW instruction into the LR register. Used by JMPL. JMPIL, and CALL. */
1300 frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU *current_cpu, int value)
1302 frvbf_write_next_vliw_addr_to_LR = value;
1306 frvbf_set_ne_index (SIM_CPU *current_cpu, int index)
1310 /* Save the target register so interrupt processing can set its NE flag
1311 in the event of an exception. */
1312 frv_interrupt_state.ne_index = index;
1314 /* Clear the NE flag of the target register. It will be reset if necessary
1315 in the event of an exception. */
1316 GET_NE_FLAGS (NE_flags, H_SPR_FNER0);
1317 CLEAR_NE_FLAG (NE_flags, index);
1318 SET_NE_FLAGS (H_SPR_FNER0, NE_flags);
1322 frvbf_force_update (SIM_CPU *current_cpu)
1324 CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (current_cpu);
1325 int ix = CGEN_WRITE_QUEUE_INDEX (q);
1328 CGEN_WRITE_QUEUE_ELEMENT *item = CGEN_WRITE_QUEUE_ELEMENT (q, ix - 1);
1329 item->flags |= FRV_WRITE_QUEUE_FORCE_WRITE;
1333 /* Condition code logic. */
1335 andcr, orcr, xorcr, nandcr, norcr, andncr, orncr, nandncr, norncr,
1339 enum cr_result {cr_undefined, cr_undefined1, cr_false, cr_true};
1341 static enum cr_result
1342 cr_logic[num_cr_ops][4][4] = {
1345 /* undefined undefined false true */
1346 /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
1347 /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
1348 /* false */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
1349 /* true */ {cr_undefined, cr_undefined, cr_false, cr_true }
1353 /* undefined undefined false true */
1354 /* undefined */ {cr_undefined, cr_undefined, cr_false, cr_true },
1355 /* undefined */ {cr_undefined, cr_undefined, cr_false, cr_true },
1356 /* false */ {cr_false, cr_false, cr_false, cr_true },
1357 /* true */ {cr_true, cr_true, cr_true, cr_true }
1361 /* undefined undefined false true */
1362 /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
1363 /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
1364 /* false */ {cr_undefined, cr_undefined, cr_false, cr_true },
1365 /* true */ {cr_true, cr_true, cr_true, cr_false }
1369 /* undefined undefined false true */
1370 /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
1371 /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
1372 /* false */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
1373 /* true */ {cr_undefined, cr_undefined, cr_true, cr_false }
1377 /* undefined undefined false true */
1378 /* undefined */ {cr_undefined, cr_undefined, cr_true, cr_false },
1379 /* undefined */ {cr_undefined, cr_undefined, cr_true, cr_false },
1380 /* false */ {cr_true, cr_true, cr_true, cr_false },
1381 /* true */ {cr_false, cr_false, cr_false, cr_false }
1385 /* undefined undefined false true */
1386 /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
1387 /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
1388 /* false */ {cr_undefined, cr_undefined, cr_false, cr_true },
1389 /* true */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}
1393 /* undefined undefined false true */
1394 /* undefined */ {cr_undefined, cr_undefined, cr_false, cr_true },
1395 /* undefined */ {cr_undefined, cr_undefined, cr_false, cr_true },
1396 /* false */ {cr_true, cr_true, cr_true, cr_true },
1397 /* true */ {cr_false, cr_false, cr_false, cr_true }
1401 /* undefined undefined false true */
1402 /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
1403 /* undefined */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined},
1404 /* false */ {cr_undefined, cr_undefined, cr_true, cr_false },
1405 /* true */ {cr_undefined, cr_undefined, cr_undefined, cr_undefined}
1409 /* undefined undefined false true */
1410 /* undefined */ {cr_undefined, cr_undefined, cr_true, cr_false },
1411 /* undefined */ {cr_undefined, cr_undefined, cr_true, cr_false },
1412 /* false */ {cr_false, cr_false, cr_false, cr_false },
1413 /* true */ {cr_true, cr_true, cr_true, cr_false }
1418 frvbf_cr_logic (SIM_CPU *current_cpu, SI operation, UQI arg1, UQI arg2)
1420 return cr_logic[operation][arg1][arg2];
1423 /* Cache Manipulation. */
1425 frvbf_insn_cache_preload (SIM_CPU *current_cpu, SI address, USI length, int lock)
1427 /* If we need to count cycles, then the cache operation will be
1428 initiated from the model profiling functions.
1429 See frvbf_model_.... */
1430 int hsr0 = GET_HSR0 ();
1431 if (GET_HSR0_ICE (hsr0))
1435 CPU_LOAD_ADDRESS (current_cpu) = address;
1436 CPU_LOAD_LENGTH (current_cpu) = length;
1437 CPU_LOAD_LOCK (current_cpu) = lock;
1441 FRV_CACHE *cache = CPU_INSN_CACHE (current_cpu);
1442 frv_cache_preload (cache, address, length, lock);
1448 frvbf_data_cache_preload (SIM_CPU *current_cpu, SI address, USI length, int lock)
1450 /* If we need to count cycles, then the cache operation will be
1451 initiated from the model profiling functions.
1452 See frvbf_model_.... */
1453 int hsr0 = GET_HSR0 ();
1454 if (GET_HSR0_DCE (hsr0))
1458 CPU_LOAD_ADDRESS (current_cpu) = address;
1459 CPU_LOAD_LENGTH (current_cpu) = length;
1460 CPU_LOAD_LOCK (current_cpu) = lock;
1464 FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
1465 frv_cache_preload (cache, address, length, lock);
1471 frvbf_insn_cache_unlock (SIM_CPU *current_cpu, SI address)
1473 /* If we need to count cycles, then the cache operation will be
1474 initiated from the model profiling functions.
1475 See frvbf_model_.... */
1476 int hsr0 = GET_HSR0 ();
1477 if (GET_HSR0_ICE (hsr0))
1480 CPU_LOAD_ADDRESS (current_cpu) = address;
1483 FRV_CACHE *cache = CPU_INSN_CACHE (current_cpu);
1484 frv_cache_unlock (cache, address);
1490 frvbf_data_cache_unlock (SIM_CPU *current_cpu, SI address)
1492 /* If we need to count cycles, then the cache operation will be
1493 initiated from the model profiling functions.
1494 See frvbf_model_.... */
1495 int hsr0 = GET_HSR0 ();
1496 if (GET_HSR0_DCE (hsr0))
1499 CPU_LOAD_ADDRESS (current_cpu) = address;
1502 FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
1503 frv_cache_unlock (cache, address);
1509 frvbf_insn_cache_invalidate (SIM_CPU *current_cpu, SI address, int all)
1511 /* Make sure the insn was specified properly. -1 will be passed for ALL
1512 for a icei with A=0. */
1515 frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
1519 /* If we need to count cycles, then the cache operation will be
1520 initiated from the model profiling functions.
1521 See frvbf_model_.... */
1524 /* Record the all-entries flag for use in profiling. */
1525 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
1526 ps->all_cache_entries = all;
1527 CPU_LOAD_ADDRESS (current_cpu) = address;
1531 FRV_CACHE *cache = CPU_INSN_CACHE (current_cpu);
1533 frv_cache_invalidate_all (cache, 0/* flush? */);
1535 frv_cache_invalidate (cache, address, 0/* flush? */);
1540 frvbf_data_cache_invalidate (SIM_CPU *current_cpu, SI address, int all)
1542 /* Make sure the insn was specified properly. -1 will be passed for ALL
1543 for a dcei with A=0. */
1546 frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
1550 /* If we need to count cycles, then the cache operation will be
1551 initiated from the model profiling functions.
1552 See frvbf_model_.... */
1555 /* Record the all-entries flag for use in profiling. */
1556 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
1557 ps->all_cache_entries = all;
1558 CPU_LOAD_ADDRESS (current_cpu) = address;
1562 FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
1564 frv_cache_invalidate_all (cache, 0/* flush? */);
1566 frv_cache_invalidate (cache, address, 0/* flush? */);
1571 frvbf_data_cache_flush (SIM_CPU *current_cpu, SI address, int all)
1573 /* Make sure the insn was specified properly. -1 will be passed for ALL
1574 for a dcef with A=0. */
1577 frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
1581 /* If we need to count cycles, then the cache operation will be
1582 initiated from the model profiling functions.
1583 See frvbf_model_.... */
1586 /* Record the all-entries flag for use in profiling. */
1587 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
1588 ps->all_cache_entries = all;
1589 CPU_LOAD_ADDRESS (current_cpu) = address;
1593 FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu);
1595 frv_cache_invalidate_all (cache, 1/* flush? */);
1597 frv_cache_invalidate (cache, address, 1/* flush? */);