1 /* collection of junk waiting time to sort out
2 Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
5 This file is part of the GNU Simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "sim-options.h"
26 /* Not defined in the cgen cpu file for access restriction purposes. */
27 #define H_SPR_ACC4 1412
28 #define H_SPR_ACC63 1471
29 #define H_SPR_ACCG4 1476
30 #define H_SPR_ACCG63 1535
32 /* Initialization of the frv cpu. */
33 void frv_initialize (SIM_CPU *, SIM_DESC);
34 void frv_term (SIM_DESC);
35 void frv_power_on_reset (SIM_CPU *);
36 void frv_hardware_reset (SIM_CPU *);
37 void frv_software_reset (SIM_CPU *);
39 /* The reset register. See FRV LSI section 10.3.1 */
40 #define RSTR_ADDRESS 0xfeff0500
41 #define RSTR_INITIAL_VALUE 0x00000400
42 #define RSTR_HARDWARE_RESET 0x00000200
43 #define RSTR_SOFTWARE_RESET 0x00000100
45 #define GET_RSTR_HR(rstr) (((rstr) >> 1) & 1)
46 #define GET_RSTR_SR(rstr) (((rstr) ) & 1)
48 #define SET_RSTR_H(rstr) ((rstr) |= (1 << 9))
49 #define SET_RSTR_S(rstr) ((rstr) |= (1 << 8))
51 #define CLEAR_RSTR_P(rstr) ((rstr) &= ~(1 << 10))
52 #define CLEAR_RSTR_H(rstr) ((rstr) &= ~(1 << 9))
53 #define CLEAR_RSTR_S(rstr) ((rstr) &= ~(1 << 8))
54 #define CLEAR_RSTR_HR(rstr) ((rstr) &= ~(1 << 1))
55 #define CLEAR_RSTR_SR(rstr) ((rstr) &= ~1)
57 /* Cutomized hardware get/set functions. */
58 extern USI frvbf_h_spr_get_handler (SIM_CPU *, UINT);
59 extern void frvbf_h_spr_set_handler (SIM_CPU *, UINT, USI);
60 extern USI frvbf_h_gr_get_handler (SIM_CPU *, UINT);
61 extern void frvbf_h_gr_set_handler (SIM_CPU *, UINT, USI);
62 extern UHI frvbf_h_gr_hi_get_handler (SIM_CPU *, UINT);
63 extern void frvbf_h_gr_hi_set_handler (SIM_CPU *, UINT, UHI);
64 extern UHI frvbf_h_gr_lo_get_handler (SIM_CPU *, UINT);
65 extern void frvbf_h_gr_lo_set_handler (SIM_CPU *, UINT, UHI);
66 extern DI frvbf_h_gr_double_get_handler (SIM_CPU *, UINT);
67 extern void frvbf_h_gr_double_set_handler (SIM_CPU *, UINT, DI);
68 extern SF frvbf_h_fr_get_handler (SIM_CPU *, UINT);
69 extern void frvbf_h_fr_set_handler (SIM_CPU *, UINT, SF);
70 extern DF frvbf_h_fr_double_get_handler (SIM_CPU *, UINT);
71 extern void frvbf_h_fr_double_set_handler (SIM_CPU *, UINT, DF);
72 extern USI frvbf_h_fr_int_get_handler (SIM_CPU *, UINT);
73 extern void frvbf_h_fr_int_set_handler (SIM_CPU *, UINT, USI);
74 extern DI frvbf_h_cpr_double_get_handler (SIM_CPU *, UINT);
75 extern void frvbf_h_cpr_double_set_handler (SIM_CPU *, UINT, DI);
76 extern void frvbf_h_gr_quad_set_handler (SIM_CPU *, UINT, SI *);
77 extern void frvbf_h_fr_quad_set_handler (SIM_CPU *, UINT, SI *);
78 extern void frvbf_h_cpr_quad_set_handler (SIM_CPU *, UINT, SI *);
79 extern void frvbf_h_psr_s_set_handler (SIM_CPU *, BI);
81 extern USI spr_psr_get_handler (SIM_CPU *);
82 extern void spr_psr_set_handler (SIM_CPU *, USI);
83 extern USI spr_tbr_get_handler (SIM_CPU *);
84 extern void spr_tbr_set_handler (SIM_CPU *, USI);
85 extern USI spr_bpsr_get_handler (SIM_CPU *);
86 extern void spr_bpsr_set_handler (SIM_CPU *, USI);
87 extern USI spr_ccr_get_handler (SIM_CPU *);
88 extern void spr_ccr_set_handler (SIM_CPU *, USI);
89 extern void spr_cccr_set_handler (SIM_CPU *, USI);
90 extern USI spr_cccr_get_handler (SIM_CPU *);
91 extern USI spr_isr_get_handler (SIM_CPU *);
92 extern void spr_isr_set_handler (SIM_CPU *, USI);
93 extern USI spr_sr_get_handler (SIM_CPU *, UINT);
94 extern void spr_sr_set_handler (SIM_CPU *, UINT, USI);
96 extern void frvbf_switch_supervisor_user_context (SIM_CPU *);
98 extern QI frvbf_set_icc_for_shift_left (SIM_CPU *, SI, SI, QI);
99 extern QI frvbf_set_icc_for_shift_right (SIM_CPU *, SI, SI, QI);
101 /* Insn semantics. */
102 extern void frvbf_signed_integer_divide (SIM_CPU *, SI, SI, int, int);
103 extern void frvbf_unsigned_integer_divide (SIM_CPU *, USI, USI, int, int);
104 extern SI frvbf_shift_left_arith_saturate (SIM_CPU *, SI, SI);
105 extern SI frvbf_iacc_cut (SIM_CPU *, DI, SI);
107 extern void frvbf_clear_accumulators (SIM_CPU *, SI, int);
109 extern SI frvbf_scan_result (SIM_CPU *, SI);
110 extern SI frvbf_cut (SIM_CPU *, SI, SI, SI);
111 extern SI frvbf_media_cut (SIM_CPU *, DI, SI);
112 extern SI frvbf_media_cut_ss (SIM_CPU *, DI, SI);
113 extern void frvbf_media_cop (SIM_CPU *, int);
114 extern UQI frvbf_cr_logic (SIM_CPU *, SI, UQI, UQI);
116 extern void frvbf_set_write_next_vliw_addr_to_LR (SIM_CPU *, int);
117 extern int frvbf_write_next_vliw_addr_to_LR;
119 extern void frvbf_set_ne_index (SIM_CPU *, int);
120 extern void frvbf_force_update (SIM_CPU *);
122 #define GETTWI GETTSI
123 #define SETTWI SETTSI
126 /* Hardware/device support.
127 ??? Will eventually want to move device stuff to config files. */
129 /* Support for the MCCR register (Cache Control Register) is needed in order
130 for overlays to work correctly with the scache: cached instructions need
131 to be flushed when the instruction space is changed at runtime. */
133 /* These were just copied from another port and are necessary to build, but
134 but don't appear to be used. */
135 #define MCCR_ADDR 0xffffffff
141 /* sim_core_attach device argument. */
142 extern device frv_devices;
144 /* FIXME: Temporary, until device support ready. */
145 struct _device { int foo; };
147 /* maintain the address of the start of the previous VLIW insn sequence. */
148 extern IADDR previous_vliw_pc;
149 extern CGEN_ATTR_VALUE_TYPE frv_current_fm_slot;
151 /* Hardware status. */
152 #define GET_HSR0() GET_H_SPR (H_SPR_HSR0)
153 #define SET_HSR0(hsr0) SET_H_SPR (H_SPR_HSR0, (hsr0))
155 #define GET_HSR0_ICE(hsr0) (((hsr0) >> 31) & 1)
156 #define SET_HSR0_ICE(hsr0) ((hsr0) |= (1 << 31))
157 #define CLEAR_HSR0_ICE(hsr0) ((hsr0) &= ~(1 << 31))
159 #define GET_HSR0_DCE(hsr0) (((hsr0) >> 30) & 1)
160 #define SET_HSR0_DCE(hsr0) ((hsr0) |= (1 << 30))
161 #define CLEAR_HSR0_DCE(hsr0) ((hsr0) &= ~(1 << 30))
163 #define GET_HSR0_CBM(hsr0) (((hsr0) >> 27) & 1)
164 #define GET_HSR0_RME(hsr0) (((hsr0) >> 22) & 1)
165 #define GET_HSR0_SA(hsr0) (((hsr0) >> 12) & 1)
166 #define GET_HSR0_FRN(hsr0) (((hsr0) >> 11) & 1)
167 #define GET_HSR0_GRN(hsr0) (((hsr0) >> 10) & 1)
168 #define GET_HSR0_FRHE(hsr0) (((hsr0) >> 9) & 1)
169 #define GET_HSR0_FRLE(hsr0) (((hsr0) >> 8) & 1)
170 #define GET_HSR0_GRHE(hsr0) (((hsr0) >> 7) & 1)
171 #define GET_HSR0_GRLE(hsr0) (((hsr0) >> 6) & 1)
173 #define GET_IHSR8() GET_H_SPR (H_SPR_IHSR8)
174 #define GET_IHSR8_NBC(ihsr8) ((ihsr8) & 1)
175 #define GET_IHSR8_ICDM(ihsr8) (((ihsr8) >> 1) & 1)
176 #define GET_IHSR8_ICWE(ihsr8) (((ihsr8) >> 8) & 7)
177 #define GET_IHSR8_DCWE(ihsr8) (((ihsr8) >> 12) & 7)
179 void frvbf_insn_cache_preload (SIM_CPU *, SI, USI, int);
180 void frvbf_data_cache_preload (SIM_CPU *, SI, USI, int);
181 void frvbf_insn_cache_unlock (SIM_CPU *, SI);
182 void frvbf_data_cache_unlock (SIM_CPU *, SI);
183 void frvbf_insn_cache_invalidate (SIM_CPU *, SI, int);
184 void frvbf_data_cache_invalidate (SIM_CPU *, SI, int);
185 void frvbf_data_cache_flush (SIM_CPU *, SI, int);
187 /* FR-V Interrupt classes.
188 These are declared in order of increasing priority. */
189 enum frv_interrupt_class
191 FRV_EXTERNAL_INTERRUPT,
192 FRV_SOFTWARE_INTERRUPT,
193 FRV_PROGRAM_INTERRUPT,
196 NUM_FRV_INTERRUPT_CLASSES
199 /* FR-V Interrupt kinds.
200 These are declared in order of increasing priority. */
201 enum frv_interrupt_kind
203 /* External interrupts */
204 FRV_INTERRUPT_LEVEL_1,
205 FRV_INTERRUPT_LEVEL_2,
206 FRV_INTERRUPT_LEVEL_3,
207 FRV_INTERRUPT_LEVEL_4,
208 FRV_INTERRUPT_LEVEL_5,
209 FRV_INTERRUPT_LEVEL_6,
210 FRV_INTERRUPT_LEVEL_7,
211 FRV_INTERRUPT_LEVEL_8,
212 FRV_INTERRUPT_LEVEL_9,
213 FRV_INTERRUPT_LEVEL_10,
214 FRV_INTERRUPT_LEVEL_11,
215 FRV_INTERRUPT_LEVEL_12,
216 FRV_INTERRUPT_LEVEL_13,
217 FRV_INTERRUPT_LEVEL_14,
218 FRV_INTERRUPT_LEVEL_15,
219 /* Software interrupt */
220 FRV_TRAP_INSTRUCTION,
221 /* Program interrupts */
222 FRV_COMMIT_EXCEPTION,
223 FRV_DIVISION_EXCEPTION,
224 FRV_DATA_STORE_ERROR,
225 FRV_DATA_ACCESS_EXCEPTION,
226 FRV_DATA_ACCESS_MMU_MISS,
227 FRV_DATA_ACCESS_ERROR,
230 FRV_MEM_ADDRESS_NOT_ALIGNED,
231 FRV_REGISTER_EXCEPTION,
234 FRV_PRIVILEGED_INSTRUCTION,
235 FRV_ILLEGAL_INSTRUCTION,
236 FRV_INSTRUCTION_ACCESS_EXCEPTION,
237 FRV_INSTRUCTION_ACCESS_ERROR,
238 FRV_INSTRUCTION_ACCESS_MMU_MISS,
239 FRV_COMPOUND_EXCEPTION,
240 /* Break interrupt */
242 /* Reset interrupt */
244 NUM_FRV_INTERRUPT_KINDS
247 /* FRV interrupt exception codes */
250 FRV_EC_DATA_STORE_ERROR = 0x00,
251 FRV_EC_INSTRUCTION_ACCESS_MMU_MISS = 0x01,
252 FRV_EC_INSTRUCTION_ACCESS_ERROR = 0x02,
253 FRV_EC_INSTRUCTION_ACCESS_EXCEPTION = 0x03,
254 FRV_EC_PRIVILEGED_INSTRUCTION = 0x04,
255 FRV_EC_ILLEGAL_INSTRUCTION = 0x05,
256 FRV_EC_FP_DISABLED = 0x06,
257 FRV_EC_MP_DISABLED = 0x07,
258 FRV_EC_MEM_ADDRESS_NOT_ALIGNED = 0x0b,
259 FRV_EC_REGISTER_EXCEPTION = 0x0c,
260 FRV_EC_FP_EXCEPTION = 0x0d,
261 FRV_EC_MP_EXCEPTION = 0x0e,
262 FRV_EC_DATA_ACCESS_ERROR = 0x10,
263 FRV_EC_DATA_ACCESS_MMU_MISS = 0x11,
264 FRV_EC_DATA_ACCESS_EXCEPTION = 0x12,
265 FRV_EC_DIVISION_EXCEPTION = 0x13,
266 FRV_EC_COMMIT_EXCEPTION = 0x14,
267 FRV_EC_NOT_EXECUTED = 0x1f,
268 FRV_EC_INTERRUPT_LEVEL_1 = FRV_EC_NOT_EXECUTED,
269 FRV_EC_INTERRUPT_LEVEL_2 = FRV_EC_NOT_EXECUTED,
270 FRV_EC_INTERRUPT_LEVEL_3 = FRV_EC_NOT_EXECUTED,
271 FRV_EC_INTERRUPT_LEVEL_4 = FRV_EC_NOT_EXECUTED,
272 FRV_EC_INTERRUPT_LEVEL_5 = FRV_EC_NOT_EXECUTED,
273 FRV_EC_INTERRUPT_LEVEL_6 = FRV_EC_NOT_EXECUTED,
274 FRV_EC_INTERRUPT_LEVEL_7 = FRV_EC_NOT_EXECUTED,
275 FRV_EC_INTERRUPT_LEVEL_8 = FRV_EC_NOT_EXECUTED,
276 FRV_EC_INTERRUPT_LEVEL_9 = FRV_EC_NOT_EXECUTED,
277 FRV_EC_INTERRUPT_LEVEL_10 = FRV_EC_NOT_EXECUTED,
278 FRV_EC_INTERRUPT_LEVEL_11 = FRV_EC_NOT_EXECUTED,
279 FRV_EC_INTERRUPT_LEVEL_12 = FRV_EC_NOT_EXECUTED,
280 FRV_EC_INTERRUPT_LEVEL_13 = FRV_EC_NOT_EXECUTED,
281 FRV_EC_INTERRUPT_LEVEL_14 = FRV_EC_NOT_EXECUTED,
282 FRV_EC_INTERRUPT_LEVEL_15 = FRV_EC_NOT_EXECUTED,
283 FRV_EC_TRAP_INSTRUCTION = FRV_EC_NOT_EXECUTED,
284 FRV_EC_COMPOUND_EXCEPTION = FRV_EC_NOT_EXECUTED,
285 FRV_EC_BREAK_EXCEPTION = FRV_EC_NOT_EXECUTED,
286 FRV_EC_RESET = FRV_EC_NOT_EXECUTED
290 This struct contains enough information to describe a particular interrupt
294 enum frv_interrupt_kind kind;
296 enum frv_interrupt_class iclass;
297 unsigned char deferred;
298 unsigned char precise;
299 unsigned char handler_offset;
302 /* FR-V Interrupt table.
303 Describes the interrupts supported by the FR-V. */
304 extern struct frv_interrupt frv_interrupt_table[];
306 /* FR-V Interrupt State.
307 Interrupts are queued during execution of parallel insns and the interupt(s)
308 to be handled determined by analysing the queue after each VLIW insn. */
309 #define FRV_INTERRUPT_QUEUE_SIZE (4 * 4) /* 4 interrupts x 4 insns for now. */
311 /* register_exception codes */
314 FRV_REC_UNIMPLEMENTED = 0,
315 FRV_REC_UNALIGNED = 1
318 /* instruction_access_exception codes */
321 FRV_IAEC_PROTECT_VIOLATION = 1
324 /* data_access_exception codes */
327 FRV_DAEC_PROTECT_VIOLATION = 1
330 /* division_exception ISR codes */
333 FRV_DTT_NO_EXCEPTION = 0,
334 FRV_DTT_DIVISION_BY_ZERO = 1,
335 FRV_DTT_OVERFLOW = 2,
339 /* data written during an insn causing an interrupt */
340 struct frv_data_written
342 USI words[4]; /* Actual data in words */
343 int length; /* length of data written */
346 /* fp_exception info */
347 /* Trap codes for FSR0 and FQ registers. */
350 FSR_INVALID_OPERATION = 0x20,
352 FSR_UNDERFLOW = 0x08,
353 FSR_DIVISION_BY_ZERO = 0x04,
355 FSR_DENORMAL_INPUT = 0x01,
359 /* Floating point trap types for FSR. */
363 FTT_IEEE_754_EXCEPTION = 1,
364 FTT_UNIMPLEMENTED_FPOP = 3,
365 FTT_SEQUENCE_ERROR = 4,
367 FTT_DENORMAL_INPUT = 7
370 struct frv_fp_exception_info
372 enum frv_fsr_traps fsr_mask; /* interrupt code for FSR */
373 enum frv_fsr_ftt ftt; /* floating point trap type */
376 struct frv_interrupt_queue_element
378 enum frv_interrupt_kind kind; /* kind of interrupt */
379 IADDR vpc; /* address of insn causing interrupt */
380 int slot; /* VLIW slot containing the insn. */
381 USI eaddress; /* address of data access */
383 enum frv_rec rec; /* register exception code */
384 enum frv_iaec iaec; /* insn access exception code */
385 enum frv_daec daec; /* data access exception code */
386 enum frv_dtt dtt; /* division exception code */
387 struct frv_fp_exception_info fp_info;
388 struct frv_data_written data_written;
392 struct frv_interrupt_timer
397 enum frv_interrupt_kind interrupt;
400 struct frv_interrupt_state
402 /* The interrupt queue */
403 struct frv_interrupt_queue_element queue[FRV_INTERRUPT_QUEUE_SIZE];
406 /* interrupt queue element causing imprecise interrupt. */
407 struct frv_interrupt_queue_element *imprecise_interrupt;
409 /* interrupt timer. */
410 struct frv_interrupt_timer timer;
412 /* The last data written stored as an array of words. */
413 struct frv_data_written data_written;
415 /* The vliw slot of the insn causing the interrupt. */
418 /* target register index for non excepting insns. */
419 #define NE_NOFLAG (-1)
422 /* Accumulated NE flags for non excepting floating point insns. */
426 extern struct frv_interrupt_state frv_interrupt_state;
428 /* Macros to manipulate the PSR. */
429 #define GET_PSR() GET_H_SPR (H_SPR_PSR)
431 #define SET_PSR_ET(psr, et) ( \
432 (psr) = ((psr) & ~0x1) | ((et) & 0x1) \
435 #define GET_PSR_PS(psr) (((psr) >> 1) & 1)
437 #define SET_PSR_S(psr, s) ( \
438 (psr) = ((psr) & ~(0x1 << 2)) | (((s) & 0x1) << 2) \
441 /* Macros to handle the ISR register. */
442 #define GET_ISR() GET_H_SPR (H_SPR_ISR)
443 #define SET_ISR(isr) SET_H_SPR (H_SPR_ISR, (isr))
445 #define GET_ISR_EDE(isr) (((isr) >> 5) & 1)
447 #define GET_ISR_DTT(isr) (((isr) >> 3) & 3)
448 #define SET_ISR_DTT(isr, dtt) ( \
449 (isr) = ((isr) & ~(0x3 << 3)) | (((dtt) & 0x3) << 3) \
452 #define SET_ISR_AEXC(isr) ((isr) |= (1 << 2))
454 #define GET_ISR_EMAM(isr) ((isr) & 1)
456 /* Macros to handle exception status registers.
457 Get and set the hardware directly, since we may be getting/setting fields
458 which are not accessible to the user. */
459 #define GET_ESR(index) \
460 (CPU (h_spr[H_SPR_ESR0 + (index)]))
461 #define SET_ESR(index, esr) \
462 (CPU (h_spr[H_SPR_ESR0 + (index)]) = (esr))
464 #define SET_ESR_VALID(esr) ((esr) |= 1)
465 #define CLEAR_ESR_VALID(esr) ((esr) &= ~1)
467 #define SET_ESR_EC(esr, ec) ( \
468 (esr) = ((esr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
471 #define SET_ESR_REC(esr, rec) ( \
472 (esr) = ((esr) & ~(0x3 << 6)) | (((rec) & 0x3) << 6) \
475 #define SET_ESR_IAEC(esr, iaec) ( \
476 (esr) = ((esr) & ~(0x1 << 8)) | (((iaec) & 0x1) << 8) \
479 #define SET_ESR_DAEC(esr, daec) ( \
480 (esr) = ((esr) & ~(0x1 << 9)) | (((daec) & 0x1) << 9) \
483 #define SET_ESR_EAV(esr) ((esr) |= (1 << 11))
484 #define CLEAR_ESR_EAV(esr) ((esr) &= ~(1 << 11))
486 #define GET_ESR_EDV(esr) (((esr) >> 12) & 1)
487 #define SET_ESR_EDV(esr) ((esr) |= (1 << 12))
488 #define CLEAR_ESR_EDV(esr) ((esr) &= ~(1 << 12))
490 #define GET_ESR_EDN(esr) ( \
491 ((esr) >> 13) & 0xf \
493 #define SET_ESR_EDN(esr, edn) ( \
494 (esr) = ((esr) & ~(0xf << 13)) | (((edn) & 0xf) << 13) \
497 #define SET_EPCR(index, address) \
498 (CPU (h_spr[H_SPR_EPCR0 + (index)]) = (address))
500 #define SET_EAR(index, address) \
501 (CPU (h_spr[H_SPR_EAR0 + (index)]) = (address))
503 #define SET_EDR(index, edr) \
504 (CPU (h_spr[H_SPR_EDR0 + (index)]) = (edr))
506 #define GET_ESFR(index) \
507 (CPU (h_spr[H_SPR_ESFR0 + (index)]))
508 #define SET_ESFR(index, esfr) \
509 (CPU (h_spr[H_SPR_ESFR0 + (index)]) = (esfr))
511 #define GET_ESFR_FLAG(findex) ( \
513 ((CPU (h_spr[H_SPR_ESFR0]) >> ((findex)-32)) & 1) \
515 ((CPU (h_spr[H_SPR_ESFR1]) >> (findex)) & 1) \
517 #define SET_ESFR_FLAG(findex) ( \
519 (CPU (h_spr[H_SPR_ESFR0]) = \
520 (CPU (h_spr[H_SPR_ESFR0]) | (1 << ((findex)-32))) \
522 (CPU (h_spr[H_SPR_ESFR1]) = \
523 (CPU (h_spr[H_SPR_ESFR1]) | (1 << (findex))) \
527 /* The FSR registers.
528 Get and set the hardware directly, since we may be getting/setting fields
529 which are not accessible to the user. */
530 #define GET_FSR(index) \
531 (CPU (h_spr[H_SPR_FSR0 + (index)]))
532 #define SET_FSR(index, fsr) \
533 (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr))
535 #define GET_FSR_TEM(fsr) ( \
536 ((fsr) >> 24) & 0x3f \
539 #define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20))
540 #define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1)
542 #define SET_FSR_FTT(fsr, ftt) ( \
543 (fsr) = ((fsr) & ~(0x7 << 17)) | (((ftt) & 0x7) << 17) \
546 #define GET_FSR_AEXC(fsr) ( \
547 ((fsr) >> 10) & 0x3f \
549 #define SET_FSR_AEXC(fsr, aexc) ( \
550 (fsr) = ((fsr) & ~(0x3f << 10)) | (((aexc) & 0x3f) << 10) \
553 /* SIMD instruction exception codes for FQ. */
561 /* MIV field of FQ. */
568 /* The FQ registers are 64 bits wide and are implemented as 32 bit pairs. The
569 index here refers to the low order 32 bit element.
570 Get and set the hardware directly, since we may be getting/setting fields
571 which are not accessible to the user. */
572 #define GET_FQ(index) \
573 (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]))
574 #define SET_FQ(index, fq) \
575 (CPU (h_spr[H_SPR_FQST0 + 2 * (index)]) = (fq))
577 #define SET_FQ_MIV(fq, miv) ( \
578 (fq) = ((fq) & ~(0x1 << 31)) | (((miv) & 0x1) << 31) \
581 #define SET_FQ_SIE(fq, sie) ( \
582 (fq) = ((fq) & ~(0x3 << 15)) | (((sie) & 0x3) << 15) \
585 #define SET_FQ_FTT(fq, ftt) ( \
586 (fq) = ((fq) & ~(0x7 << 7)) | (((ftt) & 0x7) << 7) \
589 #define SET_FQ_CEXC(fq, cexc) ( \
590 (fq) = ((fq) & ~(0x3f << 1)) | (((cexc) & 0x3f) << 1) \
593 #define GET_FQ_VALID(fq) ((fq) & 1)
594 #define SET_FQ_VALID(fq) ((fq) |= 1)
596 #define SET_FQ_OPC(index, insn) \
597 (CPU (h_spr[H_SPR_FQOP0 + 2 * (index)]) = (insn))
599 /* mp_exception support. */
600 /* Media trap types for MSR. */
605 MTT_ACC_NOT_ALIGNED = 2,
606 MTT_ACC_NOT_IMPLEMENTED = 2, /* Yes -- same value as MTT_ACC_NOT_ALIGNED. */
607 MTT_CR_NOT_ALIGNED = 3,
608 MTT_UNIMPLEMENTED_MPOP = 5,
612 /* Media status registers.
613 Get and set the hardware directly, since we may be getting/setting fields
614 which are not accessible to the user. */
615 #define GET_MSR(index) \
616 (CPU (h_spr[H_SPR_MSR0 + (index)]))
617 #define SET_MSR(index, msr) \
618 (CPU (h_spr[H_SPR_MSR0 + (index)]) = (msr))
620 #define GET_MSR_AOVF(msr) ((msr) & 1)
621 #define SET_MSR_AOVF(msr) ((msr) |= 1)
623 #define GET_MSR_OVF(msr) ( \
626 #define SET_MSR_OVF(msr) ( \
629 #define CLEAR_MSR_OVF(msr) ( \
633 #define OR_MSR_SIE(msr, sie) ( \
634 (msr) |= (((sie) & 0xf) << 2) \
636 #define CLEAR_MSR_SIE(msr) ( \
637 (msr) &= ~(0xf << 2) \
640 #define GET_MSR_MTT(msr) ( \
641 ((msr) >> 12) & 0x7 \
643 #define SET_MSR_MTT(msr, mtt) ( \
644 (msr) = ((msr) & ~(0x7 << 12)) | (((mtt) & 0x7) << 12) \
646 #define GET_MSR_EMCI(msr) ( \
647 ((msr) >> 24) & 0x1 \
649 #define GET_MSR_MPEM(msr) ( \
650 ((msr) >> 27) & 0x1 \
652 #define GET_MSR_SRDAV(msr) ( \
653 ((msr) >> 28) & 0x1 \
655 #define GET_MSR_RDAV(msr) ( \
656 ((msr) >> 29) & 0x1 \
658 #define GET_MSR_RD(msr) ( \
659 ((msr) >> 30) & 0x3 \
662 void frvbf_media_register_not_aligned (SIM_CPU *);
663 void frvbf_media_acc_not_aligned (SIM_CPU *);
664 void frvbf_media_cr_not_aligned (SIM_CPU *);
665 void frvbf_media_overflow (SIM_CPU *, int);
667 /* Functions for queuing and processing interrupts. */
668 struct frv_interrupt_queue_element *
669 frv_queue_break_interrupt (SIM_CPU *);
671 struct frv_interrupt_queue_element *
672 frv_queue_software_interrupt (SIM_CPU *, SI);
674 struct frv_interrupt_queue_element *
675 frv_queue_program_interrupt (SIM_CPU *, enum frv_interrupt_kind);
677 struct frv_interrupt_queue_element *
678 frv_queue_external_interrupt (SIM_CPU *, enum frv_interrupt_kind);
680 struct frv_interrupt_queue_element *
681 frv_queue_illegal_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
683 struct frv_interrupt_queue_element *
684 frv_queue_privileged_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
686 struct frv_interrupt_queue_element *
687 frv_queue_float_disabled_interrupt (SIM_CPU *);
689 struct frv_interrupt_queue_element *
690 frv_queue_media_disabled_interrupt (SIM_CPU *);
692 struct frv_interrupt_queue_element *
693 frv_queue_non_implemented_instruction_interrupt (SIM_CPU *, const CGEN_INSN *);
695 struct frv_interrupt_queue_element *
696 frv_queue_register_exception_interrupt (SIM_CPU *, enum frv_rec);
698 struct frv_interrupt_queue_element *
699 frv_queue_mem_address_not_aligned_interrupt (SIM_CPU *, USI);
701 struct frv_interrupt_queue_element *
702 frv_queue_data_access_error_interrupt (SIM_CPU *, USI);
704 struct frv_interrupt_queue_element *
705 frv_queue_instruction_access_error_interrupt (SIM_CPU *);
707 struct frv_interrupt_queue_element *
708 frv_queue_instruction_access_exception_interrupt (SIM_CPU *);
710 struct frv_interrupt_queue_element *
711 frv_queue_fp_exception_interrupt (SIM_CPU *, struct frv_fp_exception_info *);
713 enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int);
715 struct frv_interrupt_queue_element *
716 frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind);
719 frv_set_interrupt_queue_slot (SIM_CPU *, struct frv_interrupt_queue_element *);
721 void frv_set_mp_exception_registers (SIM_CPU *, enum frv_msr_mtt, int);
722 void frv_detect_insn_access_interrupts (SIM_CPU *, SCACHE *);
724 void frv_process_interrupts (SIM_CPU *);
726 void frv_break_interrupt (SIM_CPU *, struct frv_interrupt *, IADDR);
727 void frv_non_operating_interrupt (SIM_CPU *, enum frv_interrupt_kind, IADDR);
728 void frv_program_interrupt (
729 SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
731 void frv_software_interrupt (
732 SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
734 void frv_external_interrupt (
735 SIM_CPU *, struct frv_interrupt_queue_element *, IADDR
737 void frv_program_or_software_interrupt (
738 SIM_CPU *, struct frv_interrupt *, IADDR
740 void frv_clear_interrupt_classes (
741 enum frv_interrupt_class, enum frv_interrupt_class
745 frv_save_data_written_for_interrupts (SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *);
747 /* Special purpose traps. */
748 #define TRAP_SYSCALL 0x80
749 #define TRAP_BREAKPOINT 0x81
750 #define TRAP_REGDUMP1 0x82
751 #define TRAP_REGDUMP2 0x83
753 /* Handle the trap insns */
754 void frv_itrap (SIM_CPU *, PCADDR, USI, int);
755 void frv_mtrap (SIM_CPU *);
756 /* Handle the break insn. */
757 void frv_break (SIM_CPU *);
758 /* Handle the rett insn. */
759 USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field);
761 /* Parallel write queue flags. */
762 #define FRV_WRITE_QUEUE_FORCE_WRITE 1
764 #define CGEN_WRITE_QUEUE_ELEMENT_PIPE(element) CGEN_WRITE_QUEUE_ELEMENT_WORD1 (element)
766 /* Functions and macros for handling non-excepting instruction side effects.
767 Get and set the hardware directly, since we may be getting/setting fields
768 which are not accessible to the user. */
769 #define GET_NECR() (GET_H_SPR (H_SPR_NECR))
770 #define GET_NECR_ELOS(necr) (((necr) >> 6) & 1)
771 #define GET_NECR_NEN(necr) (((necr) >> 1) & 0x1f)
772 #define GET_NECR_VALID(necr) (((necr) ) & 1)
775 /* NESR field values. See Tables 30-33 in section 4.4.2.1 of the FRV
776 Architecture volume 1. */
777 #define NESR_MEM_ADDRESS_NOT_ALIGNED 0x0b
778 #define NESR_REGISTER_NOT_ALIGNED 0x1
779 #define NESR_UQI_SIZE 0
780 #define NESR_QI_SIZE 1
781 #define NESR_UHI_SIZE 2
782 #define NESR_HI_SIZE 3
783 #define NESR_SI_SIZE 4
784 #define NESR_DI_SIZE 5
785 #define NESR_XI_SIZE 6
787 #define GET_NESR(index) GET_H_SPR (H_SPR_NESR0 + (index))
788 #define SET_NESR(index, value) ( \
789 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, \
790 H_SPR_NESR0 + (index), (value)), \
791 frvbf_force_update (current_cpu) \
793 #define GET_NESR_VALID(nesr) ((nesr) & 1)
794 #define SET_NESR_VALID(nesr) ((nesr) |= 1)
796 #define SET_NESR_EAV(nesr) ((nesr) |= (1 << 31))
798 #define GET_NESR_FR(nesr) (((nesr) >> 30) & 1)
799 #define SET_NESR_FR(nesr) ((nesr) |= (1 << 30))
800 #define CLEAR_NESR_FR(nesr) ((nesr) &= ~(1 << 30))
802 #define GET_NESR_DRN(nesr) (((nesr) >> 24) & 0x3f)
803 #define SET_NESR_DRN(nesr, drn) ( \
804 (nesr) = ((nesr) & ~(0x3f << 24)) | (((drn) & 0x3f) << 24) \
807 #define SET_NESR_SIZE(nesr, data_size) ( \
808 (nesr) = ((nesr) & ~(0x7 << 21)) | (((data_size) & 0x7) << 21) \
811 #define SET_NESR_NEAN(nesr, index) ( \
812 (nesr) = ((nesr) & ~(0x1f << 10)) | (((index) & 0x1f) << 10) \
815 #define GET_NESR_DAEC(nesr) (((nesr) >> 9) & 1)
816 #define SET_NESR_DAEC(nesr, daec) ( \
817 (nesr) = ((nesr) & ~(1 << 9)) | (((daec) & 1) << 9) \
820 #define GET_NESR_REC(nesr) (((nesr) >> 6) & 3)
821 #define SET_NESR_REC(nesr, rec) ( \
822 (nesr) = ((nesr) & ~(3 << 6)) | (((rec) & 3) << 6) \
825 #define GET_NESR_EC(nesr) (((nesr) >> 1) & 0x1f)
826 #define SET_NESR_EC(nesr, ec) ( \
827 (nesr) = ((nesr) & ~(0x1f << 1)) | (((ec) & 0x1f) << 1) \
830 #define SET_NEEAR(index, address) ( \
831 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, \
832 H_SPR_NEEAR0 + (index), (address)), \
833 frvbf_force_update (current_cpu) \
836 #define GET_NE_FLAGS(flags, NE_base) ( \
837 (flags)[0] = GET_H_SPR ((NE_base)), \
838 (flags)[1] = GET_H_SPR ((NE_base) + 1) \
840 #define SET_NE_FLAGS(NE_base, flags) ( \
841 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base), \
843 frvbf_force_update (current_cpu), \
844 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, (NE_base) + 1, \
846 frvbf_force_update (current_cpu) \
849 #define GET_NE_FLAG(flags, index) ( \
851 ((flags[0] >> ((index) - 32)) & 1) \
853 ((flags[1] >> (index)) & 1) \
855 #define SET_NE_FLAG(flags, index) ( \
857 ((flags)[0] |= (1 << ((index) - 32))) \
859 ((flags)[1] |= (1 << (index))) \
861 #define CLEAR_NE_FLAG(flags, index) ( \
863 ((flags)[0] &= ~(1 << ((index) - 32))) \
865 ((flags)[1] &= ~(1 << (index))) \
868 BI frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI);
869 void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int);
871 void frvbf_clear_ne_flags (SIM_CPU *, SI, BI);
872 void frvbf_commit (SIM_CPU *, SI, BI);
874 void frvbf_fpu_error (CGEN_FPU *, int);
876 void frv_vliw_setup_insn (SIM_CPU *, const CGEN_INSN *);
878 extern int insns_in_slot[];
880 #define COUNT_INSNS_IN_SLOT(slot) \
882 if (WITH_PROFILE_MODEL_P) \
883 ++insns_in_slot[slot]; \
886 #define INSNS_IN_SLOT(slot) (insns_in_slot[slot])
888 /* Multiple loads and stores. */
889 void frvbf_load_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
890 void frvbf_load_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
891 void frvbf_load_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
892 void frvbf_store_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
893 void frvbf_store_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
894 void frvbf_store_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
896 /* Memory and cache support. */
897 QI frvbf_read_mem_QI (SIM_CPU *, IADDR, SI);
898 UQI frvbf_read_mem_UQI (SIM_CPU *, IADDR, SI);
899 HI frvbf_read_mem_HI (SIM_CPU *, IADDR, SI);
900 UHI frvbf_read_mem_UHI (SIM_CPU *, IADDR, SI);
901 SI frvbf_read_mem_SI (SIM_CPU *, IADDR, SI);
902 SI frvbf_read_mem_WI (SIM_CPU *, IADDR, SI);
903 DI frvbf_read_mem_DI (SIM_CPU *, IADDR, SI);
904 DF frvbf_read_mem_DF (SIM_CPU *, IADDR, SI);
906 USI frvbf_read_imem_USI (SIM_CPU *, PCADDR);
908 void frvbf_write_mem_QI (SIM_CPU *, IADDR, SI, QI);
909 void frvbf_write_mem_UQI (SIM_CPU *, IADDR, SI, UQI);
910 void frvbf_write_mem_HI (SIM_CPU *, IADDR, SI, HI);
911 void frvbf_write_mem_UHI (SIM_CPU *, IADDR, SI, UHI);
912 void frvbf_write_mem_SI (SIM_CPU *, IADDR, SI, SI);
913 void frvbf_write_mem_WI (SIM_CPU *, IADDR, SI, SI);
914 void frvbf_write_mem_DI (SIM_CPU *, IADDR, SI, DI);
915 void frvbf_write_mem_DF (SIM_CPU *, IADDR, SI, DF);
917 void frvbf_mem_set_QI (SIM_CPU *, IADDR, SI, QI);
918 void frvbf_mem_set_HI (SIM_CPU *, IADDR, SI, HI);
919 void frvbf_mem_set_SI (SIM_CPU *, IADDR, SI, SI);
920 void frvbf_mem_set_DI (SIM_CPU *, IADDR, SI, DI);
921 void frvbf_mem_set_DF (SIM_CPU *, IADDR, SI, DF);
922 void frvbf_mem_set_XI (SIM_CPU *, IADDR, SI, SI *);
924 void frv_set_write_queue_slot (SIM_CPU *current_cpu);
926 /* FRV specific options. */
927 extern const OPTION frv_options[];
929 #endif /* FRV_SIM_H */