2 * This file is part of SIS.
4 * SIS, SPARC instruction simulator V2.5 Copyright (C) 1995 Jiri Gaisler,
5 * European Space Agency
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 3 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, see <http://www.gnu.org/licenses/>.
22 /* The control space devices */
25 #include <sys/types.h>
29 #include <sys/fcntl.h>
34 #include "sim-config.h"
37 extern int32 sis_verbose;
38 extern int32 sparclite, sparclite_board;
39 extern int rom8,wrp,uben;
40 extern char uart_dev1[], uart_dev2[];
42 int dumbio = 0; /* normal, smart, terminal oriented IO by default */
45 #define MEC_START 0x01f80000
46 #define MEC_END 0x01f80100
48 /* Memory exception waitstates */
51 /* ERC32 always adds one waitstate during RAM std */
58 /* The target's byte order is big-endian by default until we load a
59 little-endian program. */
61 int current_target_byte_order = BIG_ENDIAN;
63 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
66 /* MEC register addresses */
70 #define MEC_PWDR 0x008
71 #define MEC_MEMCFG 0x010
72 #define MEC_IOCR 0x014
75 #define MEC_MAR0 0x020
76 #define MEC_MAR1 0x024
78 #define MEC_SSA1 0x020
79 #define MEC_SEA1 0x024
80 #define MEC_SSA2 0x028
81 #define MEC_SEA2 0x02C
87 #define MEC_WDOG 0x060
88 #define MEC_TRAPD 0x064
89 #define MEC_RTC_COUNTER 0x080
90 #define MEC_RTC_RELOAD 0x080
91 #define MEC_RTC_SCALER 0x084
92 #define MEC_GPT_COUNTER 0x088
93 #define MEC_GPT_RELOAD 0x088
94 #define MEC_GPT_SCALER 0x08C
95 #define MEC_TIMER_CTRL 0x098
96 #define MEC_SFSR 0x0A0
97 #define MEC_FFAR 0x0A4
98 #define MEC_ERSR 0x0B0
100 #define MEC_TCR 0x0D0
102 #define MEC_BRK 0x0C4
103 #define MEC_WPR 0x0C8
105 #define MEC_UARTA 0x0E0
106 #define MEC_UARTB 0x0E4
107 #define MEC_UART_CTRL 0x0E8
108 #define SIM_LOAD 0x0F0
110 /* Memory exception causes */
114 #define WATCH_EXC 0xa
115 #define BREAK_EXC 0xb
117 /* Size of UART buffers (bytes) */
120 /* Number of simulator ticks between flushing the UARTS. */
121 /* For good performance, keep above 1000 */
122 #define UART_FLUSH_TIME 3000
124 /* MEC timer control register bits */
129 #define TCR_TCRCR 0x100
130 #define TCR_TCRCL 0x200
131 #define TCR_TCRSE 0x400
132 #define TCR_TCRSL 0x800
134 /* New uart defines */
135 #define UART_TX_TIME 1000
136 #define UART_RX_TIME 1000
138 #define UARTA_SRE 0x2
139 #define UARTA_HRE 0x4
140 #define UARTA_OR 0x40
141 #define UARTA_CLR 0x80
142 #define UARTB_DR 0x10000
143 #define UARTB_SRE 0x20000
144 #define UARTB_HRE 0x40000
145 #define UARTB_OR 0x400000
146 #define UARTB_CLR 0x800000
148 #define UART_DR 0x100
149 #define UART_TSE 0x200
150 #define UART_THE 0x400
154 static char fname[256];
155 static int32 find = 0;
156 static uint32 mec_ssa[2]; /* Write protection start address */
157 static uint32 mec_sea[2]; /* Write protection end address */
158 static uint32 mec_wpr[2]; /* Write protection control fields */
159 static uint32 mec_sfsr;
160 static uint32 mec_ffar;
161 static uint32 mec_ipr;
162 static uint32 mec_imr;
163 static uint32 mec_isr;
164 static uint32 mec_icr;
165 static uint32 mec_ifr;
166 static uint32 mec_mcr; /* MEC control register */
167 static uint32 mec_memcfg; /* Memory control register */
168 static uint32 mec_wcr; /* MEC waitstate register */
169 static uint32 mec_iocr; /* MEC IO control register */
170 static uint32 posted_irq;
171 static uint32 mec_ersr; /* MEC error and status register */
172 static uint32 mec_tcr; /* MEC test comtrol register */
174 static uint32 rtc_counter;
175 static uint32 rtc_reload;
176 static uint32 rtc_scaler;
177 static uint32 rtc_scaler_start;
178 static uint32 rtc_enabled;
179 static uint32 rtc_cr;
180 static uint32 rtc_se;
182 static uint32 gpt_counter;
183 static uint32 gpt_reload;
184 static uint32 gpt_scaler;
185 static uint32 gpt_scaler_start;
186 static uint32 gpt_enabled;
187 static uint32 gpt_cr;
188 static uint32 gpt_se;
190 static uint32 wdog_scaler;
191 static uint32 wdog_counter;
192 static uint32 wdog_rst_delay;
193 static uint32 wdog_rston;
196 init, disabled, enabled, stopped
199 static enum wdog_type wdog_status;
202 /* ROM size 1024 Kbyte */
203 #define ROM_SZ 0x100000
204 #define ROM_MASK 0x0fffff
206 /* RAM size 4 Mbyte */
207 #define RAM_START 0x02000000
208 #define RAM_END 0x02400000
209 #define RAM_MASK 0x003fffff
211 /* SPARClite boards all seem to have RAM at the same place. */
212 #define RAM_START_SLITE 0x40000000
213 #define RAM_END_SLITE 0x40400000
214 #define RAM_MASK_SLITE 0x003fffff
216 /* Memory support variables */
218 static uint32 mem_ramr_ws; /* RAM read waitstates */
219 static uint32 mem_ramw_ws; /* RAM write waitstates */
220 static uint32 mem_romr_ws; /* ROM read waitstates */
221 static uint32 mem_romw_ws; /* ROM write waitstates */
222 static uint32 mem_ramstart; /* RAM start */
223 static uint32 mem_ramend; /* RAM end */
224 static uint32 mem_rammask; /* RAM address mask */
225 static uint32 mem_ramsz; /* RAM size */
226 static uint32 mem_romsz; /* ROM size */
227 static uint32 mem_accprot; /* RAM write protection enabled */
228 static uint32 mem_blockprot; /* RAM block write protection enabled */
230 static unsigned char romb[ROM_SZ];
231 static unsigned char ramb[RAM_END - RAM_START];
234 /* UART support variables */
236 static int32 fd1, fd2; /* file descriptor for input file */
237 static int32 Ucontrol; /* UART status register */
238 static unsigned char aq[UARTBUF], bq[UARTBUF];
239 static int32 anum, aind = 0;
240 static int32 bnum, bind = 0;
241 static char wbufa[UARTBUF], wbufb[UARTBUF];
242 static unsigned wnuma;
243 static unsigned wnumb;
244 static FILE *f1in, *f1out, *f2in, *f2out;
245 static struct termios ioc1, ioc2, iocold1, iocold2;
246 static int f1open = 0, f2open = 0;
248 static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
249 static uint32 uart_stat_reg;
250 static uint32 uarta_data, uartb_data;
257 /* Forward declarations */
259 static void decode_ersr (void);
261 static void iucomperr (void);
263 static void mecparerror (void);
264 static void decode_memcfg (void);
265 static void decode_wcr (void);
266 static void decode_mcr (void);
267 static void close_port (void);
268 static void mec_reset (void);
269 static void mec_intack (int32 level);
270 static void chk_irq (void);
271 static void mec_irq (int32 level);
272 static void set_sfsr (uint32 fault, uint32 addr,
273 uint32 asi, uint32 read);
274 static int32 mec_read (uint32 addr, uint32 asi, uint32 *data);
275 static int mec_write (uint32 addr, uint32 data);
276 static void port_init (void);
277 static uint32 read_uart (uint32 addr);
278 static void write_uart (uint32 addr, uint32 data);
279 static void flush_uart (void);
280 static void uarta_tx (void);
281 static void uartb_tx (void);
282 static void uart_rx (caddr_t arg);
283 static void uart_intr (caddr_t arg);
284 static void uart_irq_start (void);
285 static void wdog_intr (caddr_t arg);
286 static void wdog_start (void);
287 static void rtc_intr (caddr_t arg);
288 static void rtc_start (void);
289 static uint32 rtc_counter_read (void);
290 static void rtc_scaler_set (uint32 val);
291 static void rtc_reload_set (uint32 val);
292 static void gpt_intr (caddr_t arg);
293 static void gpt_start (void);
294 static uint32 gpt_counter_read (void);
295 static void gpt_scaler_set (uint32 val);
296 static void gpt_reload_set (uint32 val);
297 static void timer_ctrl (uint32 val);
298 static unsigned char *
299 get_mem_ptr (uint32 addr, uint32 size);
301 static void fetch_bytes (int asi, unsigned char *mem,
302 uint32 *data, int sz);
304 static void store_bytes (unsigned char *mem, uint32 *data, int sz);
317 /* Power-on reset init */
330 if (mec_ersr & 0x01) {
331 if (!(mec_mcr & 0x20)) {
332 if (mec_mcr & 0x40) {
336 printf("Error manager reset - IU in error mode\n");
341 printf("Error manager halt - IU in error mode\n");
346 if (mec_ersr & 0x04) {
347 if (!(mec_mcr & 0x200)) {
348 if (mec_mcr & 0x400) {
352 printf("Error manager reset - IU comparison error\n");
357 printf("Error manager halt - IU comparison error\n");
362 if (mec_ersr & 0x20) {
363 if (!(mec_mcr & 0x2000)) {
364 if (mec_mcr & 0x4000) {
368 printf("Error manager reset - MEC hardware error\n");
373 printf("Error manager halt - MEC hardware error\n");
397 /* IU error mode manager */
409 /* Check memory settings */
414 if (rom8) mec_memcfg &= ~0x20000;
415 else mec_memcfg |= 0x20000;
417 mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
418 mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7);
420 if (sparclite_board) {
421 mem_ramstart = RAM_START_SLITE;
422 mem_ramend = RAM_END_SLITE;
423 mem_rammask = RAM_MASK_SLITE;
426 mem_ramstart = RAM_START;
427 mem_ramend = RAM_END;
428 mem_rammask = RAM_MASK;
431 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
432 mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
438 mem_ramr_ws = mec_wcr & 3;
439 mem_ramw_ws = (mec_wcr >> 2) & 3;
440 mem_romr_ws = (mec_wcr >> 4) & 0x0f;
442 if (mem_romr_ws > 0 ) mem_romr_ws--;
443 mem_romr_ws = 5 + (4*mem_romr_ws);
445 mem_romw_ws = (mec_wcr >> 8) & 0x0f;
447 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
448 mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
454 mem_accprot = (mec_wpr[0] | mec_wpr[1]);
455 mem_blockprot = (mec_mcr >> 3) & 1;
456 if (sis_verbose && mem_accprot)
457 printf("Memory block write protection enabled\n");
458 if (mec_mcr & 0x08000) {
462 if (sis_verbose && (mec_mcr & 2))
463 printf("Software reset enabled\n");
464 if (sis_verbose && (mec_mcr & 1))
465 printf("Power-down mode enabled\n");
468 /* Flush ports when simulator stops */
479 sim_stop(SIM_DESC sd)
488 if (f1open && f1in != stdin)
490 if (f2open && f2in != stdin)
506 for (i = 0; i < 2; i++)
507 mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
508 mec_mcr = 0x01350014;
517 mec_memcfg = 0x10000;
519 mec_ersr = 0; /* MEC error and status register */
520 mec_tcr = 0; /* MEC test comtrol register */
528 anum = aind = bnum = bind = 0;
530 uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
531 uarta_data = uartb_data = UART_THE | UART_TSE;
533 rtc_counter = 0xffffffff;
534 rtc_reload = 0xffffffff;
540 gpt_counter = 0xffffffff;
541 gpt_reload = 0xffffffff;
548 wdog_rst_delay = 255;
549 wdog_counter = 0xffff;
568 printf("interrupt %d acknowledged\n", level);
569 irq_test = mec_tcr & 0x80000;
570 if ((irq_test) && (mec_ifr & (1 << level)))
571 mec_ifr &= ~(1 << level);
573 mec_ipr &= ~(1 << level);
585 if (mec_tcr & 0x80000) itmp = mec_ifr;
587 itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
590 for (i = 15; i > 0; i--) {
591 if (((itmp >> i) & 1) != 0) {
592 if ((sis_verbose) && (i > old_irl))
593 printf("IU irl: %d\n", i);
595 set_int(i, mec_intack, i);
606 mec_ipr |= (1 << level);
611 set_sfsr(fault, addr, asi, read)
617 if ((asi == 0xa) || (asi == 0xb)) {
619 mec_sfsr = (fault << 3) | (!read << 15);
620 mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
633 mec_read(addr, asi, data)
639 switch (addr & 0x0ff) {
641 case MEC_MCR: /* 0x00 */
645 case MEC_MEMCFG: /* 0x10 */
650 *data = mec_iocr; /* 0x14 */
653 case MEC_SSA1: /* 0x20 */
654 *data = mec_ssa[0] | (mec_wpr[0] << 23);
656 case MEC_SEA1: /* 0x24 */
659 case MEC_SSA2: /* 0x28 */
660 *data = mec_ssa[1] | (mec_wpr[1] << 23);
662 case MEC_SEA2: /* 0x2c */
666 case MEC_ISR: /* 0x44 */
670 case MEC_IPR: /* 0x48 */
674 case MEC_IMR: /* 0x4c */
678 case MEC_IFR: /* 0x54 */
682 case MEC_RTC_COUNTER: /* 0x80 */
683 *data = rtc_counter_read();
685 case MEC_RTC_SCALER: /* 0x84 */
687 *data = rtc_scaler - (now() - rtc_scaler_start);
692 case MEC_GPT_COUNTER: /* 0x88 */
693 *data = gpt_counter_read();
696 case MEC_GPT_SCALER: /* 0x8c */
698 *data = gpt_scaler - (now() - gpt_scaler_start);
704 case MEC_SFSR: /* 0xA0 */
708 case MEC_FFAR: /* 0xA4 */
715 strcpy(fname, "simload");
716 find = bfd_load(fname);
724 case MEC_ERSR: /* 0xB0 */
728 case MEC_TCR: /* 0xD0 */
732 case MEC_UARTA: /* 0xE0 */
733 case MEC_UARTB: /* 0xE4 */
735 set_sfsr(MEC_ACC, addr, asi, 1);
738 *data = read_uart(addr);
741 case MEC_UART_CTRL: /* 0xE8 */
743 *data = read_uart(addr);
747 set_sfsr(MEC_ACC, addr, asi, 1);
755 mec_write(addr, data)
760 printf("MEC write a: %08x, d: %08x\n",addr,data);
761 switch (addr & 0x0ff) {
766 if (mec_mcr & 0x08000) mecparerror();
774 printf(" Software reset issued\n");
780 if (mec_iocr & 0xC0C0C0C0) mecparerror();
783 case MEC_SSA1: /* 0x20 */
784 if (data & 0xFE000000) mecparerror();
785 mec_ssa[0] = data & 0x7fffff;
786 mec_wpr[0] = (data >> 23) & 0x03;
787 mem_accprot = mec_wpr[0] || mec_wpr[1];
788 if (sis_verbose && mec_wpr[0])
789 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
790 mec_ssa[0] << 2, mec_sea[0] << 2);
792 case MEC_SEA1: /* 0x24 */
793 if (data & 0xFF800000) mecparerror();
794 mec_sea[0] = data & 0x7fffff;
796 case MEC_SSA2: /* 0x28 */
797 if (data & 0xFE000000) mecparerror();
798 mec_ssa[1] = data & 0x7fffff;
799 mec_wpr[1] = (data >> 23) & 0x03;
800 mem_accprot = mec_wpr[0] || mec_wpr[1];
801 if (sis_verbose && mec_wpr[1])
802 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
803 mec_ssa[1] << 2, mec_sea[1] << 2);
805 case MEC_SEA2: /* 0x2c */
806 if (data & 0xFF800000) mecparerror();
807 mec_sea[1] = data & 0x7fffff;
812 if (data & 0xFFFFFF00) mecparerror();
814 if (data & 0xFF00FF00) mecparerror();
815 write_uart(addr, data);
819 gpt_reload_set(data);
823 if (data & 0xFFFF0000) mecparerror();
824 gpt_scaler_set(data);
828 if (data & 0xFFFFF0F0) mecparerror();
833 rtc_reload_set(data);
837 if (data & 0xFFFFFF00) mecparerror();
838 rtc_scaler_set(data);
841 case MEC_SFSR: /* 0xA0 */
842 if (data & 0xFFFF0880) mecparerror();
847 if (data & 0xFFFFE000) mecparerror();
851 case MEC_IMR: /* 0x4c */
853 if (data & 0xFFFF8001) mecparerror();
854 mec_imr = data & 0x7ffe;
858 case MEC_ICR: /* 0x50 */
860 if (data & 0xFFFF0001) mecparerror();
861 mec_ipr &= ~data & 0x0fffe;
865 case MEC_IFR: /* 0x54 */
867 if (mec_tcr & 0x080000) {
868 if (data & 0xFFFF0001) mecparerror();
869 mec_ifr = data & 0xfffe;
874 fname[find++] = (char) data;
878 case MEC_MEMCFG: /* 0x10 */
879 if (data & 0xC0E08000) mecparerror();
882 if (mec_memcfg & 0xc0e08000)
886 case MEC_WCR: /* 0x18 */
891 case MEC_ERSR: /* 0xB0 */
892 if (mec_tcr & 0x100000)
893 if (data & 0xFFFFEFC0) mecparerror();
894 mec_ersr = data & 0x103f;
897 case MEC_TCR: /* 0xD0 */
898 if (data & 0xFFE1FFC0) mecparerror();
899 mec_tcr = data & 0x1e003f;
902 case MEC_WDOG: /* 0x60 */
903 wdog_scaler = (data >> 16) & 0x0ff;
904 wdog_counter = data & 0x0ffff;
905 wdog_rst_delay = data >> 24;
907 if (wdog_status == stopped)
909 wdog_status = enabled;
912 case MEC_TRAPD: /* 0x64 */
913 if (wdog_status == init) {
914 wdog_status = disabled;
916 printf("Watchdog disabled\n");
926 set_sfsr(MEC_ACC, addr, 0xb, 0);
936 static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
942 return; /* do nothing */
944 tcsetattr(0, TCSANOW, &ioc1);
946 tcsetattr(0, TCSANOW, &ioc2);
953 return; /* do nothing */
955 tcsetattr(0, TCSANOW, &iocold1);
957 tcsetattr(0, TCSANOW, &iocold2);
960 #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
962 ? (0) /* no bytes read, no delay */ \
963 : read( _fd_, _buf_, _len_ ) )
981 if (uart_dev1[0] != 0)
982 if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
983 printf("Warning, couldn't open output device %s\n", uart_dev1);
986 printf("serial port A on %s\n", uart_dev1);
987 f1in = f1out = fdopen(fd1, "r+");
991 if (f1in) ifd1 = fileno(f1in);
994 printf("serial port A on stdin/stdout\n");
996 tcgetattr(ifd1, &ioc1);
998 ioc1.c_lflag &= ~(ICANON | ECHO);
1000 ioc1.c_cc[VTIME] = 0;
1006 ofd1 = fileno(f1out);
1007 if (!dumbio && ofd1 == 1) setbuf(f1out, NULL);
1010 if (uart_dev2[0] != 0)
1011 if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
1012 printf("Warning, couldn't open output device %s\n", uart_dev2);
1015 printf("serial port B on %s\n", uart_dev2);
1016 f2in = f2out = fdopen(fd2, "r+");
1017 setbuf(f2out, NULL);
1020 if (f2in) ifd2 = fileno(f2in);
1023 printf("serial port B on stdin/stdout\n");
1025 tcgetattr(ifd2, &ioc2);
1027 ioc2.c_lflag &= ~(ICANON | ECHO);
1028 ioc2.c_cc[VMIN] = 0;
1029 ioc2.c_cc[VTIME] = 0;
1035 ofd2 = fileno(f2out);
1036 if (!dumbio && ofd2 == 1) setbuf(f2out, NULL);
1051 switch (addr & 0xff) {
1053 case 0xE0: /* UART 1 */
1058 if ((aind + 1) < anum)
1060 return (0x700 | (uint32) aq[aind++]);
1063 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1067 if ((aind + 1) < anum)
1069 return (0x700 | (uint32) aq[aind++]);
1071 return (0x600 | (uint32) aq[aind]);
1077 uarta_data &= ~UART_DR;
1078 uart_stat_reg &= ~UARTA_DR;
1086 case 0xE4: /* UART 2 */
1090 if ((bind + 1) < bnum)
1092 return (0x700 | (uint32) bq[bind++]);
1095 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1099 if ((bind + 1) < bnum)
1101 return (0x700 | (uint32) bq[bind++]);
1103 return (0x600 | (uint32) bq[bind]);
1109 uartb_data &= ~UART_DR;
1110 uart_stat_reg &= ~UARTB_DR;
1118 case 0xE8: /* UART status register */
1124 Ucontrol |= 0x00000001;
1127 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1130 Ucontrol |= 0x00000001;
1136 Ucontrol |= 0x00010000;
1139 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1142 Ucontrol |= 0x00010000;
1148 Ucontrol |= 0x00060006;
1151 return (uart_stat_reg);
1159 printf("Read from unimplemented MEC register (%x)\n", addr);
1166 write_uart(addr, data)
1172 c = (unsigned char) data;
1173 switch (addr & 0xff) {
1175 case 0xE0: /* UART A */
1178 if (wnuma < UARTBUF)
1182 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1188 if (uart_stat_reg & UARTA_SRE) {
1190 uart_stat_reg &= ~UARTA_SRE;
1191 event(uarta_tx, 0, UART_TX_TIME);
1194 uart_stat_reg &= ~UARTA_HRE;
1199 case 0xE4: /* UART B */
1202 if (wnumb < UARTBUF)
1206 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1212 if (uart_stat_reg & UARTB_SRE) {
1214 uart_stat_reg &= ~UARTB_SRE;
1215 event(uartb_tx, 0, UART_TX_TIME);
1218 uart_stat_reg &= ~UARTB_HRE;
1222 case 0xE8: /* UART status register */
1224 if (data & UARTA_CLR) {
1225 uart_stat_reg &= 0xFFFF0000;
1226 uart_stat_reg |= UARTA_SRE | UARTA_HRE;
1228 if (data & UARTB_CLR) {
1229 uart_stat_reg &= 0x0000FFFF;
1230 uart_stat_reg |= UARTB_SRE | UARTB_HRE;
1236 printf("Write to unimplemented MEC register (%x)\n", addr);
1244 while (wnuma && f1open)
1245 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1246 while (wnumb && f2open)
1247 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1256 while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
1257 if (uart_stat_reg & UARTA_HRE) {
1258 uart_stat_reg |= UARTA_SRE;
1260 uarta_sreg = uarta_hreg;
1261 uart_stat_reg |= UARTA_HRE;
1262 event(uarta_tx, 0, UART_TX_TIME);
1270 while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
1271 if (uart_stat_reg & UARTB_HRE) {
1272 uart_stat_reg |= UARTB_SRE;
1274 uartb_sreg = uartb_hreg;
1275 uart_stat_reg |= UARTB_HRE;
1276 event(uartb_tx, 0, UART_TX_TIME);
1291 rsize = DO_STDIO_READ(ifd1, &rxd, 1);
1293 uarta_data = UART_DR | rxd;
1294 if (uart_stat_reg & UARTA_HRE)
1295 uarta_data |= UART_THE;
1296 if (uart_stat_reg & UARTA_SRE)
1297 uarta_data |= UART_TSE;
1298 if (uart_stat_reg & UARTA_DR) {
1299 uart_stat_reg |= UARTA_OR;
1300 mec_irq(7); /* UART error interrupt */
1302 uart_stat_reg |= UARTA_DR;
1307 rsize = DO_STDIO_READ(ifd2, &rxd, 1);
1309 uartb_data = UART_DR | rxd;
1310 if (uart_stat_reg & UARTB_HRE)
1311 uartb_data |= UART_THE;
1312 if (uart_stat_reg & UARTB_SRE)
1313 uartb_data |= UART_TSE;
1314 if (uart_stat_reg & UARTB_DR) {
1315 uart_stat_reg |= UARTB_OR;
1316 mec_irq(7); /* UART error interrupt */
1318 uart_stat_reg |= UARTB_DR;
1321 event(uart_rx, 0, UART_RX_TIME);
1328 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1329 flush_uart(); /* Flush UART ports */
1330 event(uart_intr, 0, UART_FLUSH_TIME);
1338 event(uart_intr, 0, UART_FLUSH_TIME);
1341 event(uart_rx, 0, UART_RX_TIME);
1352 if (wdog_status == disabled) {
1353 wdog_status = stopped;
1358 event(wdog_intr, 0, wdog_scaler + 1);
1361 printf("Watchdog reset!\n");
1367 wdog_counter = wdog_rst_delay;
1368 event(wdog_intr, 0, wdog_scaler + 1);
1377 event(wdog_intr, 0, wdog_scaler + 1);
1379 printf("Watchdog started, scaler = %d, counter = %d\n",
1380 wdog_scaler, wdog_counter);
1391 if (rtc_counter == 0) {
1395 rtc_counter = rtc_reload;
1401 event(rtc_intr, 0, rtc_scaler + 1);
1402 rtc_scaler_start = now();
1406 printf("RTC stopped\n\r");
1415 printf("RTC started (period %d)\n\r", rtc_scaler + 1);
1416 event(rtc_intr, 0, rtc_scaler + 1);
1417 rtc_scaler_start = now();
1424 return (rtc_counter);
1431 rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
1445 if (gpt_counter == 0) {
1448 gpt_counter = gpt_reload;
1454 event(gpt_intr, 0, gpt_scaler + 1);
1455 gpt_scaler_start = now();
1459 printf("GPT stopped\n\r");
1468 printf("GPT started (period %d)\n\r", gpt_scaler + 1);
1469 event(gpt_intr, 0, gpt_scaler + 1);
1470 gpt_scaler_start = now();
1477 return (gpt_counter);
1484 gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
1499 rtc_cr = ((val & TCR_TCRCR) != 0);
1500 if (val & TCR_TCRCL) {
1501 rtc_counter = rtc_reload;
1503 if (val & TCR_TCRSL) {
1505 rtc_se = ((val & TCR_TCRSE) != 0);
1506 if (rtc_se && (rtc_enabled == 0))
1509 gpt_cr = (val & TCR_GACR);
1510 if (val & TCR_GACL) {
1511 gpt_counter = gpt_reload;
1513 if (val & TCR_GACL) {
1515 gpt_se = (val & TCR_GASE) >> 2;
1516 if (gpt_se && (gpt_enabled == 0))
1521 /* Retrieve data from target memory. MEM points to location from which
1522 to read the data; DATA points to words where retrieved data will be
1523 stored in host byte order. SZ contains log(2) of the number of bytes
1524 to retrieve, and can be 0 (1 byte), 1 (one half-word), 2 (one word),
1525 or 3 (two words). */
1528 fetch_bytes (asi, mem, data, sz)
1534 if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN
1535 || asi == 8 || asi == 9) {
1538 data[1] = (((uint32) mem[7]) & 0xff) |
1539 ((((uint32) mem[6]) & 0xff) << 8) |
1540 ((((uint32) mem[5]) & 0xff) << 16) |
1541 ((((uint32) mem[4]) & 0xff) << 24);
1542 /* Fall through to 2 */
1544 data[0] = (((uint32) mem[3]) & 0xff) |
1545 ((((uint32) mem[2]) & 0xff) << 8) |
1546 ((((uint32) mem[1]) & 0xff) << 16) |
1547 ((((uint32) mem[0]) & 0xff) << 24);
1550 data[0] = (((uint32) mem[1]) & 0xff) |
1551 ((((uint32) mem[0]) & 0xff) << 8);
1554 data[0] = mem[0] & 0xff;
1561 data[1] = ((((uint32) mem[7]) & 0xff) << 24) |
1562 ((((uint32) mem[6]) & 0xff) << 16) |
1563 ((((uint32) mem[5]) & 0xff) << 8) |
1564 (((uint32) mem[4]) & 0xff);
1565 /* Fall through to 4 */
1567 data[0] = ((((uint32) mem[3]) & 0xff) << 24) |
1568 ((((uint32) mem[2]) & 0xff) << 16) |
1569 ((((uint32) mem[1]) & 0xff) << 8) |
1570 (((uint32) mem[0]) & 0xff);
1573 data[0] = ((((uint32) mem[1]) & 0xff) << 8) |
1574 (((uint32) mem[0]) & 0xff);
1577 data[0] = mem[0] & 0xff;
1584 /* Store data in target byte order. MEM points to location to store data;
1585 DATA points to words in host byte order to be stored. SZ contains log(2)
1586 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1587 2 (one word), or 3 (two words). */
1590 store_bytes (mem, data, sz)
1595 if (CURRENT_TARGET_BYTE_ORDER == LITTLE_ENDIAN) {
1598 mem[7] = (data[1] >> 24) & 0xff;
1599 mem[6] = (data[1] >> 16) & 0xff;
1600 mem[5] = (data[1] >> 8) & 0xff;
1601 mem[4] = data[1] & 0xff;
1602 /* Fall through to 2 */
1604 mem[3] = (data[0] >> 24) & 0xff;
1605 mem[2] = (data[0] >> 16) & 0xff;
1606 /* Fall through to 1 */
1608 mem[1] = (data[0] >> 8) & 0xff;
1609 /* Fall through to 0 */
1611 mem[0] = data[0] & 0xff;
1617 mem[7] = data[1] & 0xff;
1618 mem[6] = (data[1] >> 8) & 0xff;
1619 mem[5] = (data[1] >> 16) & 0xff;
1620 mem[4] = (data[1] >> 24) & 0xff;
1621 /* Fall through to 2 */
1623 mem[3] = data[0] & 0xff;
1624 mem[2] = (data[0] >> 8) & 0xff;
1625 mem[1] = (data[0] >> 16) & 0xff;
1626 mem[0] = (data[0] >> 24) & 0xff;
1629 mem[1] = data[0] & 0xff;
1630 mem[0] = (data[0] >> 8) & 0xff;
1633 mem[0] = data[0] & 0xff;
1641 /* Memory emulation */
1644 memory_read(asi, addr, data, sz, ws)
1656 printf("Inserted MEC error %d\n",errmec);
1657 set_sfsr(errmec, addr, asi, 1);
1658 if (errmec == 5) mecparerror();
1659 if (errmec == 6) iucomperr();
1665 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1666 fetch_bytes (asi, &ramb[addr & mem_rammask], data, sz);
1669 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1670 mexc = mec_read(addr, asi, data);
1672 set_sfsr(MEC_ACC, addr, asi, 1);
1682 if ((addr < 0x100000) ||
1683 ((addr>= 0x80000000) && (addr < 0x80100000))) {
1684 fetch_bytes (asi, &romb[addr & ROM_MASK], data, sz);
1687 } else if ((addr >= 0x10000000) &&
1688 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1689 (mec_iocr & 0x10)) {
1694 } else if (addr < mem_romsz) {
1695 fetch_bytes (asi, &romb[addr], data, sz);
1700 } else if (addr < mem_romsz) {
1701 fetch_bytes (asi, &romb[addr], data, sz);
1708 printf("Memory exception at %x (illegal address)\n", addr);
1709 set_sfsr(UIMP_ACC, addr, asi, 1);
1715 memory_write(asi, addr, data, sz, ws)
1733 printf("Inserted MEC error %d\n",errmec);
1734 set_sfsr(errmec, addr, asi, 0);
1735 if (errmec == 5) mecparerror();
1736 if (errmec == 6) iucomperr();
1742 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1745 waddr = (addr & 0x7fffff) >> 2;
1746 for (i = 0; i < 2; i++)
1748 (((asi == 0xa) && (mec_wpr[i] & 1)) ||
1749 ((asi == 0xb) && (mec_wpr[i] & 2))) &&
1750 ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
1752 if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
1753 ((!mem_blockprot) &&
1754 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
1757 printf("Memory access protection error at 0x%08x\n", addr);
1758 set_sfsr(PROT_EXC, addr, asi, 0);
1764 store_bytes (&ramb[addr & mem_rammask], data, sz);
1769 *ws = mem_ramw_ws + 3;
1775 *ws = 2 * mem_ramw_ws + STD_WS;
1779 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1780 if ((sz != 2) || (asi != 0xb)) {
1781 set_sfsr(MEC_ACC, addr, asi, 0);
1785 mexc = mec_write(addr, *data);
1787 set_sfsr(MEC_ACC, addr, asi, 0);
1798 ((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
1800 *ws = sz == 3 ? 8 : 4;
1801 store_bytes (&romb[addr], data, sz);
1803 } else if ((addr >= 0x10000000) &&
1804 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1805 (mec_iocr & 0x10)) {
1806 erareg = *data & 0x0e;
1810 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1811 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1812 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1814 *ws = mem_romw_ws + 1;
1816 *ws += mem_romw_ws + STD_WS;
1817 store_bytes (&romb[addr], data, sz);
1821 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1822 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1823 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1825 *ws = mem_romw_ws + 1;
1827 *ws += mem_romw_ws + STD_WS;
1828 store_bytes (&romb[addr], data, sz);
1836 set_sfsr(UIMP_ACC, addr, asi, 0);
1840 static unsigned char *
1841 get_mem_ptr(addr, size)
1845 if ((addr + size) < ROM_SZ) {
1846 return (&romb[addr]);
1847 } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
1848 return (&ramb[addr & mem_rammask]);
1852 else if ((era) && ((addr <0x100000) ||
1853 ((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
1854 return (&romb[addr & ROM_MASK]);
1858 return ((char *) -1);
1862 sis_memory_write(addr, data, length)
1864 const unsigned char *data;
1869 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1872 memcpy(mem, data, length);
1877 sis_memory_read(addr, data, length)
1884 if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
1887 memcpy(data, mem, length);