9 #include "sys/syscall.h"
36 static void trace_input PARAMS ((char *name,
41 static void trace_output PARAMS ((enum op_types result));
43 #ifndef SIZE_INSTRUCTION
44 #define SIZE_INSTRUCTION 10
48 #define SIZE_OPERANDS 24
52 #define SIZE_VALUES 13
56 trace_input (name, in1, in2, in3)
70 if ((d10v_debug & DEBUG_TRACE) == 0)
73 switch (State.ins_type)
76 case INS_UNKNOWN: type = " ?"; break;
77 case INS_LEFT: type = " L"; break;
78 case INS_RIGHT: type = " R"; break;
79 case INS_LEFT_PARALLEL: type = "*L"; break;
80 case INS_RIGHT_PARALLEL: type = "*R"; break;
81 case INS_LONG: type = " B"; break;
84 (*d10v_callback->printf_filtered) (d10v_callback,
87 SIZE_INSTRUCTION, name);
94 for (i = 0; i < 3; i++)
105 sprintf (p, "%sr%d", comma, OP[i]);
113 sprintf (p, "%scr%d", comma, OP[i]);
119 case OP_ACCUM_OUTPUT:
120 case OP_ACCUM_REVERSE:
121 sprintf (p, "%sa%d", comma, OP[i]);
127 sprintf (p, "%s%d", comma, OP[i]);
133 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
139 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
145 sprintf (p, "%s@r%d", comma, OP[i]);
151 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
157 sprintf (p, "%s@r%d+", comma, OP[i]);
163 sprintf (p, "%s@r%d-", comma, OP[i]);
169 sprintf (p, "%s@-r%d", comma, OP[i]);
177 sprintf (p, "%sf0", comma);
180 sprintf (p, "%sf1", comma);
183 sprintf (p, "%sc", comma);
191 if ((d10v_debug & DEBUG_VALUES) == 0)
195 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
200 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
203 for (i = 0; i < 3; i++)
209 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
215 case OP_ACCUM_OUTPUT:
217 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
225 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
226 (uint16)State.regs[OP[i]]);
230 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
231 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
236 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
237 (uint16)State.cregs[OP[i]]);
241 case OP_ACCUM_REVERSE:
242 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
243 ((int)(State.a[OP[i]] >> 32) & 0xff),
244 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
248 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
253 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
254 (uint16)SEXT4(OP[i]));
258 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
259 (uint16)SEXT3(OP[i]));
264 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
268 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
272 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
278 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
280 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
281 (uint16)State.regs[OP[++i]]);
289 trace_output (result)
290 enum op_types result;
292 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
304 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
305 (uint16)State.regs[OP[0]],
306 State.F0 != 0, State.F1 != 0, State.C != 0);
311 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
312 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
313 State.F0 != 0, State.F1 != 0, State.C != 0);
318 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
319 (uint16)State.cregs[OP[0]],
320 State.F0 != 0, State.F1 != 0, State.C != 0);
324 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
325 (uint16)State.cregs[OP[1]],
326 State.F0 != 0, State.F1 != 0, State.C != 0);
330 case OP_ACCUM_OUTPUT:
331 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
332 ((int)(State.a[OP[0]] >> 32) & 0xff),
333 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
334 State.F0 != 0, State.F1 != 0, State.C != 0);
337 case OP_ACCUM_REVERSE:
338 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
339 ((int)(State.a[OP[1]] >> 32) & 0xff),
340 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
341 State.F0 != 0, State.F1 != 0, State.C != 0);
346 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
347 State.F0 != 0, State.F1 != 0, State.C != 0);
354 #define trace_input(NAME, IN1, IN2, IN3)
355 #define trace_output(RESULT)
362 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
364 if ((int16)(State.regs[OP[0]]) < 0)
366 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
371 trace_output (OP_REG);
380 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
382 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
384 if (State.a[OP[0]] < 0 )
386 tmp = -State.a[OP[0]];
390 State.a[OP[0]] = MAX32;
391 else if (tmp < MIN32)
392 State.a[OP[0]] = MIN32;
394 State.a[OP[0]] = tmp & MASK40;
397 State.a[OP[0]] = tmp & MASK40;
402 trace_output (OP_ACCUM);
409 uint16 tmp = State.regs[OP[0]];
410 trace_input ("add", OP_REG, OP_REG, OP_VOID);
411 State.regs[OP[0]] += State.regs[OP[1]];
412 if ( tmp > State.regs[OP[0]])
416 trace_output (OP_REG);
424 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
426 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
430 State.a[OP[0]] = MAX32;
431 else if ( tmp < MIN32)
432 State.a[OP[0]] = MIN32;
434 State.a[OP[0]] = tmp & MASK40;
437 State.a[OP[0]] = tmp & MASK40;
438 trace_output (OP_ACCUM);
446 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
448 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
452 State.a[OP[0]] = MAX32;
453 else if ( tmp < MIN32)
454 State.a[OP[0]] = MIN32;
456 State.a[OP[0]] = tmp & MASK40;
459 State.a[OP[0]] = tmp & MASK40;
460 trace_output (OP_ACCUM);
468 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
469 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
471 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
473 if ( (tmp < tmp1) || (tmp < tmp2) )
477 State.regs[OP[0]] = tmp >> 16;
478 State.regs[OP[0]+1] = tmp & 0xFFFF;
479 trace_output (OP_DREG);
486 uint16 tmp = State.regs[OP[0]];
487 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
489 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
490 if ( tmp > State.regs[OP[0]])
494 trace_output (OP_REG);
502 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
504 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
505 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
506 State.regs[OP[0]+1] = tmp & 0xffff;
507 trace_output (OP_DREG);
515 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
517 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
518 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
519 State.regs[OP[0]+1] = tmp & 0xffff;
520 trace_output (OP_DREG);
530 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
531 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
534 State.regs[OP[0]] = 0x7fff;
535 State.regs[OP[0]+1] = 0xffff;
538 else if (tmp < MIN32)
540 State.regs[OP[0]] = 0x8000;
541 State.regs[OP[0]+1] = 0;
546 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
547 State.regs[OP[0]+1] = tmp & 0xffff;
550 trace_output (OP_DREG);
560 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
561 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
564 State.regs[OP[0]] = 0x7fff;
565 State.regs[OP[0]+1] = 0xffff;
568 else if (tmp < MIN32)
570 State.regs[OP[0]] = 0x8000;
571 State.regs[OP[0]+1] = 0;
576 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
577 State.regs[OP[0]+1] = tmp & 0xffff;
580 trace_output (OP_DREG);
587 uint tmp = State.regs[OP[0]];
590 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
591 State.regs[OP[0]] += OP[1];
592 if (tmp > State.regs[OP[0]])
596 trace_output (OP_REG);
603 trace_input ("and", OP_REG, OP_REG, OP_VOID);
604 State.regs[OP[0]] &= State.regs[OP[1]];
605 trace_output (OP_REG);
612 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
613 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
614 trace_output (OP_REG);
621 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
622 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
623 trace_output (OP_REG);
630 trace_input ("bl.s", OP_CONSTANT16, OP_VOID, OP_VOID);
631 State.regs[13] = PC+1;
633 trace_output (OP_VOID);
640 trace_input ("bl.l", OP_CONSTANT16, OP_VOID, OP_VOID);
641 State.regs[13] = PC+1;
643 trace_output (OP_VOID);
650 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
651 State.regs[OP[0]] ^= 0x8000 >> OP[1];
652 trace_output (OP_REG);
659 trace_input ("bra.s", OP_CONSTANT16, OP_VOID, OP_VOID);
661 trace_output (OP_VOID);
668 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
670 trace_output (OP_VOID);
677 trace_input ("brf0f.s", OP_CONSTANT16, OP_VOID, OP_VOID);
680 trace_output (OP_FLAG);
687 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
690 trace_output (OP_FLAG);
697 trace_input ("brf0t.s", OP_CONSTANT16, OP_VOID, OP_VOID);
700 trace_output (OP_FLAG);
707 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
710 trace_output (OP_FLAG);
717 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
718 State.regs[OP[0]] |= 0x8000 >> OP[1];
719 trace_output (OP_REG);
726 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
728 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
729 trace_output (OP_FLAG);
736 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
738 trace_output (OP_ACCUM);
745 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
747 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
748 trace_output (OP_FLAG);
755 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
757 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
758 trace_output (OP_FLAG);
765 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
767 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
768 trace_output (OP_FLAG);
775 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
777 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
778 trace_output (OP_FLAG);
785 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT16, OP_VOID);
787 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
788 trace_output (OP_FLAG);
795 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
797 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
798 trace_output (OP_FLAG);
805 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
807 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
808 trace_output (OP_FLAG);
815 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
817 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
818 trace_output (OP_FLAG);
825 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
827 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
828 trace_output (OP_FLAG);
835 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
837 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
838 trace_output (OP_FLAG);
847 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
861 trace_output (OP_FLAG);
868 d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC);
869 State.exception = SIGTRAP;
876 uint16 foo, tmp, tmpf;
878 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
879 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
880 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
881 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
882 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
883 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
884 trace_output (OP_DREG);
891 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
892 State.exe = (State.F0 == 0);
893 trace_output (OP_FLAG);
900 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
901 State.exe = (State.F0 != 0);
902 trace_output (OP_FLAG);
909 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
910 State.exe = (State.F1 == 0);
911 trace_output (OP_FLAG);
918 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
919 State.exe = (State.F1 != 0);
920 trace_output (OP_FLAG);
927 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
928 State.exe = (State.F0 == 0) & (State.F1 == 0);
929 trace_output (OP_FLAG);
936 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
937 State.exe = (State.F0 == 0) & (State.F1 != 0);
938 trace_output (OP_FLAG);
945 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
946 State.exe = (State.F0 != 0) & (State.F1 == 0);
947 trace_output (OP_FLAG);
954 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
955 State.exe = (State.F0 != 0) & (State.F1 != 0);
956 trace_output (OP_FLAG);
966 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
967 if (((int16)State.regs[OP[1]]) >= 0)
968 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
970 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
977 State.regs[OP[0]] = i-1;
978 trace_output (OP_REG);
983 State.regs[OP[0]] = 16;
984 trace_output (OP_REG);
994 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
995 if (SEXT40(State.a[OP[1]]) >= 0)
996 tmp = State.a[OP[1]];
998 tmp = ~(State.a[OP[1]]);
1000 foo = 0x4000000000LL;
1005 State.regs[OP[0]] = i-9;
1006 trace_output (OP_REG);
1011 State.regs[OP[0]] = 16;
1012 trace_output (OP_REG);
1019 trace_input ("jl", OP_REG, OP_VOID, OP_VOID);
1020 State.regs[13] = PC+1;
1021 PC = State.regs[OP[0]];
1022 trace_output (OP_VOID);
1029 trace_input ("jmp", OP_REG, OP_VOID, OP_VOID);
1030 PC = State.regs[OP[0]];
1031 trace_output (OP_VOID);
1038 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1039 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1040 trace_output (OP_REG);
1047 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1048 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1049 INC_ADDR(State.regs[OP[1]],-2);
1050 trace_output (OP_REG);
1057 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1058 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1059 INC_ADDR(State.regs[OP[1]],2);
1060 trace_output (OP_REG);
1067 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1068 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1069 trace_output (OP_REG);
1076 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1077 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1078 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
1079 trace_output (OP_DREG);
1086 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1087 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1088 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1089 INC_ADDR(State.regs[OP[1]],-4);
1090 trace_output (OP_DREG);
1097 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1098 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1099 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1100 INC_ADDR(State.regs[OP[1]],4);
1101 trace_output (OP_REG);
1108 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1109 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1110 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
1111 trace_output (OP_REG);
1118 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1119 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1120 SEXT8 (State.regs[OP[0]]);
1121 trace_output (OP_REG);
1128 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1129 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1130 SEXT8 (State.regs[OP[0]]);
1131 trace_output (OP_REG);
1138 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1139 State.regs[OP[0]] = SEXT4(OP[1]);
1140 trace_output (OP_REG);
1147 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1148 State.regs[OP[0]] = OP[1];
1149 trace_output (OP_REG);
1156 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1157 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1158 trace_output (OP_REG);
1165 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1166 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1167 trace_output (OP_REG);
1176 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1177 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1180 tmp = SEXT40( (tmp << 1) & MASK40);
1182 if (State.ST && tmp > MAX32)
1185 tmp += SEXT40(State.a[OP[0]]);
1189 State.a[OP[0]] = MAX32;
1190 else if (tmp < MIN32)
1191 State.a[OP[0]] = MIN32;
1193 State.a[OP[0]] = tmp & MASK40;
1196 State.a[OP[0]] = tmp & MASK40;
1197 trace_output (OP_ACCUM);
1206 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1207 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1209 tmp = SEXT40( (tmp << 1) & MASK40);
1211 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1212 trace_output (OP_ACCUM);
1221 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1222 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1224 tmp = SEXT40( (tmp << 1) & MASK40);
1225 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1226 trace_output (OP_ACCUM);
1233 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1234 State.F1 = State.F0;
1235 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
1237 State.regs[OP[0]] = State.regs[OP[1]];
1242 trace_output (OP_REG);
1251 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1252 State.F1 = State.F0;
1253 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1254 if (tmp > SEXT40(State.a[OP[0]]))
1256 State.a[OP[0]] = tmp & MASK40;
1261 trace_output (OP_ACCUM);
1268 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1269 State.F1 = State.F0;
1270 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1272 State.a[OP[0]] = State.a[OP[1]];
1277 trace_output (OP_ACCUM);
1285 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1286 State.F1 = State.F0;
1287 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
1289 State.regs[OP[0]] = State.regs[OP[1]];
1294 trace_output (OP_REG);
1303 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1304 State.F1 = State.F0;
1305 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1306 if (tmp < SEXT40(State.a[OP[0]]))
1308 State.a[OP[0]] = tmp & MASK40;
1313 trace_output (OP_ACCUM);
1320 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1321 State.F1 = State.F0;
1322 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1324 State.a[OP[0]] = State.a[OP[1]];
1329 trace_output (OP_ACCUM);
1338 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1339 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1342 tmp = SEXT40 ((tmp << 1) & MASK40);
1344 if (State.ST && tmp > MAX32)
1347 tmp = SEXT40(State.a[OP[0]]) - tmp;
1351 State.a[OP[0]] = MAX32;
1352 else if (tmp < MIN32)
1353 State.a[OP[0]] = MIN32;
1355 State.a[OP[0]] = tmp & MASK40;
1358 State.a[OP[0]] = tmp & MASK40;
1359 trace_output (OP_ACCUM);
1368 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1369 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1371 tmp = SEXT40( (tmp << 1) & MASK40);
1373 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1374 trace_output (OP_ACCUM);
1383 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1384 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1386 tmp = SEXT40( (tmp << 1) & MASK40);
1388 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1389 trace_output (OP_ACCUM);
1396 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1397 State.regs[OP[0]] *= State.regs[OP[1]];
1398 trace_output (OP_REG);
1407 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1408 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1411 tmp = SEXT40 ((tmp << 1) & MASK40);
1413 if (State.ST && tmp > MAX32)
1414 State.a[OP[0]] = MAX32;
1416 State.a[OP[0]] = tmp & MASK40;
1417 trace_output (OP_ACCUM);
1426 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1427 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1432 State.a[OP[0]] = tmp & MASK40;
1433 trace_output (OP_ACCUM);
1442 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1443 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1448 State.a[OP[0]] = tmp & MASK40;
1449 trace_output (OP_ACCUM);
1456 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1457 State.regs[OP[0]] = State.regs[OP[1]];
1458 trace_output (OP_REG);
1465 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1466 State.regs[OP[0]] = State.regs[OP[1]];
1467 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1468 trace_output (OP_DREG);
1475 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1476 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1477 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1478 trace_output (OP_DREG);
1485 trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
1486 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1487 trace_output (OP_ACCUM);
1494 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1495 State.a[OP[0]] = State.a[OP[1]];
1496 trace_output (OP_ACCUM);
1503 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1504 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1505 trace_output (OP_REG);
1512 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1514 State.regs[OP[0]] = State.regs[OP[1]];
1515 trace_output (OP_REG);
1522 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1524 State.regs[OP[0]] = State.regs[OP[1]];
1525 trace_output (OP_REG);
1532 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1533 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1534 trace_output (OP_ACCUM);
1541 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1542 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1543 trace_output (OP_REG);
1550 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1551 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1552 trace_output (OP_REG);
1559 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1562 /* PSW is treated specially */
1564 if (State.SM) PSW |= 0x8000;
1565 if (State.EA) PSW |= 0x2000;
1566 if (State.DB) PSW |= 0x1000;
1567 if (State.IE) PSW |= 0x400;
1568 if (State.RP) PSW |= 0x200;
1569 if (State.MD) PSW |= 0x100;
1570 if (State.FX) PSW |= 0x80;
1571 if (State.ST) PSW |= 0x40;
1572 if (State.F0) PSW |= 8;
1573 if (State.F1) PSW |= 4;
1574 if (State.C) PSW |= 1;
1576 State.regs[OP[0]] = State.cregs[OP[1]];
1577 trace_output (OP_REG);
1584 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1585 State.a[OP[1]] &= MASK32;
1586 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1587 trace_output (OP_ACCUM_REVERSE);
1596 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1597 tmp = State.a[OP[1]] & 0xffff;
1598 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1599 trace_output (OP_ACCUM_REVERSE);
1606 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1607 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1608 trace_output (OP_ACCUM_REVERSE);
1615 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1616 State.cregs[OP[1]] = State.regs[OP[0]];
1619 /* PSW is treated specially */
1620 State.SM = (PSW & 0x8000) ? 1 : 0;
1621 State.EA = (PSW & 0x2000) ? 1 : 0;
1622 State.DB = (PSW & 0x1000) ? 1 : 0;
1623 State.IE = (PSW & 0x400) ? 1 : 0;
1624 State.RP = (PSW & 0x200) ? 1 : 0;
1625 State.MD = (PSW & 0x100) ? 1 : 0;
1626 State.FX = (PSW & 0x80) ? 1 : 0;
1627 State.ST = (PSW & 0x40) ? 1 : 0;
1628 State.F0 = (PSW & 8) ? 1 : 0;
1629 State.F1 = (PSW & 4) ? 1 : 0;
1631 if (State.ST && !State.FX)
1633 (*d10v_callback->printf_filtered) (d10v_callback,
1634 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1636 State.exception = SIGILL;
1639 trace_output (OP_CR_REVERSE);
1646 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1647 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1648 trace_output (OP_REG);
1655 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1656 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1657 trace_output (OP_REG);
1666 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1667 tmp = -SEXT40(State.a[OP[0]]);
1671 State.a[OP[0]] = MAX32;
1672 else if (tmp < MIN32)
1673 State.a[OP[0]] = MIN32;
1675 State.a[OP[0]] = tmp & MASK40;
1678 State.a[OP[0]] = tmp & MASK40;
1679 trace_output (OP_ACCUM);
1687 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1688 trace_output (OP_VOID);
1690 if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
1700 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1701 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1702 trace_output (OP_REG);
1709 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1710 State.regs[OP[0]] |= State.regs[OP[1]];
1711 trace_output (OP_REG);
1718 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1719 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1720 trace_output (OP_REG);
1728 int shift = SEXT3 (OP[2]);
1730 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1733 (*d10v_callback->printf_filtered) (d10v_callback,
1734 "ERROR at PC 0x%x: instruction only valid for A0\n",
1736 State.exception = SIGILL;
1739 State.F1 = State.F0;
1741 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1743 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1744 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1747 State.regs[OP[0]] = 0x7fff;
1748 State.regs[OP[0]+1] = 0xffff;
1751 else if (tmp < MIN32)
1753 State.regs[OP[0]] = 0x8000;
1754 State.regs[OP[0]+1] = 0;
1759 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1760 State.regs[OP[0]+1] = tmp & 0xffff;
1763 trace_output (OP_DREG);
1771 int shift = SEXT3 (OP[2]);
1773 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1774 State.F1 = State.F0;
1776 tmp = SEXT44 (State.a[1]) << shift;
1778 tmp = SEXT44 (State.a[1]) >> -shift;
1783 State.regs[OP[0]] = 0x7fff;
1786 else if (tmp < 0xfff80000000LL)
1788 State.regs[OP[0]] = 0x8000;
1793 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1796 trace_output (OP_REG);
1803 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
1806 RPT_C = State.regs[OP[0]];
1810 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
1811 State.exception = SIGILL;
1815 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
1816 State.exception = SIGILL;
1818 trace_output (OP_VOID);
1825 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
1832 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
1833 State.exception = SIGILL;
1837 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
1838 State.exception = SIGILL;
1840 trace_output (OP_VOID);
1847 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
1848 State.exception = SIGILL;
1855 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
1858 trace_output (OP_VOID);
1867 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
1868 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
1872 State.a[OP[0]] = MAX32;
1873 else if (tmp < MIN32)
1874 State.a[OP[0]] = MIN32;
1876 State.a[OP[0]] = tmp & MASK40;
1879 State.a[OP[0]] = tmp & MASK40;
1880 trace_output (OP_ACCUM);
1887 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
1888 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
1889 trace_output (OP_REG);
1896 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
1897 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
1898 trace_output (OP_REG);
1905 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
1907 trace_output (OP_VOID);
1914 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
1915 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
1916 trace_output (OP_REG);
1924 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
1925 if ((State.regs[OP[1]] & 31) <= 16)
1926 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
1929 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
1930 State.exception = SIGILL;
1937 State.a[OP[0]] = MAX32;
1938 else if (tmp < 0xffffff80000000LL)
1939 State.a[OP[0]] = MIN32;
1941 State.a[OP[0]] = tmp & MASK40;
1944 State.a[OP[0]] = tmp & MASK40;
1945 trace_output (OP_ACCUM);
1952 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
1953 State.regs[OP[0]] <<= OP[1];
1954 trace_output (OP_REG);
1966 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
1967 tmp = SEXT40(State.a[OP[0]]) << OP[1];
1972 State.a[OP[0]] = MAX32;
1973 else if (tmp < 0xffffff80000000LL)
1974 State.a[OP[0]] = MIN32;
1976 State.a[OP[0]] = tmp & MASK40;
1979 State.a[OP[0]] = tmp & MASK40;
1980 trace_output (OP_ACCUM);
1989 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
1990 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
1991 trace_output (OP_REG);
1998 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
1999 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
2000 trace_output (OP_REG);
2007 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2008 if ((State.regs[OP[1]] & 31) <= 16)
2009 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2012 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2013 State.exception = SIGILL;
2017 trace_output (OP_ACCUM);
2024 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2025 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
2026 trace_output (OP_REG);
2036 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2037 State.a[OP[0]] >>= OP[1];
2038 trace_output (OP_ACCUM);
2045 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2046 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
2047 trace_output (OP_REG);
2054 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2055 if ((State.regs[OP[1]] & 31) <= 16)
2056 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
2059 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2060 State.exception = SIGILL;
2064 trace_output (OP_ACCUM);
2071 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2072 State.regs[OP[0]] >>= OP[1];
2073 trace_output (OP_REG);
2083 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2084 State.a[OP[0]] >>= OP[1];
2085 trace_output (OP_ACCUM);
2094 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2095 tmp = State.F0 << 15;
2096 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2097 trace_output (OP_REG);
2104 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2105 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2106 trace_output (OP_VOID);
2113 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2114 SW (State.regs[OP[1]], State.regs[OP[0]]);
2115 trace_output (OP_VOID);
2122 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2125 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2126 State.exception = SIGILL;
2129 State.regs[OP[1]] -= 2;
2130 SW (State.regs[OP[1]], State.regs[OP[0]]);
2131 trace_output (OP_VOID);
2138 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2139 SW (State.regs[OP[1]], State.regs[OP[0]]);
2140 INC_ADDR (State.regs[OP[1]],2);
2141 trace_output (OP_VOID);
2148 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2149 SW (State.regs[OP[1]], State.regs[OP[0]]);
2150 INC_ADDR (State.regs[OP[1]],-2);
2151 trace_output (OP_VOID);
2158 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2159 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2160 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2161 trace_output (OP_VOID);
2168 trace_input ("st2w", OP_REG, OP_MEMREF, OP_VOID);
2169 SW (State.regs[OP[1]], State.regs[OP[0]]);
2170 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2171 trace_output (OP_VOID);
2178 trace_input ("st2w", OP_REG, OP_PREDEC, OP_VOID);
2181 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2182 State.exception = SIGILL;
2185 State.regs[OP[1]] -= 4;
2186 SW (State.regs[OP[1]], State.regs[OP[0]]);
2187 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2188 trace_output (OP_VOID);
2195 trace_input ("st2w", OP_REG, OP_POSTDEC, OP_VOID);
2196 SW (State.regs[OP[1]], State.regs[OP[0]]);
2197 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2198 INC_ADDR (State.regs[OP[1]],4);
2199 trace_output (OP_VOID);
2206 trace_input ("st2w", OP_REG, OP_POSTINC, OP_VOID);
2207 SW (State.regs[OP[1]], State.regs[OP[0]]);
2208 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2209 INC_ADDR (State.regs[OP[1]],-4);
2210 trace_output (OP_VOID);
2217 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2218 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2219 trace_output (OP_VOID);
2226 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2227 SB (State.regs[OP[1]], State.regs[OP[0]]);
2228 trace_output (OP_VOID);
2235 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2236 State.exception = SIGQUIT;
2237 trace_output (OP_VOID);
2246 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2247 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
2248 State.C = (tmp & 0xffff0000) ? 1 : 0;
2249 State.regs[OP[0]] = tmp & 0xffff;
2250 trace_output (OP_REG);
2259 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2260 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2264 State.a[OP[0]] = MAX32;
2265 else if ( tmp < MIN32)
2266 State.a[OP[0]] = MIN32;
2268 State.a[OP[0]] = tmp & MASK40;
2271 State.a[OP[0]] = tmp & MASK40;
2273 trace_output (OP_ACCUM);
2283 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2284 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2288 State.a[OP[0]] = MAX32;
2289 else if ( tmp < MIN32)
2290 State.a[OP[0]] = MIN32;
2292 State.a[OP[0]] = tmp & MASK40;
2295 State.a[OP[0]] = tmp & MASK40;
2297 trace_output (OP_ACCUM);
2307 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2308 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2309 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2311 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2312 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2313 State.regs[OP[0]+1] = tmp & 0xffff;
2314 trace_output (OP_DREG);
2323 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2324 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2325 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2326 State.regs[OP[0]+1] = tmp & 0xffff;
2327 trace_output (OP_DREG);
2336 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2337 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2338 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2339 State.regs[OP[0]+1] = tmp & 0xffff;
2340 trace_output (OP_DREG);
2349 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2350 State.F1 = State.F0;
2351 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2354 State.regs[OP[0]] = 0x7fff;
2355 State.regs[OP[0]+1] = 0xffff;
2358 else if (tmp < MIN32)
2360 State.regs[OP[0]] = 0x8000;
2361 State.regs[OP[0]+1] = 0;
2366 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2367 State.regs[OP[0]+1] = tmp & 0xffff;
2370 trace_output (OP_DREG);
2379 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2380 State.F1 = State.F0;
2381 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2384 State.regs[OP[0]] = 0x7fff;
2385 State.regs[OP[0]+1] = 0xffff;
2388 else if (tmp < MIN32)
2390 State.regs[OP[0]] = 0x8000;
2391 State.regs[OP[0]+1] = 0;
2396 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2397 State.regs[OP[0]+1] = tmp & 0xffff;
2400 trace_output (OP_DREG);
2411 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2412 tmp = (int16)State.regs[OP[0]] - OP[1];
2413 State.C = (tmp & 0xffff0000) ? 1 : 0;
2414 State.regs[OP[0]] = tmp & 0xffff;
2415 trace_output (OP_REG);
2422 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2423 trace_output (OP_VOID);
2428 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
2429 State.exception = SIGILL;
2432 /* Trap 0 is used for simulating low-level I/O */
2434 int save_errno = errno;
2437 /* Registers passed to trap 0 */
2439 #define FUNC State.regs[2] /* function number, return value */
2440 #define PARM1 State.regs[3] /* optional parm 1 */
2441 #define PARM2 State.regs[4] /* optional parm 2 */
2442 #define PARM3 State.regs[5] /* optional parm 3 */
2444 /* Registers set by trap 0 */
2446 #define RETVAL State.regs[2] /* return value */
2447 #define RETERR State.regs[3] /* return error code */
2449 /* Turn a pointer in a register into a pointer into real memory. */
2451 #define MEMPTR(x) ((char *)((x) + State.imem))
2455 #if !defined(__GO32__) && !defined(_WIN32)
2463 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2464 (char **)MEMPTR (PARM3));
2469 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2479 RETVAL = pipe (host_fd);
2480 SW (buf, host_fd[0]);
2481 buf += sizeof(uint16);
2482 SW (buf, host_fd[1]);
2491 RETVAL = wait (&status);
2500 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2507 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2508 MEMPTR (PARM2), PARM3);
2510 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2511 MEMPTR (PARM2), PARM3);
2516 RETVAL = d10v_callback->lseek (d10v_callback, PARM1, PARM2, PARM3);
2521 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2526 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2531 /* EXIT - caller can look in PARM1 to work out the
2533 State.exception = SIGQUIT;
2539 /* stat system call */
2541 struct stat host_stat;
2544 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2548 /* The hard-coded offsets and sizes were determined by using
2549 * the D10V compiler on a test program that used struct stat.
2551 SW (buf, host_stat.st_dev);
2552 SW (buf+2, host_stat.st_ino);
2553 SW (buf+4, host_stat.st_mode);
2554 SW (buf+6, host_stat.st_nlink);
2555 SW (buf+8, host_stat.st_uid);
2556 SW (buf+10, host_stat.st_gid);
2557 SW (buf+12, host_stat.st_rdev);
2558 SLW (buf+16, host_stat.st_size);
2559 SLW (buf+20, host_stat.st_atime);
2560 SLW (buf+28, host_stat.st_mtime);
2561 SLW (buf+36, host_stat.st_ctime);
2568 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2573 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2578 /* Cast the second argument to void *, to avoid type mismatch
2579 if a prototype is present. */
2580 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2592 /* Trap 1 prints a string */
2594 char *fstr = State.regs[2] + State.imem;
2595 fputs (fstr, stdout);
2600 /* Trap 2 calls printf */
2602 char *fstr = State.regs[2] + State.imem;
2603 (*d10v_callback->printf_filtered) (d10v_callback, fstr,
2604 (int16)State.regs[3],
2605 (int16)State.regs[4],
2606 (int16)State.regs[5]);
2611 /* Trap 3 writes a character */
2612 putchar (State.regs[2]);
2621 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
2622 State.F1 = State.F0;
2623 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
2624 trace_output (OP_FLAG);
2631 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
2632 State.F1 = State.F0;
2633 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
2634 trace_output (OP_FLAG);
2641 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
2643 trace_output (OP_VOID);
2650 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
2651 State.regs[OP[0]] ^= State.regs[OP[1]];
2652 trace_output (OP_REG);
2659 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2660 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
2661 trace_output (OP_REG);