9 #include "sys/syscall.h"
18 printf(" abs\tr%d\n",OP[0]);
21 if ((int16)(State.regs[OP[0]]) < 0)
23 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
37 printf(" abs\ta%d\n",OP[0]);
40 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
42 if (State.a[OP[0]] < 0 )
44 tmp = -State.a[OP[0]];
48 State.a[OP[0]] = MAX32;
50 State.a[OP[0]] = MIN32;
52 State.a[OP[0]] = tmp & MASK40;
55 State.a[OP[0]] = tmp & MASK40;
66 uint16 tmp = State.regs[OP[0]];
68 printf(" add\tr%d,r%d\n",OP[0],OP[1]);
70 State.regs[OP[0]] += State.regs[OP[1]];
71 if ( tmp > State.regs[OP[0]])
83 printf(" add\ta%d,r%d\n",OP[0],OP[1]);
85 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
89 State.a[OP[0]] = MAX32;
90 else if ( tmp < MIN32)
91 State.a[OP[0]] = MIN32;
93 State.a[OP[0]] = tmp & MASK40;
96 State.a[OP[0]] = tmp & MASK40;
105 printf(" add\ta%d,a%d\n",OP[0],OP[1]);
107 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
111 State.a[OP[0]] = MAX32;
112 else if ( tmp < MIN32)
113 State.a[OP[0]] = MIN32;
115 State.a[OP[0]] = tmp & MASK40;
118 State.a[OP[0]] = tmp & MASK40;
126 uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
127 uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
129 printf(" add2w\tr%d,r%d\n",OP[0],OP[1]);
132 if ( (tmp < tmp1) || (tmp < tmp2) )
136 State.regs[OP[0]] = tmp >> 16;
137 State.regs[OP[0]+1] = tmp & 0xFFFF;
144 uint16 tmp = State.regs[OP[0]];
146 printf(" add3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
148 State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
149 if ( tmp > State.regs[OP[0]])
161 printf(" addac3\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
163 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
164 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
165 State.regs[OP[0]+1] = tmp & 0xffff;
174 printf(" addac3\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
176 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
177 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
178 State.regs[OP[0]+1] = tmp & 0xffff;
187 printf(" addac3s\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
190 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
193 State.regs[OP[0]] = 0x7fff;
194 State.regs[OP[0]+1] = 0xffff;
197 else if (tmp < MIN32)
199 State.regs[OP[0]] = 0x8000;
200 State.regs[OP[0]+1] = 0;
205 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
206 State.regs[OP[0]+1] = tmp & 0xffff;
217 printf(" addac3s\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
220 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
223 State.regs[OP[0]] = 0x7fff;
224 State.regs[OP[0]+1] = 0xffff;
227 else if (tmp < MIN32)
229 State.regs[OP[0]] = 0x8000;
230 State.regs[OP[0]+1] = 0;
235 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
236 State.regs[OP[0]+1] = tmp & 0xffff;
248 printf(" addi\tr%d,0x%x\n",OP[0],OP[1]);
250 State.regs[OP[0]] += OP[1];
258 printf(" and\tr%d,r%d\n",OP[0],OP[1]);
260 State.regs[OP[0]] &= State.regs[OP[1]];
268 printf(" and3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
270 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
278 printf(" bclri\tr%d,%d\n",OP[0],OP[1]);
280 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
288 printf(" bl.s\t0x%x\n",OP[0]);
290 State.regs[13] = PC+1;
299 printf(" bl.l\t0x%x\n",OP[0]);
301 State.regs[13] = PC+1;
310 printf(" bnoti\tr%d,%d\n",OP[0],OP[1]);
312 State.regs[OP[0]] ^= 0x8000 >> OP[1];
320 printf(" bra.s\t0x%x\n",OP[0]);
330 printf(" bra.l\t0x%x\n",OP[0]);
340 printf(" brf0f.s\t0x%x\n",OP[0]);
351 printf(" brf0f.l\t0x%x\n",OP[0]);
362 printf(" brf0t.s\t0x%x\n",OP[0]);
373 printf(" brf0t.l\t0x%x\n",OP[0]);
384 printf(" bseti\tr%d,%d\n",OP[0],OP[1]);
386 State.regs[OP[0]] |= 0x8000 >> OP[1];
394 printf(" btsti\tr%d,%d\n",OP[0],OP[1]);
397 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
405 printf(" clrac\ta%d\n",OP[0]);
415 printf(" cmp\tr%d,r%d\n",OP[0],OP[1]);
418 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
426 printf(" cmp\ta%d,a%d\n",OP[0],OP[1]);
429 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
437 printf(" cmpeq\tr%d,r%d\n",OP[0],OP[1]);
440 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
448 printf(" cmpeq\ta%d,a%d\n",OP[0],OP[1]);
451 State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
459 printf(" cmpeqi.s\tr%d,0x%x\n",OP[0],OP[1]);
462 State.F0 = (State.regs[OP[0]] == SEXT4(OP[1])) ? 1 : 0;
470 printf(" cmpeqi.l\tr%d,0x%x\n",OP[0],OP[1]);
473 State.F0 = (State.regs[OP[0]] == OP[1]) ? 1 : 0;
481 printf(" cmpi.s\tr%d,0x%x\n",OP[0],OP[1]);
484 State.F0 = ((int16)(State.regs[OP[0]]) < SEXT4(OP[1])) ? 1 : 0;
492 printf(" cmpi.l\tr%d,0x%x\n",OP[0],OP[1]);
495 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
503 printf(" cmpu\tr%d,r%d\n",OP[0],OP[1]);
506 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
514 printf(" cmpui\tr%d,0x%x\n",OP[0],OP[1]);
517 State.F0 = (State.regs[OP[0]] < OP[1]) ? 1 : 0;
526 printf(" cpfg\t%x,%x\n",OP[0],OP[1]);
548 printf("***** DBT ***** PC=%x\n",PC);
549 State.exception = SIGTRAP;
556 uint16 foo, tmp, tmpf;
558 printf(" divs\tr%d,r%d\n",OP[0],OP[1]);
560 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
561 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
562 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
563 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
564 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
574 State.exe = (State.F0) ? 0 : 1;
584 State.exe = State.F0;
594 State.exe = (State.F1) ? 0 : 1;
604 State.exe = State.F1;
614 State.exe = (State.F0 | State.F1) ? 0 : 1;
624 State.exe = (State.F0) ? 0 : (State.F1);
634 State.exe = (State.F1) ? 0 : (State.F0);
644 State.exe = (State.F0) ? (State.F1) : 0;
655 printf(" exp\tr%d,r%d\n",OP[0],OP[1]);
657 if (((int16)State.regs[OP[1]]) >= 0)
658 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
660 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
667 State.regs[OP[0]] = i-1;
672 State.regs[OP[0]] = 16;
682 printf(" exp\tr%d,a%d\n",OP[0],OP[1]);
684 if (SEXT40(State.a[OP[1]]) >= 0)
685 tmp = State.a[OP[1]];
687 tmp = ~(State.a[OP[1]]);
689 foo = 0x4000000000LL;
694 State.regs[OP[0]] = i-9;
699 State.regs[OP[0]] = 16;
707 printf(" jl\t%x\n",OP[0]);
709 State.regs[13] = PC+1;
710 PC = State.regs[OP[0]];
718 printf(" jmp\tr%d\n",OP[0]);
720 PC = State.regs[OP[0]];
728 printf(" ld\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
730 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
738 printf(" ld\tr%d,@r%d-\n",OP[0],OP[1]);
740 State.regs[OP[0]] = RW (State.regs[OP[1]]);
741 INC_ADDR(State.regs[OP[1]],-2);
749 printf(" ld\tr%d,@r%d+\n",OP[0],OP[1]);
751 State.regs[OP[0]] = RW (State.regs[OP[1]]);
752 INC_ADDR(State.regs[OP[1]],2);
760 printf(" ld\tr%d,@r%d\n",OP[0],OP[1]);
762 State.regs[OP[0]] = RW (State.regs[OP[1]]);
770 printf(" ld2w\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
772 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
773 State.regs[OP[0]+1] = RW (OP[1] + State.regs[OP[2]] + 2);
781 printf(" ld2w\tr%d,@r%d-\n",OP[0],OP[1]);
783 State.regs[OP[0]] = RW (State.regs[OP[1]]);
784 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
785 INC_ADDR(State.regs[OP[1]],-4);
793 printf(" ld2w\tr%d,@r%d+\n",OP[0],OP[1]);
795 State.regs[OP[0]] = RW (State.regs[OP[1]]);
796 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
797 INC_ADDR(State.regs[OP[1]],4);
805 printf(" ld2w\tr%d,@r%d\n",OP[0],OP[1]);
807 State.regs[OP[0]] = RW (State.regs[OP[1]]);
808 State.regs[OP[0]+1] = RW (State.regs[OP[1]]+2);
816 printf(" ldb\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
818 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
819 SEXT8 (State.regs[OP[0]]);
827 printf(" ldb\tr%d,@r%d\n",OP[0],OP[1]);
829 State.regs[OP[0]] = RB (State.regs[OP[1]]);
830 SEXT8 (State.regs[OP[0]]);
838 printf(" ldi.s\tr%d,%x\n",OP[0],SEXT4(OP[1]));
840 State.regs[OP[0]] = SEXT4(OP[1]);
848 printf(" ldi.l\tr%d,%d\t;0x%x\n",OP[0],OP[1],OP[1]);
850 State.regs[OP[0]] = OP[1];
858 printf(" ldub\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
860 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
868 printf(" ldub\tr%d,@r%d\n",OP[0],OP[1]);
870 State.regs[OP[0]] = RB (State.regs[OP[1]]);
879 printf(" mac\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
881 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
884 tmp = SEXT40( (tmp << 1) & MASK40);
886 if (State.ST && tmp > MAX32)
889 tmp += SEXT40(State.a[OP[0]]);
893 State.a[OP[0]] = MAX32;
894 else if (tmp < MIN32)
895 State.a[OP[0]] = MIN32;
897 State.a[OP[0]] = tmp & MASK40;
900 State.a[OP[0]] = tmp & MASK40;
909 printf(" macsu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
911 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
913 tmp = SEXT40( (tmp << 1) & MASK40);
915 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
924 printf(" macu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
926 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
928 tmp = SEXT40( (tmp << 1) & MASK40);
929 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
937 printf(" max\tr%d,r%d\n",OP[0],OP[1]);
940 if (State.regs[OP[1]] > State.regs[OP[0]])
942 State.regs[OP[0]] = State.regs[OP[1]];
955 printf(" max\ta%d,r%d\n",OP[0],OP[1]);
958 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
959 if (tmp > SEXT40(State.a[OP[0]]))
961 State.a[OP[0]] = tmp & MASK40;
973 printf(" max\ta%d,a%d\n",OP[0],OP[1]);
976 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
978 State.a[OP[0]] = State.a[OP[1]];
991 printf(" min\tr%d,r%d\n",OP[0],OP[1]);
994 if (State.regs[OP[1]] < State.regs[OP[0]])
996 State.regs[OP[0]] = State.regs[OP[1]];
1009 printf(" min\ta%d,r%d\n",OP[0],OP[1]);
1011 State.F1 = State.F0;
1012 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1013 if (tmp < SEXT40(State.a[OP[0]]))
1015 State.a[OP[0]] = tmp & MASK40;
1027 printf(" min\ta%d,a%d\n",OP[0],OP[1]);
1029 State.F1 = State.F0;
1030 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1032 State.a[OP[0]] = State.a[OP[1]];
1045 printf(" msb\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
1047 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1050 tmp = SEXT40 ((tmp << 1) & MASK40);
1052 if (State.ST && tmp > MAX32)
1055 tmp = SEXT40(State.a[OP[0]]) - tmp;
1059 State.a[OP[0]] = MAX32;
1060 else if (tmp < MIN32)
1061 State.a[OP[0]] = MIN32;
1063 State.a[OP[0]] = tmp & MASK40;
1066 State.a[OP[0]] = tmp & MASK40;
1075 printf(" msbsu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
1077 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1079 tmp = SEXT40( (tmp << 1) & MASK40);
1081 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1090 printf(" msbu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
1092 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1094 tmp = SEXT40( (tmp << 1) & MASK40);
1096 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1104 printf(" mul\tr%d,r%d\n",OP[0],OP[1]);
1106 State.regs[OP[0]] *= State.regs[OP[1]];
1115 printf(" mulx\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
1117 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1120 tmp = SEXT40 ((tmp << 1) & MASK40);
1122 if (State.ST && tmp > MAX32)
1123 State.a[OP[0]] = MAX32;
1125 State.a[OP[0]] = tmp & MASK40;
1134 printf(" mulxsu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
1136 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1141 State.a[OP[0]] = tmp & MASK40;
1150 printf(" mulxu\ta%d,r%d,r%d\n",OP[0],OP[1],OP[2]);
1152 tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
1157 State.a[OP[0]] = tmp & MASK40;
1165 printf(" mv\tr%d,r%d\n",OP[0],OP[1]);
1167 State.regs[OP[0]] = State.regs[OP[1]];
1175 printf(" mv2w\tr%d,r%d\n",OP[0],OP[1]);
1177 State.regs[OP[0]] = State.regs[OP[1]];
1178 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1186 printf(" mv2wfac\tr%d,a%d\n",OP[0],OP[1]);
1188 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1189 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1197 printf(" mv2wtac\tr%d,a%d\n",OP[0],OP[1]);
1199 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1207 printf(" mvac\ta%d,a%d\n",OP[0],OP[1]);
1209 State.a[OP[0]] = State.a[OP[1]];
1217 printf(" mvb\tr%d,r%d\n",OP[0],OP[1]);
1219 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1227 printf(" mvf0f\tr%d,r%d\n",OP[0],OP[1]);
1230 State.regs[OP[0]] = State.regs[OP[1]];
1238 printf(" mvf0t\tr%d,r%d\n",OP[0],OP[1]);
1241 State.regs[OP[0]] = State.regs[OP[1]];
1249 printf(" mvfacg\tr%d,a%d\n",OP[0],OP[1]);
1251 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1259 printf(" mvfachi\tr%d,a%d\n",OP[0],OP[1]);
1261 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1269 printf(" mvfaclo\tr%d,a%d\n",OP[0],OP[1]);
1271 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1279 printf(" mvfc\tr%d,cr%d\n",OP[0],OP[1]);
1283 /* PSW is treated specially */
1285 if (State.SM) PSW |= 0x8000;
1286 if (State.EA) PSW |= 0x2000;
1287 if (State.DB) PSW |= 0x1000;
1288 if (State.IE) PSW |= 0x400;
1289 if (State.RP) PSW |= 0x200;
1290 if (State.MD) PSW |= 0x100;
1291 if (State.FX) PSW |= 0x80;
1292 if (State.ST) PSW |= 0x40;
1293 if (State.F0) PSW |= 8;
1294 if (State.F1) PSW |= 4;
1295 if (State.C) PSW |= 1;
1297 State.regs[OP[0]] = State.cregs[OP[1]];
1305 printf(" mvtacg\tr%d,a%d\n",OP[0],OP[1]);
1307 State.a[OP[1]] &= MASK32;
1308 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1317 printf(" mvtachi\tr%d,a%d\n",OP[0],OP[1]);
1319 tmp = State.a[OP[1]] & 0xffff;
1320 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1328 printf(" mvtaclo\tr%d,a%d\n",OP[0],OP[1]);
1330 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1338 printf(" mvtc\tr%d,cr%d\n",OP[0],OP[1]);
1340 State.cregs[OP[1]] = State.regs[OP[0]];
1343 /* PSW is treated specially */
1344 State.SM = (PSW & 0x8000) ? 1 : 0;
1345 State.EA = (PSW & 0x2000) ? 1 : 0;
1346 State.DB = (PSW & 0x1000) ? 1 : 0;
1347 State.IE = (PSW & 0x400) ? 1 : 0;
1348 State.RP = (PSW & 0x200) ? 1 : 0;
1349 State.MD = (PSW & 0x100) ? 1 : 0;
1350 State.FX = (PSW & 0x80) ? 1 : 0;
1351 State.ST = (PSW & 0x40) ? 1 : 0;
1352 State.F0 = (PSW & 8) ? 1 : 0;
1353 State.F1 = (PSW & 4) ? 1 : 0;
1355 if (State.ST && !State.FX)
1357 fprintf (stderr,"ERROR at PC 0x%x: ST can only be set when FX is set.\n",PC<<2);
1358 State.exception = SIGILL;
1368 printf(" mvub\tr%d,r%d\n",OP[0],OP[1]);
1370 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1378 printf(" neg\tr%d\n",OP[0]);
1380 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1389 printf(" neg\ta%d\n",OP[0]);
1391 tmp = -SEXT40(State.a[OP[0]]);
1395 State.a[OP[0]] = MAX32;
1396 else if (tmp < MIN32)
1397 State.a[OP[0]] = MIN32;
1399 State.a[OP[0]] = tmp & MASK40;
1402 State.a[OP[0]] = tmp & MASK40;
1417 printf(" not\tr%d\n",OP[0]);
1419 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1427 printf(" or\tr%d,r%d\n",OP[0],OP[1]);
1429 State.regs[OP[0]] |= State.regs[OP[1]];
1437 printf(" or3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
1439 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1447 int shift = SEXT3 (OP[2]);
1449 printf(" rac\tr%d,a%d,%d\n",OP[0],OP[1],shift);
1453 fprintf (stderr,"ERROR at PC 0x%x: instruction only valid for A0\n",PC<<2);
1454 State.exception = SIGILL;
1457 State.F1 = State.F0;
1459 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
1461 tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
1462 tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
1465 State.regs[OP[0]] = 0x7fff;
1466 State.regs[OP[0]+1] = 0xffff;
1469 else if (tmp < MIN32)
1471 State.regs[OP[0]] = 0x8000;
1472 State.regs[OP[0]+1] = 0;
1477 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1478 State.regs[OP[0]+1] = tmp & 0xffff;
1488 int shift = SEXT3 (OP[2]);
1490 printf(" rachi\tr%d,a%d,%d\n",OP[0],OP[1],shift);
1492 State.F1 = State.F0;
1494 tmp = SEXT44 (State.a[1]) << shift;
1496 tmp = SEXT44 (State.a[1]) >> -shift;
1501 State.regs[OP[0]] = 0x7fff;
1504 else if (tmp < 0xfff80000000LL)
1506 State.regs[OP[0]] = 0x8000;
1511 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1521 printf(" rep\tr%d,0x%x\n",OP[0],OP[1]);
1525 RPT_C = State.regs[OP[0]];
1529 fprintf (stderr, "ERROR: rep with count=0 is illegal.\n");
1530 State.exception = SIGILL;
1534 fprintf (stderr, "ERROR: rep must include at least 4 instructions.\n");
1535 State.exception = SIGILL;
1544 printf(" repi\t%d,0x%x\n",OP[0],OP[1]);
1552 fprintf (stderr, "ERROR: repi with count=0 is illegal.\n");
1553 State.exception = SIGILL;
1557 fprintf (stderr, "ERROR: repi must include at least 4 instructions.\n");
1558 State.exception = SIGILL;
1566 printf(" rtd - NOT IMPLEMENTED\n");
1586 printf(" sadd\ta%d,a%d\n",OP[0],OP[1]);
1588 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
1592 State.a[OP[0]] = MAX32;
1593 else if (tmp < MIN32)
1594 State.a[OP[0]] = MIN32;
1596 State.a[OP[0]] = tmp & MASK40;
1599 State.a[OP[0]] = tmp & MASK40;
1607 printf(" setf0f\tr%d\n",OP[0]);
1609 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
1617 printf(" setf0t\tr%d\n",OP[0]);
1619 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
1637 printf(" sll\tr%d,r%d\n",OP[0],OP[1]);
1639 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
1648 printf(" sll\ta%d,r%d\n",OP[0],OP[1]);
1650 if (State.regs[OP[1]] & 31 <= 16)
1651 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
1656 State.a[OP[0]] = MAX32;
1657 else if (tmp < 0xffffff80000000LL)
1658 State.a[OP[0]] = MIN32;
1660 State.a[OP[0]] = tmp & MASK40;
1663 State.a[OP[0]] = tmp & MASK40;
1671 printf(" slli\tr%d,%d\n",OP[0],OP[1]);
1673 State.regs[OP[0]] <<= OP[1];
1685 printf(" slli\ta%d,%d\n",OP[0],OP[1]);
1688 tmp = SEXT40(State.a[OP[0]]) << OP[1];
1693 State.a[OP[0]] = MAX32;
1694 else if (tmp < 0xffffff80000000LL)
1695 State.a[OP[0]] = MIN32;
1697 State.a[OP[0]] = tmp & MASK40;
1700 State.a[OP[0]] = tmp & MASK40;
1709 printf(" slx\tr%d\n",OP[0]);
1711 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
1719 printf(" sra\tr%d,r%d\n",OP[0],OP[1]);
1721 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
1729 printf(" sra\ta%d,r%d\n",OP[0],OP[1]);
1731 if (State.regs[OP[1]] & 31 <= 16)
1732 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
1740 printf(" srai\tr%d,%d\n",OP[0],OP[1]);
1742 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
1752 printf(" srai\ta%d,%d\n",OP[0],OP[1]);
1754 State.a[OP[0]] >>= OP[1];
1762 printf(" srl\tr%d,r%d\n",OP[0],OP[1]);
1764 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
1772 printf(" srl\ta%d,r%d\n",OP[0],OP[1]);
1774 if (State.regs[OP[1]] & 31 <= 16)
1775 State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
1783 printf(" srli\tr%d,%d\n",OP[0],OP[1]);
1785 State.regs[OP[0]] >>= OP[1];
1795 printf(" srli\ta%d,%d\n",OP[0],OP[1]);
1797 State.a[OP[0]] >>= OP[1];
1806 printf(" srx\tr%d\n",OP[0]);
1808 tmp = State.F0 << 15;
1809 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
1817 printf(" st\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
1819 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
1827 printf(" st\tr%d,@r%d\n",OP[0],OP[1]);
1829 SW (State.regs[OP[1]], State.regs[OP[0]]);
1837 printf(" st\tr%d,@-r%d\n",OP[0],OP[1]);
1841 fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
1842 State.exception = SIGILL;
1845 State.regs[OP[1]] -= 2;
1846 SW (State.regs[OP[1]], State.regs[OP[0]]);
1854 printf(" st\tr%d,@r%d+\n",OP[0],OP[1]);
1856 SW (State.regs[OP[1]], State.regs[OP[0]]);
1857 INC_ADDR (State.regs[OP[1]],2);
1865 printf(" st\tr%d,@r%d-\n",OP[0],OP[1]);
1867 SW (State.regs[OP[1]], State.regs[OP[0]]);
1868 INC_ADDR (State.regs[OP[1]],-2);
1876 printf(" st2w\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
1878 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
1879 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
1887 printf(" st2w\tr%d,@r%d\n",OP[0],OP[1]);
1889 SW (State.regs[OP[1]], State.regs[OP[0]]);
1890 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
1898 printf(" st2w\tr%d,@-r%d\n",OP[0],OP[1]);
1902 fprintf (stderr,"ERROR: cannot pre-decrement any registers but r15 (SP).\n");
1903 State.exception = SIGILL;
1906 State.regs[OP[1]] -= 4;
1907 SW (State.regs[OP[1]], State.regs[OP[0]]);
1908 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
1916 printf(" st2w\tr%d,r%d+\n",OP[0],OP[1]);
1918 SW (State.regs[OP[1]], State.regs[OP[0]]);
1919 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
1920 INC_ADDR (State.regs[OP[1]],4);
1928 printf(" st2w\tr%d,r%d-\n",OP[0],OP[1]);
1930 SW (State.regs[OP[1]], State.regs[OP[0]]);
1931 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
1932 INC_ADDR (State.regs[OP[1]],-4);
1940 printf(" stb\tr%d,@(0x%x,r%d)\n",OP[0],OP[1],OP[2]);
1942 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
1950 printf(" stb\tr%d,@r%d\n",OP[0],OP[1]);
1952 SB (State.regs[OP[1]], State.regs[OP[0]]);
1962 State.exception = SIGQUIT;
1971 printf(" sub\tr%d,r%d\n",OP[0],OP[1]);
1973 tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
1974 State.C = (tmp & 0xffff0000) ? 1 : 0;
1975 State.regs[OP[0]] = tmp & 0xffff;
1984 printf(" sub\ta%d,r%d\n",OP[0],OP[1]);
1986 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
1990 State.a[OP[0]] = MAX32;
1991 else if ( tmp < MIN32)
1992 State.a[OP[0]] = MIN32;
1994 State.a[OP[0]] = tmp & MASK40;
1997 State.a[OP[0]] = tmp & MASK40;
2007 printf(" sub\ta%d,a%d\n",OP[0],OP[1]);
2009 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2013 State.a[OP[0]] = MAX32;
2014 else if ( tmp < MIN32)
2015 State.a[OP[0]] = MIN32;
2017 State.a[OP[0]] = tmp & MASK40;
2020 State.a[OP[0]] = tmp & MASK40;
2030 printf(" sub2w\tr%d,r%d\n",OP[0],OP[1]);
2033 a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2034 b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2036 State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;
2037 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2038 State.regs[OP[0]+1] = tmp & 0xffff;
2047 printf(" subac3\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
2049 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2050 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2051 State.regs[OP[0]+1] = tmp & 0xffff;
2060 printf(" subac3\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
2062 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2063 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2064 State.regs[OP[0]+1] = tmp & 0xffff;
2073 printf(" subac3s\tr%d,r%d,a%d\n",OP[0],OP[1],OP[2]);
2075 State.F1 = State.F0;
2076 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2079 State.regs[OP[0]] = 0x7fff;
2080 State.regs[OP[0]+1] = 0xffff;
2083 else if (tmp < MIN32)
2085 State.regs[OP[0]] = 0x8000;
2086 State.regs[OP[0]+1] = 0;
2091 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2092 State.regs[OP[0]+1] = tmp & 0xffff;
2103 printf(" subac3s\tr%d,a%d,a%d\n",OP[0],OP[1],OP[2]);
2105 State.F1 = State.F0;
2106 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2109 State.regs[OP[0]] = 0x7fff;
2110 State.regs[OP[0]+1] = 0xffff;
2113 else if (tmp < MIN32)
2115 State.regs[OP[0]] = 0x8000;
2116 State.regs[OP[0]+1] = 0;
2121 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2122 State.regs[OP[0]+1] = tmp & 0xffff;
2135 printf(" subi\tr%d,%d\n",OP[0],OP[1]);
2137 tmp = (int16)State.regs[OP[0]] - OP[1];
2138 State.C = (tmp & 0xffff0000) ? 1 : 0;
2139 State.regs[OP[0]] = tmp & 0xffff;
2147 printf(" trap\t%d\n",OP[0]);
2153 fprintf (stderr, "Unknown trap code %d\n", OP[0]);
2154 State.exception = SIGILL;
2157 /* Trap 0 is used for simulating low-level I/O */
2159 int save_errno = errno;
2162 /* Registers passed to trap 0 */
2164 #define FUNC State.regs[2] /* function number, return value */
2165 #define PARM1 State.regs[3] /* optional parm 1 */
2166 #define PARM2 State.regs[4] /* optional parm 2 */
2167 #define PARM3 State.regs[5] /* optional parm 3 */
2169 /* Registers set by trap 0 */
2171 #define RETVAL State.regs[2] /* return value */
2172 #define RETERR State.regs[3] /* return error code */
2174 /* Turn a pointer in a register into a pointer into real memory. */
2176 #define MEMPTR(x) ((char *)((x) + State.imem))
2180 #if !defined(__GO32__) && !defined(_WIN32)
2188 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2189 (char **)MEMPTR (PARM3));
2194 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2204 RETVAL = pipe (host_fd);
2205 SW (buf, host_fd[0]);
2206 buf += sizeof(uint16);
2207 SW (buf, host_fd[1]);
2216 RETVAL = wait (&status);
2225 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2232 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2233 MEMPTR (PARM2), PARM3);
2235 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2236 MEMPTR (PARM2), PARM3);
2241 RETVAL = d10v_callback->lseek (d10v_callback, PARM1, PARM2, PARM3);
2246 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2251 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2256 /* EXIT - caller can look in PARM1 to work out the
2258 State.exception = SIGQUIT;
2264 /* stat system call */
2266 struct stat host_stat;
2269 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2273 /* The hard-coded offsets and sizes were determined by using
2274 * the D10V compiler on a test program that used struct stat.
2276 SW (buf, host_stat.st_dev);
2277 SW (buf+2, host_stat.st_ino);
2278 SW (buf+4, host_stat.st_mode);
2279 SW (buf+6, host_stat.st_nlink);
2280 SW (buf+8, host_stat.st_uid);
2281 SW (buf+10, host_stat.st_gid);
2282 SW (buf+12, host_stat.st_rdev);
2283 SLW (buf+16, host_stat.st_size);
2284 SLW (buf+20, host_stat.st_atime);
2285 SLW (buf+28, host_stat.st_mtime);
2286 SLW (buf+36, host_stat.st_ctime);
2293 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2298 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2303 /* Cast the second argument to void *, to avoid type mismatch
2304 if a prototype is present. */
2305 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2317 /* Trap 1 prints a string */
2319 char *fstr = State.regs[2] + State.imem;
2320 fputs (fstr, stdout);
2325 /* Trap 2 calls printf */
2327 char *fstr = State.regs[2] + State.imem;
2328 printf (fstr, (short)State.regs[3], (short)State.regs[4], (short)State.regs[5]);
2333 /* Trap 3 writes a character */
2334 putchar (State.regs[2]);
2344 printf(" tst0i\tr%d,0x%x\n",OP[0],OP[1]);
2346 State.F1 = State.F0;
2347 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
2355 printf(" tst1i\tr%d,0x%x\n",OP[0],OP[1]);
2357 State.F1 = State.F0;
2358 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
2376 printf(" xor\tr%d,r%d\n",OP[0],OP[1]);
2378 State.regs[OP[0]] ^= State.regs[OP[1]];
2386 printf(" xor3\tr%d,r%d,0x%x\n",OP[0],OP[1],OP[2]);
2388 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];