13 #include "sys/syscall.h"
15 extern char *strrchr ();
47 static void trace_input_func PARAMS ((char *name,
52 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
54 static void trace_output_func PARAMS ((enum op_types result));
56 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
58 #ifndef SIZE_INSTRUCTION
59 #define SIZE_INSTRUCTION 8
63 #define SIZE_OPERANDS 18
67 #define SIZE_VALUES 13
71 #define SIZE_LOCATION 20
78 #ifndef SIZE_LINE_NUMBER
79 #define SIZE_LINE_NUMBER 4
83 trace_input_func (name, in1, in2, in3)
97 const char *functionname;
98 unsigned int linenumber;
101 if ((d10v_debug & DEBUG_TRACE) == 0)
104 switch (State.ins_type)
107 case INS_UNKNOWN: type = " ?"; break;
108 case INS_LEFT: type = " L"; break;
109 case INS_RIGHT: type = " R"; break;
110 case INS_LEFT_PARALLEL: type = "*L"; break;
111 case INS_RIGHT_PARALLEL: type = "*R"; break;
112 case INS_LEFT_COND_TEST: type = "?L"; break;
113 case INS_RIGHT_COND_TEST: type = "?R"; break;
114 case INS_LEFT_COND_EXE: type = "&L"; break;
115 case INS_RIGHT_COND_EXE: type = "&R"; break;
116 case INS_LONG: type = " B"; break;
119 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
120 (*d10v_callback->printf_filtered) (d10v_callback,
122 SIZE_PC, (unsigned)PC,
124 SIZE_INSTRUCTION, name);
129 byte_pc = decode_pc ();
130 if (text && byte_pc >= text_start && byte_pc < text_end)
132 filename = (const char *)0;
133 functionname = (const char *)0;
135 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
136 &filename, &functionname, &linenumber))
141 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
146 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
147 p += SIZE_LINE_NUMBER+2;
152 sprintf (p, "%s ", functionname);
157 char *q = strrchr (filename, '/');
158 sprintf (p, "%s ", (q) ? q+1 : filename);
167 (*d10v_callback->printf_filtered) (d10v_callback,
168 "0x%.*x %s: %-*.*s %-*s ",
169 SIZE_PC, (unsigned)PC,
171 SIZE_LOCATION, SIZE_LOCATION, buf,
172 SIZE_INSTRUCTION, name);
180 for (i = 0; i < 3; i++)
195 sprintf (p, "%sr%d", comma, OP[i]);
203 sprintf (p, "%scr%d", comma, OP[i]);
209 case OP_ACCUM_OUTPUT:
210 case OP_ACCUM_REVERSE:
211 sprintf (p, "%sa%d", comma, OP[i]);
217 sprintf (p, "%s%d", comma, OP[i]);
223 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
229 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
235 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
241 sprintf (p, "%s@r%d", comma, OP[i]);
247 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
253 sprintf (p, "%s@r%d+", comma, OP[i]);
259 sprintf (p, "%s@r%d-", comma, OP[i]);
265 sprintf (p, "%s@-r%d", comma, OP[i]);
273 sprintf (p, "%sf0", comma);
276 sprintf (p, "%sf1", comma);
279 sprintf (p, "%sc", comma);
287 if ((d10v_debug & DEBUG_VALUES) == 0)
291 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
296 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
299 for (i = 0; i < 3; i++)
305 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
311 case OP_ACCUM_OUTPUT:
313 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
321 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
322 (uint16)State.regs[OP[i]]);
326 tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1]));
327 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
332 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
333 (uint16)State.cregs[OP[i]]);
337 case OP_ACCUM_REVERSE:
338 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
339 ((int)(State.a[OP[i]] >> 32) & 0xff),
340 ((unsigned long)State.a[OP[i]]) & 0xffffffff);
344 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
349 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
350 (uint16)SEXT4(OP[i]));
354 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
355 (uint16)SEXT8(OP[i]));
359 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
360 (uint16)SEXT3(OP[i]));
365 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
369 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
373 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
379 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
381 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
382 (uint16)State.regs[OP[++i]]);
386 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
387 (uint16)State.regs[2]);
391 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
392 (uint16)State.regs[3]);
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
397 (uint16)State.regs[4]);
401 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
402 (uint16)State.regs[2]);
403 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
404 (uint16)State.regs[3]);
411 (*d10v_callback->flush_stdout) (d10v_callback);
415 trace_output_func (result)
416 enum op_types result;
418 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
430 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
431 (uint16)State.regs[OP[0]],
432 State.F0 != 0, State.F1 != 0, State.C != 0);
437 tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1]));
438 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp,
439 State.F0 != 0, State.F1 != 0, State.C != 0);
444 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
445 (uint16)State.cregs[OP[0]],
446 State.F0 != 0, State.F1 != 0, State.C != 0);
450 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
451 (uint16)State.cregs[OP[1]],
452 State.F0 != 0, State.F1 != 0, State.C != 0);
456 case OP_ACCUM_OUTPUT:
457 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
458 ((int)(State.a[OP[0]] >> 32) & 0xff),
459 ((unsigned long)State.a[OP[0]]) & 0xffffffff,
460 State.F0 != 0, State.F1 != 0, State.C != 0);
463 case OP_ACCUM_REVERSE:
464 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "",
465 ((int)(State.a[OP[1]] >> 32) & 0xff),
466 ((unsigned long)State.a[OP[1]]) & 0xffffffff,
467 State.F0 != 0, State.F1 != 0, State.C != 0);
472 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "",
473 State.F0 != 0, State.F1 != 0, State.C != 0);
477 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
478 (uint16)State.regs[2],
479 State.F0 != 0, State.F1 != 0, State.C != 0);
483 (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
484 (uint16)State.regs[2], (uint16)State.regs[3],
485 State.F0 != 0, State.F1 != 0, State.C != 0);
490 (*d10v_callback->flush_stdout) (d10v_callback);
494 #define trace_input(NAME, IN1, IN2, IN3)
495 #define trace_output(RESULT)
502 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
504 if ((int16)(State.regs[OP[0]]) < 0)
506 State.regs[OP[0]] = -(int16)(State.regs[OP[0]]);
511 trace_output (OP_REG);
520 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
522 State.a[OP[0]] = SEXT40(State.a[OP[0]]);
524 if (State.a[OP[0]] < 0 )
526 tmp = -State.a[OP[0]];
530 State.a[OP[0]] = MAX32;
531 else if (tmp < MIN32)
532 State.a[OP[0]] = MIN32;
534 State.a[OP[0]] = tmp & MASK40;
537 State.a[OP[0]] = tmp & MASK40;
542 trace_output (OP_ACCUM);
549 uint16 tmp = State.regs[OP[0]];
550 trace_input ("add", OP_REG, OP_REG, OP_VOID);
551 State.regs[OP[0]] += State.regs[OP[1]];
552 if ( tmp > State.regs[OP[0]])
556 trace_output (OP_REG);
564 tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
566 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
570 State.a[OP[0]] = MAX32;
571 else if ( tmp < MIN32)
572 State.a[OP[0]] = MIN32;
574 State.a[OP[0]] = tmp & MASK40;
577 State.a[OP[0]] = tmp & MASK40;
578 trace_output (OP_ACCUM);
586 tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]);
588 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
592 State.a[OP[0]] = MAX32;
593 else if ( tmp < MIN32)
594 State.a[OP[0]] = MIN32;
596 State.a[OP[0]] = tmp & MASK40;
599 State.a[OP[0]] = tmp & MASK40;
600 trace_output (OP_ACCUM);
608 uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
609 uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
611 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
614 State.regs[OP[0]] = tmp >> 16;
615 State.regs[OP[0]+1] = tmp & 0xFFFF;
616 trace_output (OP_DREG);
623 uint16 tmp = State.regs[OP[1]];
624 State.regs[OP[0]] = tmp + OP[2];
626 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
627 State.C = (State.regs[OP[0]] < tmp);
628 trace_output (OP_REG);
636 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
638 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
639 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
640 State.regs[OP[0]+1] = tmp & 0xffff;
641 trace_output (OP_DREG);
649 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
651 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
652 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
653 State.regs[OP[0]+1] = tmp & 0xffff;
654 trace_output (OP_DREG);
664 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
665 tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
668 State.regs[OP[0]] = 0x7fff;
669 State.regs[OP[0]+1] = 0xffff;
672 else if (tmp < MIN32)
674 State.regs[OP[0]] = 0x8000;
675 State.regs[OP[0]+1] = 0;
680 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
681 State.regs[OP[0]+1] = tmp & 0xffff;
684 trace_output (OP_DREG);
694 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
695 tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]);
698 State.regs[OP[0]] = 0x7fff;
699 State.regs[OP[0]+1] = 0xffff;
702 else if (tmp < MIN32)
704 State.regs[OP[0]] = 0x8000;
705 State.regs[OP[0]+1] = 0;
710 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
711 State.regs[OP[0]+1] = tmp & 0xffff;
714 trace_output (OP_DREG);
721 uint tmp = State.regs[OP[0]];
725 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
726 State.regs[OP[0]] += OP[1];
727 State.C = (State.regs[OP[0]] < tmp);
728 trace_output (OP_REG);
735 trace_input ("and", OP_REG, OP_REG, OP_VOID);
736 State.regs[OP[0]] &= State.regs[OP[1]];
737 trace_output (OP_REG);
744 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
745 State.regs[OP[0]] = State.regs[OP[1]] & OP[2];
746 trace_output (OP_REG);
753 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
754 State.regs[OP[0]] &= ~(0x8000 >> OP[1]);
755 trace_output (OP_REG);
762 trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
763 State.regs[13] = PC+1;
764 JMP( PC + SEXT8 (OP[0]));
765 trace_output (OP_VOID);
772 trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
773 State.regs[13] = PC+1;
775 trace_output (OP_VOID);
782 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
783 State.regs[OP[0]] ^= 0x8000 >> OP[1];
784 trace_output (OP_REG);
791 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
792 JMP (PC + SEXT8 (OP[0]));
793 trace_output (OP_VOID);
800 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
802 trace_output (OP_VOID);
809 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
811 JMP (PC + SEXT8 (OP[0]));
812 trace_output (OP_FLAG);
819 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
822 trace_output (OP_FLAG);
829 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
831 JMP (PC + SEXT8 (OP[0]));
832 trace_output (OP_FLAG);
839 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
842 trace_output (OP_FLAG);
849 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
850 State.regs[OP[0]] |= 0x8000 >> OP[1];
851 trace_output (OP_REG);
858 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
860 State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0;
861 trace_output (OP_FLAG);
868 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
870 trace_output (OP_ACCUM);
877 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
879 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0;
880 trace_output (OP_FLAG);
887 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
889 State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0;
890 trace_output (OP_FLAG);
897 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
899 State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0;
900 trace_output (OP_FLAG);
907 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
909 State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
910 trace_output (OP_FLAG);
917 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
919 State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0;
920 trace_output (OP_FLAG);
927 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
929 State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0;
930 trace_output (OP_FLAG);
937 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
939 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0;
940 trace_output (OP_FLAG);
947 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
949 State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0;
950 trace_output (OP_FLAG);
957 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
959 State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0;
960 trace_output (OP_FLAG);
967 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
969 State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0;
970 trace_output (OP_FLAG);
979 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
993 trace_output (OP_FLAG);
1000 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1001 State.exception = SIGTRAP;
1008 uint16 foo, tmp, tmpf;
1010 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1011 foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15);
1012 tmp = (int16)foo - (int16)(State.regs[OP[1]]);
1013 tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0;
1014 State.regs[OP[0]] = (tmpf == 1) ? tmp : foo;
1015 State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf;
1016 trace_output (OP_DREG);
1023 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1024 State.exe = (State.F0 == 0);
1025 trace_output (OP_FLAG);
1032 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1033 State.exe = (State.F0 != 0);
1034 trace_output (OP_FLAG);
1041 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1042 State.exe = (State.F1 == 0);
1043 trace_output (OP_FLAG);
1050 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1051 State.exe = (State.F1 != 0);
1052 trace_output (OP_FLAG);
1059 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1060 State.exe = (State.F0 == 0) & (State.F1 == 0);
1061 trace_output (OP_FLAG);
1068 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1069 State.exe = (State.F0 == 0) & (State.F1 != 0);
1070 trace_output (OP_FLAG);
1077 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1078 State.exe = (State.F0 != 0) & (State.F1 == 0);
1079 trace_output (OP_FLAG);
1086 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1087 State.exe = (State.F0 != 0) & (State.F1 != 0);
1088 trace_output (OP_FLAG);
1098 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1099 if (((int16)State.regs[OP[1]]) >= 0)
1100 tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1];
1102 tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
1109 State.regs[OP[0]] = i-1;
1110 trace_output (OP_REG);
1115 State.regs[OP[0]] = 16;
1116 trace_output (OP_REG);
1126 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1127 tmp = SEXT40(State.a[OP[1]]);
1129 tmp = ~tmp & MASK40;
1131 foo = 0x4000000000LL;
1136 State.regs[OP[0]] = i-9;
1137 trace_output (OP_REG);
1142 State.regs[OP[0]] = 16;
1143 trace_output (OP_REG);
1150 trace_input ("jl", OP_REG, OP_R2, OP_R3);
1151 State.regs[13] = PC+1;
1152 JMP (State.regs[OP[0]]);
1153 trace_output (OP_VOID);
1160 trace_input ("jmp", OP_REG,
1161 (OP[0] == 13) ? OP_R2 : OP_VOID,
1162 (OP[0] == 13) ? OP_R3 : OP_VOID);
1164 JMP (State.regs[OP[0]]);
1165 trace_output (OP_VOID);
1172 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1173 State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]);
1174 trace_output (OP_REG);
1181 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1182 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1183 INC_ADDR(State.regs[OP[1]],-2);
1184 trace_output (OP_REG);
1191 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1192 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1193 INC_ADDR(State.regs[OP[1]],2);
1194 trace_output (OP_REG);
1201 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1202 State.regs[OP[0]] = RW (State.regs[OP[1]]);
1203 trace_output (OP_REG);
1210 uint16 addr = State.regs[OP[2]];
1211 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1212 State.regs[OP[0]] = RW (OP[1] + addr);
1213 State.regs[OP[0]+1] = RW (OP[1] + addr + 2);
1214 trace_output (OP_DREG);
1221 uint16 addr = State.regs[OP[1]];
1222 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1223 State.regs[OP[0]] = RW (addr);
1224 State.regs[OP[0]+1] = RW (addr+2);
1225 INC_ADDR(State.regs[OP[1]],-4);
1226 trace_output (OP_DREG);
1233 uint16 addr = State.regs[OP[1]];
1234 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1235 State.regs[OP[0]] = RW (addr);
1236 State.regs[OP[0]+1] = RW (addr+2);
1237 INC_ADDR(State.regs[OP[1]],4);
1238 trace_output (OP_DREG);
1245 uint16 addr = State.regs[OP[1]];
1246 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1247 State.regs[OP[0]] = RW (addr);
1248 State.regs[OP[0]+1] = RW (addr+2);
1249 trace_output (OP_DREG);
1256 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1257 State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
1258 trace_output (OP_REG);
1265 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1266 State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
1267 trace_output (OP_REG);
1274 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1275 State.regs[OP[0]] = SEXT4(OP[1]);
1276 trace_output (OP_REG);
1283 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1284 State.regs[OP[0]] = OP[1];
1285 trace_output (OP_REG);
1292 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1293 State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
1294 trace_output (OP_REG);
1301 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1302 State.regs[OP[0]] = RB (State.regs[OP[1]]);
1303 trace_output (OP_REG);
1312 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1313 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1316 tmp = SEXT40( (tmp << 1) & MASK40);
1318 if (State.ST && tmp > MAX32)
1321 tmp += SEXT40(State.a[OP[0]]);
1325 State.a[OP[0]] = MAX32;
1326 else if (tmp < MIN32)
1327 State.a[OP[0]] = MIN32;
1329 State.a[OP[0]] = tmp & MASK40;
1332 State.a[OP[0]] = tmp & MASK40;
1333 trace_output (OP_ACCUM);
1342 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1343 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1345 tmp = SEXT40( (tmp << 1) & MASK40);
1347 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
1348 trace_output (OP_ACCUM);
1359 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1360 src1 = (uint16) State.regs[OP[1]];
1361 src2 = (uint16) State.regs[OP[2]];
1365 State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40;
1366 trace_output (OP_ACCUM);
1373 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1374 State.F1 = State.F0;
1375 if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]])
1377 State.regs[OP[0]] = State.regs[OP[1]];
1382 trace_output (OP_REG);
1391 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1392 State.F1 = State.F0;
1393 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1394 if (tmp > SEXT40(State.a[OP[0]]))
1396 State.a[OP[0]] = tmp & MASK40;
1401 trace_output (OP_ACCUM);
1408 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1409 State.F1 = State.F0;
1410 if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]]))
1412 State.a[OP[0]] = State.a[OP[1]];
1417 trace_output (OP_ACCUM);
1425 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1426 State.F1 = State.F0;
1427 if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]])
1429 State.regs[OP[0]] = State.regs[OP[1]];
1434 trace_output (OP_REG);
1443 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1444 State.F1 = State.F0;
1445 tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
1446 if (tmp < SEXT40(State.a[OP[0]]))
1448 State.a[OP[0]] = tmp & MASK40;
1453 trace_output (OP_ACCUM);
1460 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1461 State.F1 = State.F0;
1462 if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]]))
1464 State.a[OP[0]] = State.a[OP[1]];
1469 trace_output (OP_ACCUM);
1478 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1479 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1482 tmp = SEXT40 ((tmp << 1) & MASK40);
1484 if (State.ST && tmp > MAX32)
1487 tmp = SEXT40(State.a[OP[0]]) - tmp;
1491 State.a[OP[0]] = MAX32;
1492 else if (tmp < MIN32)
1493 State.a[OP[0]] = MIN32;
1495 State.a[OP[0]] = tmp & MASK40;
1498 State.a[OP[0]] = tmp & MASK40;
1499 trace_output (OP_ACCUM);
1508 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1509 tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]);
1511 tmp = SEXT40( (tmp << 1) & MASK40);
1513 State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
1514 trace_output (OP_ACCUM);
1525 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1526 src1 = (uint16) State.regs[OP[1]];
1527 src2 = (uint16) State.regs[OP[2]];
1532 State.a[OP[0]] = (State.a[OP[0]] - tmp) & MASK40;
1533 trace_output (OP_ACCUM);
1540 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1541 State.regs[OP[0]] *= State.regs[OP[1]];
1542 trace_output (OP_REG);
1551 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1552 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]]));
1555 tmp = SEXT40 ((tmp << 1) & MASK40);
1557 if (State.ST && tmp > MAX32)
1558 State.a[OP[0]] = MAX32;
1560 State.a[OP[0]] = tmp & MASK40;
1561 trace_output (OP_ACCUM);
1570 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1571 tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]);
1576 State.a[OP[0]] = tmp & MASK40;
1577 trace_output (OP_ACCUM);
1588 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1589 src1 = (uint16) State.regs[OP[1]];
1590 src2 = (uint16) State.regs[OP[2]];
1595 State.a[OP[0]] = tmp & MASK40;
1596 trace_output (OP_ACCUM);
1603 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1604 State.regs[OP[0]] = State.regs[OP[1]];
1605 trace_output (OP_REG);
1612 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1613 State.regs[OP[0]] = State.regs[OP[1]];
1614 State.regs[OP[0]+1] = State.regs[OP[1]+1];
1615 trace_output (OP_DREG);
1622 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1623 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1624 State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff;
1625 trace_output (OP_DREG);
1632 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1633 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
1634 trace_output (OP_ACCUM_REVERSE);
1641 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1642 State.a[OP[0]] = State.a[OP[1]];
1643 trace_output (OP_ACCUM);
1650 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1651 State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff);
1652 trace_output (OP_REG);
1659 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1661 State.regs[OP[0]] = State.regs[OP[1]];
1662 trace_output (OP_REG);
1669 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1671 State.regs[OP[0]] = State.regs[OP[1]];
1672 trace_output (OP_REG);
1679 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1680 State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff;
1681 trace_output (OP_ACCUM);
1688 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1689 State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff;
1690 trace_output (OP_REG);
1697 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1698 State.regs[OP[0]] = State.a[OP[1]] & 0xffff;
1699 trace_output (OP_REG);
1706 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1709 /* PSW is treated specially */
1711 if (State.SM) PSW |= 0x8000;
1712 if (State.EA) PSW |= 0x2000;
1713 if (State.DB) PSW |= 0x1000;
1714 if (State.DM) PSW |= 0x800;
1715 if (State.IE) PSW |= 0x400;
1716 if (State.RP) PSW |= 0x200;
1717 if (State.MD) PSW |= 0x100;
1718 if (State.FX) PSW |= 0x80;
1719 if (State.ST) PSW |= 0x40;
1720 if (State.F0) PSW |= 8;
1721 if (State.F1) PSW |= 4;
1722 if (State.C) PSW |= 1;
1724 State.regs[OP[0]] = State.cregs[OP[1]];
1725 trace_output (OP_REG);
1732 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1733 State.a[OP[1]] &= MASK32;
1734 State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32;
1735 trace_output (OP_ACCUM_REVERSE);
1744 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1745 tmp = State.a[OP[1]] & 0xffff;
1746 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40;
1747 trace_output (OP_ACCUM_REVERSE);
1754 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1755 State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40;
1756 trace_output (OP_ACCUM_REVERSE);
1763 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1764 State.cregs[OP[1]] = State.regs[OP[0]];
1767 /* PSW is treated specially */
1768 State.SM = (PSW & 0x8000) ? 1 : 0;
1769 State.EA = (PSW & 0x2000) ? 1 : 0;
1770 State.DB = (PSW & 0x1000) ? 1 : 0;
1771 State.DM = (PSW & 0x800) ? 1 : 0;
1772 State.IE = (PSW & 0x400) ? 1 : 0;
1773 State.RP = (PSW & 0x200) ? 1 : 0;
1774 State.MD = (PSW & 0x100) ? 1 : 0;
1775 State.FX = (PSW & 0x80) ? 1 : 0;
1776 State.ST = (PSW & 0x40) ? 1 : 0;
1777 State.F0 = (PSW & 8) ? 1 : 0;
1778 State.F1 = (PSW & 4) ? 1 : 0;
1780 if (State.ST && !State.FX)
1782 (*d10v_callback->printf_filtered) (d10v_callback,
1783 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1785 State.exception = SIGILL;
1788 trace_output (OP_CR_REVERSE);
1795 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1796 State.regs[OP[0]] = State.regs[OP[1]] & 0xff;
1797 trace_output (OP_REG);
1804 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1805 State.regs[OP[0]] = 0 - State.regs[OP[0]];
1806 trace_output (OP_REG);
1815 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1816 tmp = -SEXT40(State.a[OP[0]]);
1820 State.a[OP[0]] = MAX32;
1821 else if (tmp < MIN32)
1822 State.a[OP[0]] = MIN32;
1824 State.a[OP[0]] = tmp & MASK40;
1827 State.a[OP[0]] = tmp & MASK40;
1828 trace_output (OP_ACCUM);
1836 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
1838 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
1839 switch (State.ins_type)
1842 ins_type_counters[ (int)INS_UNKNOWN ]++;
1845 case INS_LEFT_PARALLEL:
1846 /* Don't count a parallel op that includes a NOP as a true parallel op */
1847 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
1848 ins_type_counters[ (int)INS_RIGHT ]++;
1849 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1853 case INS_LEFT_COND_EXE:
1854 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
1857 case INS_RIGHT_PARALLEL:
1858 /* Don't count a parallel op that includes a NOP as a true parallel op */
1859 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
1860 ins_type_counters[ (int)INS_LEFT ]++;
1861 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1865 case INS_RIGHT_COND_EXE:
1866 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
1870 trace_output (OP_VOID);
1877 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
1878 State.regs[OP[0]] = ~(State.regs[OP[0]]);
1879 trace_output (OP_REG);
1886 trace_input ("or", OP_REG, OP_REG, OP_VOID);
1887 State.regs[OP[0]] |= State.regs[OP[1]];
1888 trace_output (OP_REG);
1895 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
1896 State.regs[OP[0]] = State.regs[OP[1]] | OP[2];
1897 trace_output (OP_REG);
1905 int shift = SEXT3 (OP[2]);
1907 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1910 (*d10v_callback->printf_filtered) (d10v_callback,
1911 "ERROR at PC 0x%x: instruction only valid for A0\n",
1913 State.exception = SIGILL;
1916 State.F1 = State.F0;
1917 tmp = SEXT56 ((State.a[0] << 16) | (State.a[1] & 0xffff));
1923 tmp >>= 16; /* look at bits 0:43 */
1924 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
1926 State.regs[OP[0]] = 0x7fff;
1927 State.regs[OP[0]+1] = 0xffff;
1930 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
1932 State.regs[OP[0]] = 0x8000;
1933 State.regs[OP[0]+1] = 0;
1938 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1939 State.regs[OP[0]+1] = tmp & 0xffff;
1942 trace_output (OP_DREG);
1950 int shift = SEXT3 (OP[2]);
1952 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
1953 State.F1 = State.F0;
1955 tmp = SEXT40 (State.a[OP[1]]) << shift;
1957 tmp = SEXT40 (State.a[OP[1]]) >> -shift;
1960 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
1962 State.regs[OP[0]] = 0x7fff;
1965 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
1967 State.regs[OP[0]] = 0x8000;
1972 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
1975 trace_output (OP_REG);
1982 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
1985 RPT_C = State.regs[OP[0]];
1989 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
1990 State.exception = SIGILL;
1994 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
1995 State.exception = SIGILL;
1997 trace_output (OP_VOID);
2004 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2011 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2012 State.exception = SIGILL;
2016 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2017 State.exception = SIGILL;
2019 trace_output (OP_VOID);
2026 d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n");
2027 State.exception = SIGILL;
2034 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2037 trace_output (OP_VOID);
2046 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2047 tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16);
2051 State.a[OP[0]] = MAX32;
2052 else if (tmp < MIN32)
2053 State.a[OP[0]] = MIN32;
2055 State.a[OP[0]] = tmp & MASK40;
2058 State.a[OP[0]] = tmp & MASK40;
2059 trace_output (OP_ACCUM);
2066 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2067 State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0;
2068 trace_output (OP_REG);
2075 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2076 State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0;
2077 trace_output (OP_REG);
2084 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2086 trace_output (OP_VOID);
2093 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2094 State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf);
2095 trace_output (OP_REG);
2103 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2104 if ((State.regs[OP[1]] & 31) <= 16)
2105 tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31);
2108 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2109 State.exception = SIGILL;
2116 State.a[OP[0]] = MAX32;
2117 else if (tmp < 0xffffff80000000LL)
2118 State.a[OP[0]] = MIN32;
2120 State.a[OP[0]] = tmp & MASK40;
2123 State.a[OP[0]] = tmp & MASK40;
2124 trace_output (OP_ACCUM);
2131 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2132 State.regs[OP[0]] <<= OP[1];
2133 trace_output (OP_REG);
2145 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2146 tmp = SEXT40(State.a[OP[0]]) << OP[1];
2151 State.a[OP[0]] = MAX32;
2152 else if (tmp < 0xffffff80000000LL)
2153 State.a[OP[0]] = MIN32;
2155 State.a[OP[0]] = tmp & MASK40;
2158 State.a[OP[0]] = tmp & MASK40;
2159 trace_output (OP_ACCUM);
2166 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2167 State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
2168 trace_output (OP_REG);
2175 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2176 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf);
2177 trace_output (OP_REG);
2184 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2185 if ((State.regs[OP[1]] & 31) <= 16)
2186 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
2189 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2190 State.exception = SIGILL;
2194 trace_output (OP_ACCUM);
2201 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2202 State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1];
2203 trace_output (OP_REG);
2213 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2214 State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
2215 trace_output (OP_ACCUM);
2222 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2223 State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf);
2224 trace_output (OP_REG);
2231 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2232 if ((State.regs[OP[1]] & 31) <= 16)
2233 State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
2236 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
2237 State.exception = SIGILL;
2241 trace_output (OP_ACCUM);
2248 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2249 State.regs[OP[0]] >>= OP[1];
2250 trace_output (OP_REG);
2260 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2261 State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
2262 trace_output (OP_ACCUM);
2271 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2272 tmp = State.F0 << 15;
2273 State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp;
2274 trace_output (OP_REG);
2281 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2282 SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]);
2283 trace_output (OP_VOID);
2290 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2291 SW (State.regs[OP[1]], State.regs[OP[0]]);
2292 trace_output (OP_VOID);
2299 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2302 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2303 State.exception = SIGILL;
2306 State.regs[OP[1]] -= 2;
2307 SW (State.regs[OP[1]], State.regs[OP[0]]);
2308 trace_output (OP_VOID);
2315 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2316 SW (State.regs[OP[1]], State.regs[OP[0]]);
2317 INC_ADDR (State.regs[OP[1]],2);
2318 trace_output (OP_VOID);
2325 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2328 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2329 State.exception = SIGILL;
2332 SW (State.regs[OP[1]], State.regs[OP[0]]);
2333 INC_ADDR (State.regs[OP[1]],-2);
2334 trace_output (OP_VOID);
2341 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2342 SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2343 SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]);
2344 trace_output (OP_VOID);
2351 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2352 SW (State.regs[OP[1]], State.regs[OP[0]]);
2353 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2354 trace_output (OP_VOID);
2361 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2364 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2365 State.exception = SIGILL;
2368 State.regs[OP[1]] -= 4;
2369 SW (State.regs[OP[1]], State.regs[OP[0]]);
2370 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2371 trace_output (OP_VOID);
2378 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2379 SW (State.regs[OP[1]], State.regs[OP[0]]);
2380 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2381 INC_ADDR (State.regs[OP[1]],4);
2382 trace_output (OP_VOID);
2389 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2392 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2393 State.exception = SIGILL;
2396 SW (State.regs[OP[1]], State.regs[OP[0]]);
2397 SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
2398 INC_ADDR (State.regs[OP[1]],-4);
2399 trace_output (OP_VOID);
2406 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2407 SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]);
2408 trace_output (OP_VOID);
2415 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2416 SB (State.regs[OP[1]], State.regs[OP[0]]);
2417 trace_output (OP_VOID);
2424 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2425 State.exception = SIG_D10V_STOP;
2426 trace_output (OP_VOID);
2435 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2436 /* see ../common/sim-alu.h for a more extensive discussion on how to
2437 compute the carry/overflow bits. */
2438 tmp = State.regs[OP[0]] - State.regs[OP[1]];
2439 State.C = ((uint16) State.regs[OP[0]] >= (uint16) State.regs[OP[1]]);
2440 State.regs[OP[0]] = tmp;
2441 trace_output (OP_REG);
2450 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2451 tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]);
2455 State.a[OP[0]] = MAX32;
2456 else if ( tmp < MIN32)
2457 State.a[OP[0]] = MIN32;
2459 State.a[OP[0]] = tmp & MASK40;
2462 State.a[OP[0]] = tmp & MASK40;
2464 trace_output (OP_ACCUM);
2474 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2475 tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]);
2479 State.a[OP[0]] = MAX32;
2480 else if ( tmp < MIN32)
2481 State.a[OP[0]] = MIN32;
2483 State.a[OP[0]] = tmp & MASK40;
2486 State.a[OP[0]] = tmp & MASK40;
2488 trace_output (OP_ACCUM);
2497 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2498 a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
2499 b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
2500 /* see ../common/sim-alu.h for a more extensive discussion on how to
2501 compute the carry/overflow bits */
2504 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2505 State.regs[OP[0]+1] = tmp & 0xffff;
2506 trace_output (OP_DREG);
2515 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2516 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]);
2517 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2518 State.regs[OP[0]+1] = tmp & 0xffff;
2519 trace_output (OP_DREG);
2528 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2529 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2530 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2531 State.regs[OP[0]+1] = tmp & 0xffff;
2532 trace_output (OP_DREG);
2541 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2542 State.F1 = State.F0;
2543 tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]);
2546 State.regs[OP[0]] = 0x7fff;
2547 State.regs[OP[0]+1] = 0xffff;
2550 else if (tmp < MIN32)
2552 State.regs[OP[0]] = 0x8000;
2553 State.regs[OP[0]+1] = 0;
2558 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2559 State.regs[OP[0]+1] = tmp & 0xffff;
2562 trace_output (OP_DREG);
2571 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2572 State.F1 = State.F0;
2573 tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]);
2576 State.regs[OP[0]] = 0x7fff;
2577 State.regs[OP[0]+1] = 0xffff;
2580 else if (tmp < MIN32)
2582 State.regs[OP[0]] = 0x8000;
2583 State.regs[OP[0]+1] = 0;
2588 State.regs[OP[0]] = (tmp >> 16) & 0xffff;
2589 State.regs[OP[0]+1] = tmp & 0xffff;
2592 trace_output (OP_DREG);
2603 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2604 /* see ../common/sim-alu.h for a more extensive discussion on how to
2605 compute the carry/overflow bits. */
2606 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2607 tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
2608 + (unsigned)(unsigned16) ( - OP[1]));
2609 State.C = (tmp >= (1 << 16));
2610 State.regs[OP[0]] = tmp;
2611 trace_output (OP_REG);
2618 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2619 trace_output (OP_VOID);
2625 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
2626 State.exception = SIGILL;
2628 /* Use any other traps for batch debugging. */
2631 static int first_time = 1;
2636 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2637 for (i = 0; i < 16; i++)
2638 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2639 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2642 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2644 for (i = 0; i < 16; i++)
2645 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
2647 for (i = 0; i < 2; i++)
2648 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2649 ((int)(State.a[i] >> 32) & 0xff),
2650 ((unsigned long)State.a[i]) & 0xffffffff);
2652 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2653 State.F0 != 0, State.F1 != 0, State.C != 0);
2654 (*d10v_callback->flush_stdout) (d10v_callback);
2659 case 0: /* old system call trap, to be deleted */
2660 case 15: /* new system call trap */
2661 /* Trap 15 is used for simulating low-level I/O */
2665 /* Registers passed to trap 0 */
2667 #define FUNC State.regs[6] /* function number */
2668 #define PARM1 State.regs[2] /* optional parm 1 */
2669 #define PARM2 State.regs[3] /* optional parm 2 */
2670 #define PARM3 State.regs[4] /* optional parm 3 */
2671 #define PARM4 State.regs[5] /* optional parm 3 */
2673 /* Registers set by trap 0 */
2675 #define RETVAL State.regs[2] /* return value */
2676 #define RETVAL_HIGH State.regs[2] /* return value */
2677 #define RETVAL_LOW State.regs[3] /* return value */
2678 #define RETERR State.regs[4] /* return error code */
2680 /* Turn a pointer in a register into a pointer into real memory. */
2682 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2686 #if !defined(__GO32__) && !defined(_WIN32)
2689 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2690 trace_output (OP_R2);
2694 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2696 trace_output (OP_R2);
2700 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2701 if (PARM1 == getpid ())
2703 trace_output (OP_VOID);
2704 State.exception = PARM2;
2712 case 1: os_sig = SIGHUP; break;
2715 case 2: os_sig = SIGINT; break;
2718 case 3: os_sig = SIGQUIT; break;
2721 case 4: os_sig = SIGILL; break;
2724 case 5: os_sig = SIGTRAP; break;
2727 case 6: os_sig = SIGABRT; break;
2728 #elif defined(SIGIOT)
2729 case 6: os_sig = SIGIOT; break;
2732 case 7: os_sig = SIGEMT; break;
2735 case 8: os_sig = SIGFPE; break;
2738 case 9: os_sig = SIGKILL; break;
2741 case 10: os_sig = SIGBUS; break;
2744 case 11: os_sig = SIGSEGV; break;
2747 case 12: os_sig = SIGSYS; break;
2750 case 13: os_sig = SIGPIPE; break;
2753 case 14: os_sig = SIGALRM; break;
2756 case 15: os_sig = SIGTERM; break;
2759 case 16: os_sig = SIGURG; break;
2762 case 17: os_sig = SIGSTOP; break;
2765 case 18: os_sig = SIGTSTP; break;
2768 case 19: os_sig = SIGCONT; break;
2771 case 20: os_sig = SIGCHLD; break;
2772 #elif defined(SIGCLD)
2773 case 20: os_sig = SIGCLD; break;
2776 case 21: os_sig = SIGTTIN; break;
2779 case 22: os_sig = SIGTTOU; break;
2782 case 23: os_sig = SIGIO; break;
2783 #elif defined (SIGPOLL)
2784 case 23: os_sig = SIGPOLL; break;
2787 case 24: os_sig = SIGXCPU; break;
2790 case 25: os_sig = SIGXFSZ; break;
2793 case 26: os_sig = SIGVTALRM; break;
2796 case 27: os_sig = SIGPROF; break;
2799 case 28: os_sig = SIGWINCH; break;
2802 case 29: os_sig = SIGLOST; break;
2805 case 30: os_sig = SIGUSR1; break;
2808 case 31: os_sig = SIGUSR2; break;
2814 trace_output (OP_VOID);
2815 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
2816 (*d10v_callback->flush_stdout) (d10v_callback);
2817 State.exception = SIGILL;
2821 RETVAL = kill (PARM1, PARM2);
2822 trace_output (OP_R2);
2828 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2829 (char **)MEMPTR (PARM3));
2830 trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
2831 trace_output (OP_R2);
2836 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2837 trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
2838 trace_output (OP_R2);
2848 RETVAL = pipe (host_fd);
2849 SW (buf, host_fd[0]);
2850 buf += sizeof(uint16);
2851 SW (buf, host_fd[1]);
2852 trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
2853 trace_output (OP_R2);
2862 RETVAL = wait (&status);
2865 trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
2866 trace_output (OP_R2);
2872 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2874 trace_output (OP_R2);
2878 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
2879 trace_output (OP_VOID);
2880 State.exception = PARM2;
2885 RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
2887 trace_input ("<read>", OP_R2, OP_R3, OP_R4);
2888 trace_output (OP_R2);
2893 RETVAL = (int)d10v_callback->write_stdout (d10v_callback,
2894 MEMPTR (PARM2), PARM3);
2896 RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
2897 MEMPTR (PARM2), PARM3);
2898 trace_input ("<write>", OP_R2, OP_R3, OP_R4);
2899 trace_output (OP_R2);
2904 unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1,
2905 (((unsigned long)PARM2) << 16) || (unsigned long)PARM3,
2907 RETVAL_HIGH = ret >> 16;
2908 RETVAL_LOW = ret & 0xffff;
2910 trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
2911 trace_output (OP_R2R3);
2915 RETVAL = d10v_callback->close (d10v_callback, PARM1);
2916 trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
2917 trace_output (OP_R2);
2921 RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
2922 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2923 trace_output (OP_R2);
2924 trace_input ("<open>", OP_R2, OP_R3, OP_R4);
2925 trace_output (OP_R2);
2929 State.exception = SIG_D10V_EXIT;
2930 trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
2931 trace_output (OP_VOID);
2935 /* stat system call */
2937 struct stat host_stat;
2940 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2944 /* The hard-coded offsets and sizes were determined by using
2945 * the D10V compiler on a test program that used struct stat.
2947 SW (buf, host_stat.st_dev);
2948 SW (buf+2, host_stat.st_ino);
2949 SW (buf+4, host_stat.st_mode);
2950 SW (buf+6, host_stat.st_nlink);
2951 SW (buf+8, host_stat.st_uid);
2952 SW (buf+10, host_stat.st_gid);
2953 SW (buf+12, host_stat.st_rdev);
2954 SLW (buf+16, host_stat.st_size);
2955 SLW (buf+20, host_stat.st_atime);
2956 SLW (buf+28, host_stat.st_mtime);
2957 SLW (buf+36, host_stat.st_ctime);
2959 trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
2960 trace_output (OP_R2);
2964 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2965 trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
2966 trace_output (OP_R2);
2970 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2971 trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
2972 trace_output (OP_R2);
2977 /* Cast the second argument to void *, to avoid type mismatch
2978 if a prototype is present. */
2979 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2980 trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
2981 trace_output (OP_R2);
2988 unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
2989 RETVAL_HIGH = ret >> 16;
2990 RETVAL_LOW = ret & 0xffff;
2992 trace_input ("<time>", OP_R2, OP_R3, OP_R4);
2993 trace_output (OP_R2R3);
3000 RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0;
3010 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3011 State.F1 = State.F0;
3012 State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0;
3013 trace_output (OP_FLAG);
3020 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3021 State.F1 = State.F0;
3022 State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0;
3023 trace_output (OP_FLAG);
3030 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3032 trace_output (OP_VOID);
3039 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3040 State.regs[OP[0]] ^= State.regs[OP[1]];
3041 trace_output (OP_REG);
3048 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3049 State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2];
3050 trace_output (OP_REG);