13 #include "targ-vals.h"
15 extern char *strrchr ();
48 PSW_MASK = (PSW_SM_BIT
62 move_to_cr (int cr, reg_t mask, reg_t val)
64 /* A MASK bit is set when the corresponding bit in the CR should
66 /* This assumes that (VAL & MASK) == 0 */
71 if ((mask & PSW_SM_BIT) == 0)
73 int new_sm = (val & PSW_SM_BIT) != 0;
74 SET_HELD_SP (PSW_SM, GPR (SP_IDX)); /* save old SP */
76 SET_GPR (SP_IDX, HELD_SP (new_sm)); /* restore new SP */
78 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
80 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
82 (*d10v_callback->printf_filtered)
84 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
86 State.exception = SIGILL;
89 /* keep an up-to-date psw around for tracing */
90 State.trace.psw = (State.trace.psw & mask) | val;
103 /* only issue an update if the register is being changed */
104 if ((State.cregs[cr] & ~mask) != val)
105 SLOT_PEND_MASK (State.cregs[cr], mask, val);
110 static void trace_input_func PARAMS ((char *name,
115 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
117 #ifndef SIZE_INSTRUCTION
118 #define SIZE_INSTRUCTION 8
121 #ifndef SIZE_OPERANDS
122 #define SIZE_OPERANDS 18
126 #define SIZE_VALUES 13
129 #ifndef SIZE_LOCATION
130 #define SIZE_LOCATION 20
137 #ifndef SIZE_LINE_NUMBER
138 #define SIZE_LINE_NUMBER 4
142 trace_input_func (name, in1, in2, in3)
155 const char *filename;
156 const char *functionname;
157 unsigned int linenumber;
160 if ((d10v_debug & DEBUG_TRACE) == 0)
163 switch (State.ins_type)
166 case INS_UNKNOWN: type = " ?"; break;
167 case INS_LEFT: type = " L"; break;
168 case INS_RIGHT: type = " R"; break;
169 case INS_LEFT_PARALLEL: type = "*L"; break;
170 case INS_RIGHT_PARALLEL: type = "*R"; break;
171 case INS_LEFT_COND_TEST: type = "?L"; break;
172 case INS_RIGHT_COND_TEST: type = "?R"; break;
173 case INS_LEFT_COND_EXE: type = "&L"; break;
174 case INS_RIGHT_COND_EXE: type = "&R"; break;
175 case INS_LONG: type = " B"; break;
178 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
179 (*d10v_callback->printf_filtered) (d10v_callback,
181 SIZE_PC, (unsigned)PC,
183 SIZE_INSTRUCTION, name);
188 byte_pc = decode_pc ();
189 if (text && byte_pc >= text_start && byte_pc < text_end)
191 filename = (const char *)0;
192 functionname = (const char *)0;
194 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
195 &filename, &functionname, &linenumber))
200 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
205 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
206 p += SIZE_LINE_NUMBER+2;
211 sprintf (p, "%s ", functionname);
216 char *q = strrchr (filename, '/');
217 sprintf (p, "%s ", (q) ? q+1 : filename);
226 (*d10v_callback->printf_filtered) (d10v_callback,
227 "0x%.*x %s: %-*.*s %-*s ",
228 SIZE_PC, (unsigned)PC,
230 SIZE_LOCATION, SIZE_LOCATION, buf,
231 SIZE_INSTRUCTION, name);
239 for (i = 0; i < 3; i++)
253 sprintf (p, "%sr%d", comma, OP[i]);
261 sprintf (p, "%scr%d", comma, OP[i]);
267 case OP_ACCUM_OUTPUT:
268 case OP_ACCUM_REVERSE:
269 sprintf (p, "%sa%d", comma, OP[i]);
275 sprintf (p, "%s%d", comma, OP[i]);
281 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
287 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
293 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
299 sprintf (p, "%s@r%d", comma, OP[i]);
305 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
311 sprintf (p, "%s@%d", comma, OP[i]);
317 sprintf (p, "%s@r%d+", comma, OP[i]);
323 sprintf (p, "%s@r%d-", comma, OP[i]);
329 sprintf (p, "%s@-r%d", comma, OP[i]);
337 sprintf (p, "%sf0", comma);
340 sprintf (p, "%sf1", comma);
343 sprintf (p, "%sc", comma);
351 if ((d10v_debug & DEBUG_VALUES) == 0)
355 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
360 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
363 for (i = 0; i < 3; i++)
369 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
375 case OP_ACCUM_OUTPUT:
377 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
385 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
386 (uint16) GPR (OP[i]));
390 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
394 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
395 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
400 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
401 (uint16) CREG (OP[i]));
405 case OP_ACCUM_REVERSE:
406 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
407 ((int)(ACC (OP[i]) >> 32) & 0xff),
408 ((unsigned long) ACC (OP[i])) & 0xffffffff);
412 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
417 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
418 (uint16)SEXT4(OP[i]));
422 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
423 (uint16)SEXT8(OP[i]));
427 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
428 (uint16)SEXT3(OP[i]));
433 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
437 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
441 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
447 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
449 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
450 (uint16)GPR (OP[i + 1]));
455 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
460 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
465 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
473 (*d10v_callback->flush_stdout) (d10v_callback);
477 do_trace_output_flush (void)
479 (*d10v_callback->flush_stdout) (d10v_callback);
483 do_trace_output_finish (void)
485 (*d10v_callback->printf_filtered) (d10v_callback,
486 " F0=%d F1=%d C=%d\n",
487 (State.trace.psw & PSW_F0_BIT) != 0,
488 (State.trace.psw & PSW_F1_BIT) != 0,
489 (State.trace.psw & PSW_C_BIT) != 0);
490 (*d10v_callback->flush_stdout) (d10v_callback);
494 trace_output_40 (uint64 val)
496 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
498 (*d10v_callback->printf_filtered) (d10v_callback,
499 " :: %*s0x%.2x%.8lx",
502 ((int)(val >> 32) & 0xff),
503 ((unsigned long) val) & 0xffffffff);
504 do_trace_output_finish ();
509 trace_output_32 (uint32 val)
511 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
513 (*d10v_callback->printf_filtered) (d10v_callback,
518 do_trace_output_finish ();
523 trace_output_16 (uint16 val)
525 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
527 (*d10v_callback->printf_filtered) (d10v_callback,
532 do_trace_output_finish ();
539 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
541 (*d10v_callback->printf_filtered) (d10v_callback, "\n");
542 do_trace_output_flush ();
549 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
551 (*d10v_callback->printf_filtered) (d10v_callback,
555 do_trace_output_finish ();
563 #define trace_input(NAME, IN1, IN2, IN3)
564 #define trace_output(RESULT)
572 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
582 SET_GPR (OP[0], tmp);
583 trace_output_16 (tmp);
591 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
594 tmp = SEXT40 (ACC (OP[0]));
600 if (tmp > SEXT40(MAX32))
602 else if (tmp < SEXT40(MIN32))
605 tmp = (tmp & MASK40);
608 tmp = (tmp & MASK40);
613 tmp = (tmp & MASK40);
616 SET_ACC (OP[0], tmp);
617 trace_output_40 (tmp);
624 uint16 a = GPR (OP[0]);
625 uint16 b = GPR (OP[1]);
626 uint16 tmp = (a + b);
627 trace_input ("add", OP_REG, OP_REG, OP_VOID);
629 SET_GPR (OP[0], tmp);
630 trace_output_16 (tmp);
638 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
640 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
643 if (tmp > SEXT40(MAX32))
645 else if (tmp < SEXT40(MIN32))
648 tmp = (tmp & MASK40);
651 tmp = (tmp & MASK40);
652 SET_ACC (OP[0], tmp);
653 trace_output_40 (tmp);
661 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
663 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
666 if (tmp > SEXT40(MAX32))
668 else if (tmp < SEXT40(MIN32))
671 tmp = (tmp & MASK40);
674 tmp = (tmp & MASK40);
675 SET_ACC (OP[0], tmp);
676 trace_output_40 (tmp);
684 uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
685 uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
686 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
689 SET_GPR (OP[0] + 0, (tmp >> 16));
690 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
691 trace_output_32 (tmp);
698 uint16 a = GPR (OP[1]);
700 uint16 tmp = (a + b);
701 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
703 SET_GPR (OP[0], tmp);
704 trace_output_16 (tmp);
712 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
714 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
715 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
716 SET_GPR (OP[0] + 1, (tmp & 0xffff));
717 trace_output_32 (tmp);
725 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
727 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
728 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
729 SET_GPR (OP[0] + 1, tmp & 0xffff);
730 trace_output_32 (tmp);
740 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
741 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
742 if (tmp > SEXT40(MAX32))
747 else if (tmp < SEXT40(MIN32))
756 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
757 SET_GPR (OP[0] + 1, (tmp & 0xffff));
758 trace_output_32 (tmp);
768 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
769 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
770 if (tmp > SEXT40(MAX32))
775 else if (tmp < SEXT40(MIN32))
784 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
785 SET_GPR (OP[0] + 1, (tmp & 0xffff));
786 trace_output_32 (tmp);
793 uint16 a = GPR (OP[0]);
800 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
802 SET_GPR (OP[0], tmp);
803 trace_output_16 (tmp);
810 uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
811 trace_input ("and", OP_REG, OP_REG, OP_VOID);
812 SET_GPR (OP[0], tmp);
813 trace_output_16 (tmp);
820 uint16 tmp = GPR (OP[1]) & OP[2];
821 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
822 SET_GPR (OP[0], tmp);
823 trace_output_16 (tmp);
831 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
832 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
833 SET_GPR (OP[0], tmp);
834 trace_output_16 (tmp);
841 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
842 SET_GPR (13, PC + 1);
843 JMP( PC + SEXT8 (OP[0]));
844 trace_output_void ();
851 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
852 SET_GPR (13, (PC + 1));
854 trace_output_void ();
862 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
863 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
864 SET_GPR (OP[0], tmp);
865 trace_output_16 (tmp);
872 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
873 JMP (PC + SEXT8 (OP[0]));
874 trace_output_void ();
881 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
883 trace_output_void ();
890 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
892 JMP (PC + SEXT8 (OP[0]));
893 trace_output_flag ();
900 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
903 trace_output_flag ();
910 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
912 JMP (PC + SEXT8 (OP[0]));
913 trace_output_flag ();
920 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
923 trace_output_flag ();
931 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
932 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
933 SET_GPR (OP[0], tmp);
934 trace_output_16 (tmp);
941 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
943 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
944 trace_output_flag ();
951 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
960 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
962 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
963 trace_output_flag ();
970 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
972 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
973 trace_output_flag ();
980 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
982 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
983 trace_output_flag ();
990 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
992 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
993 trace_output_flag ();
1000 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1001 SET_PSW_F1 (PSW_F0);
1002 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1003 trace_output_flag ();
1010 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1011 SET_PSW_F1 (PSW_F0);
1012 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1013 trace_output_flag ();
1020 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1021 SET_PSW_F1 (PSW_F0);
1022 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1023 trace_output_flag ();
1030 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1031 SET_PSW_F1 (PSW_F0);
1032 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1033 trace_output_flag ();
1040 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1041 SET_PSW_F1 (PSW_F0);
1042 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1043 trace_output_flag ();
1050 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1051 SET_PSW_F1 (PSW_F0);
1052 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1053 trace_output_flag ();
1062 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1066 else if (OP[1] == 1)
1075 trace_output_flag ();
1082 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1084 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1085 The conditional below is for either of the instruction pairs
1086 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1087 where the dbt instruction should be interpreted.
1089 The module `sim-break' provides a more effective mechanism for
1090 detecting GDB planted breakpoints. The code below may,
1091 eventually, be changed to use that mechanism. */
1093 if (State.ins_type == INS_LEFT
1094 || State.ins_type == INS_RIGHT)
1096 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1099 SET_PSW (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT));
1100 JMP (DBT_VECTOR_START);
1101 trace_output_void ();
1105 State.exception = SIGTRAP;
1113 uint16 foo, tmp, tmpf;
1117 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1118 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1119 tmp = (int16)foo - (int16)(GPR (OP[1]));
1120 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1121 hi = ((tmpf == 1) ? tmp : foo);
1122 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1123 SET_GPR (OP[0] + 0, hi);
1124 SET_GPR (OP[0] + 1, lo);
1125 trace_output_32 (((uint32) hi << 16) | lo);
1132 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1133 State.exe = (PSW_F0 == 0);
1134 trace_output_flag ();
1141 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1142 State.exe = (PSW_F0 != 0);
1143 trace_output_flag ();
1150 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1151 State.exe = (PSW_F1 == 0);
1152 trace_output_flag ();
1159 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1160 State.exe = (PSW_F1 != 0);
1161 trace_output_flag ();
1168 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1169 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1170 trace_output_flag ();
1177 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1178 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1179 trace_output_flag ();
1186 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1187 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1188 trace_output_flag ();
1195 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1196 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1197 trace_output_flag ();
1207 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1208 if (((int16)GPR (OP[1])) >= 0)
1209 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1211 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1218 SET_GPR (OP[0], (i - 1));
1219 trace_output_16 (i - 1);
1224 SET_GPR (OP[0], 16);
1225 trace_output_16 (16);
1235 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1236 tmp = SEXT40(ACC (OP[1]));
1238 tmp = ~tmp & MASK40;
1240 foo = 0x4000000000LL;
1245 SET_GPR (OP[0], i - 9);
1246 trace_output_16 (i - 9);
1251 SET_GPR (OP[0], 16);
1252 trace_output_16 (16);
1259 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1260 SET_GPR (13, PC + 1);
1262 trace_output_void ();
1269 trace_input ("jmp", OP_REG,
1270 (OP[0] == 13) ? OP_R0 : OP_VOID,
1271 (OP[0] == 13) ? OP_R1 : OP_VOID);
1274 trace_output_void ();
1282 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1283 tmp = RW (OP[1] + GPR (OP[2]));
1284 SET_GPR (OP[0], tmp);
1285 trace_output_16 (tmp);
1293 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1294 tmp = RW (GPR (OP[1]));
1295 SET_GPR (OP[0], tmp);
1297 INC_ADDR (OP[1], -2);
1298 trace_output_16 (tmp);
1306 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1307 tmp = RW (GPR (OP[1]));
1308 SET_GPR (OP[0], tmp);
1310 INC_ADDR (OP[1], 2);
1311 trace_output_16 (tmp);
1319 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1320 tmp = RW (GPR (OP[1]));
1321 SET_GPR (OP[0], tmp);
1322 trace_output_16 (tmp);
1331 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1333 SET_GPR (OP[0], tmp);
1334 trace_output_16 (tmp);
1342 uint16 addr = GPR (OP[2]);
1343 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1344 tmp = RLW (OP[1] + addr);
1345 SET_GPR32 (OP[0], tmp);
1346 trace_output_32 (tmp);
1353 uint16 addr = GPR (OP[1]);
1355 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1357 SET_GPR32 (OP[0], tmp);
1358 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1359 INC_ADDR (OP[1], -4);
1360 trace_output_32 (tmp);
1368 uint16 addr = GPR (OP[1]);
1369 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1371 SET_GPR32 (OP[0], tmp);
1372 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1373 INC_ADDR (OP[1], 4);
1374 trace_output_32 (tmp);
1381 uint16 addr = GPR (OP[1]);
1383 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1384 tmp = RLW (addr + 0);
1385 SET_GPR32 (OP[0], tmp);
1386 trace_output_32 (tmp);
1395 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1397 SET_GPR32 (OP[0], tmp);
1398 trace_output_32 (tmp);
1406 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1407 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1408 SET_GPR (OP[0], tmp);
1409 trace_output_16 (tmp);
1417 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1418 tmp = SEXT8 (RB (GPR (OP[1])));
1419 SET_GPR (OP[0], tmp);
1420 trace_output_16 (tmp);
1428 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1429 tmp = SEXT4 (OP[1]);
1430 SET_GPR (OP[0], tmp);
1431 trace_output_16 (tmp);
1439 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1441 SET_GPR (OP[0], tmp);
1442 trace_output_16 (tmp);
1450 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1451 tmp = RB (OP[1] + GPR (OP[2]));
1452 SET_GPR (OP[0], tmp);
1453 trace_output_16 (tmp);
1461 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1462 tmp = RB (GPR (OP[1]));
1463 SET_GPR (OP[0], tmp);
1464 trace_output_16 (tmp);
1473 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1474 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1477 tmp = SEXT40( (tmp << 1) & MASK40);
1479 if (PSW_ST && tmp > SEXT40(MAX32))
1482 tmp += SEXT40 (ACC (OP[0]));
1485 if (tmp > SEXT40(MAX32))
1487 else if (tmp < SEXT40(MIN32))
1490 tmp = (tmp & MASK40);
1493 tmp = (tmp & MASK40);
1494 SET_ACC (OP[0], tmp);
1495 trace_output_40 (tmp);
1504 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1505 tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1507 tmp = SEXT40 ((tmp << 1) & MASK40);
1508 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1509 SET_ACC (OP[0], tmp);
1510 trace_output_40 (tmp);
1521 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1522 src1 = (uint16) GPR (OP[1]);
1523 src2 = (uint16) GPR (OP[2]);
1527 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1528 SET_ACC (OP[0], tmp);
1529 trace_output_40 (tmp);
1537 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1538 SET_PSW_F1 (PSW_F0);
1539 if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1549 SET_GPR (OP[0], tmp);
1550 trace_output_16 (tmp);
1559 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1560 SET_PSW_F1 (PSW_F0);
1561 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1562 if (tmp > SEXT40 (ACC (OP[0])))
1564 tmp = (tmp & MASK40);
1572 SET_ACC (OP[0], tmp);
1573 trace_output_40 (tmp);
1581 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1582 SET_PSW_F1 (PSW_F0);
1583 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1593 SET_ACC (OP[0], tmp);
1594 trace_output_40 (tmp);
1603 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1604 SET_PSW_F1 (PSW_F0);
1605 if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1615 SET_GPR (OP[0], tmp);
1616 trace_output_16 (tmp);
1625 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1626 SET_PSW_F1 (PSW_F0);
1627 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1628 if (tmp < SEXT40(ACC (OP[0])))
1630 tmp = (tmp & MASK40);
1638 SET_ACC (OP[0], tmp);
1639 trace_output_40 (tmp);
1647 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1648 SET_PSW_F1 (PSW_F0);
1649 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1659 SET_ACC (OP[0], tmp);
1660 trace_output_40 (tmp);
1669 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1670 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1673 tmp = SEXT40 ((tmp << 1) & MASK40);
1675 if (PSW_ST && tmp > SEXT40(MAX32))
1678 tmp = SEXT40(ACC (OP[0])) - tmp;
1681 if (tmp > SEXT40(MAX32))
1683 else if (tmp < SEXT40(MIN32))
1686 tmp = (tmp & MASK40);
1690 tmp = (tmp & MASK40);
1692 SET_ACC (OP[0], tmp);
1693 trace_output_40 (tmp);
1702 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1703 tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1705 tmp = SEXT40( (tmp << 1) & MASK40);
1706 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1707 SET_ACC (OP[0], tmp);
1708 trace_output_40 (tmp);
1719 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1720 src1 = (uint16) GPR (OP[1]);
1721 src2 = (uint16) GPR (OP[2]);
1725 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1726 SET_ACC (OP[0], tmp);
1727 trace_output_40 (tmp);
1735 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1736 tmp = GPR (OP[0]) * GPR (OP[1]);
1737 SET_GPR (OP[0], tmp);
1738 trace_output_16 (tmp);
1747 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1748 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1751 tmp = SEXT40 ((tmp << 1) & MASK40);
1753 if (PSW_ST && tmp > SEXT40(MAX32))
1756 tmp = (tmp & MASK40);
1757 SET_ACC (OP[0], tmp);
1758 trace_output_40 (tmp);
1767 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1768 tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1772 tmp = (tmp & MASK40);
1773 SET_ACC (OP[0], tmp);
1774 trace_output_40 (tmp);
1785 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1786 src1 = (uint16) GPR (OP[1]);
1787 src2 = (uint16) GPR (OP[2]);
1791 tmp = (tmp & MASK40);
1792 SET_ACC (OP[0], tmp);
1793 trace_output_40 (tmp);
1801 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1803 SET_GPR (OP[0], tmp);
1804 trace_output_16 (tmp);
1812 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1813 tmp = GPR32 (OP[1]);
1814 SET_GPR32 (OP[0], tmp);
1815 trace_output_32 (tmp);
1823 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1825 SET_GPR32 (OP[0], tmp);
1826 trace_output_32 (tmp);
1834 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1835 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1836 SET_ACC (OP[1], tmp);
1837 trace_output_40 (tmp);
1845 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1847 SET_ACC (OP[0], tmp);
1848 trace_output_40 (tmp);
1856 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1857 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1858 SET_GPR (OP[0], tmp);
1859 trace_output_16 (tmp);
1867 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1871 SET_GPR (OP[0], tmp);
1875 trace_output_16 (tmp);
1883 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1887 SET_GPR (OP[0], tmp);
1891 trace_output_16 (tmp);
1899 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1900 tmp = ((ACC (OP[1]) >> 32) & 0xff);
1901 SET_GPR (OP[0], tmp);
1902 trace_output_16 (tmp);
1910 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1911 tmp = (ACC (OP[1]) >> 16);
1912 SET_GPR (OP[0], tmp);
1913 trace_output_16 (tmp);
1921 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1923 SET_GPR (OP[0], tmp);
1924 trace_output_16 (tmp);
1932 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1934 SET_GPR (OP[0], tmp);
1935 trace_output_16 (tmp);
1943 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1944 tmp = ((ACC (OP[1]) & MASK32)
1945 | ((int64)(GPR (OP[0]) & 0xff) << 32));
1946 SET_ACC (OP[1], tmp);
1947 trace_output_40 (tmp);
1955 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1956 tmp = ACC (OP[1]) & 0xffff;
1957 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
1958 SET_ACC (OP[1], tmp);
1959 trace_output_40 (tmp);
1967 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1968 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
1969 SET_ACC (OP[1], tmp);
1970 trace_output_40 (tmp);
1978 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1980 tmp = SET_CREG (OP[1], tmp);
1981 trace_output_16 (tmp);
1989 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1990 tmp = (GPR (OP[1]) & 0xff);
1991 SET_GPR (OP[0], tmp);
1992 trace_output_16 (tmp);
2000 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2001 tmp = - GPR (OP[0]);
2002 SET_GPR (OP[0], tmp);
2003 trace_output_16 (tmp);
2012 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2013 tmp = -SEXT40(ACC (OP[0]));
2016 if (tmp > SEXT40(MAX32))
2018 else if (tmp < SEXT40(MIN32))
2021 tmp = (tmp & MASK40);
2024 tmp = (tmp & MASK40);
2025 SET_ACC (OP[0], tmp);
2026 trace_output_40 (tmp);
2034 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2036 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2037 switch (State.ins_type)
2040 ins_type_counters[ (int)INS_UNKNOWN ]++;
2043 case INS_LEFT_PARALLEL:
2044 /* Don't count a parallel op that includes a NOP as a true parallel op */
2045 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2046 ins_type_counters[ (int)INS_RIGHT ]++;
2047 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2051 case INS_LEFT_COND_EXE:
2052 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2055 case INS_RIGHT_PARALLEL:
2056 /* Don't count a parallel op that includes a NOP as a true parallel op */
2057 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2058 ins_type_counters[ (int)INS_LEFT ]++;
2059 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2063 case INS_RIGHT_COND_EXE:
2064 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2068 trace_output_void ();
2076 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2078 SET_GPR (OP[0], tmp);
2079 trace_output_16 (tmp);
2087 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2088 tmp = (GPR (OP[0]) | GPR (OP[1]));
2089 SET_GPR (OP[0], tmp);
2090 trace_output_16 (tmp);
2098 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2099 tmp = (GPR (OP[1]) | OP[2]);
2100 SET_GPR (OP[0], tmp);
2101 trace_output_16 (tmp);
2109 int shift = SEXT3 (OP[2]);
2111 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2114 (*d10v_callback->printf_filtered) (d10v_callback,
2115 "ERROR at PC 0x%x: instruction only valid for A0\n",
2117 State.exception = SIGILL;
2120 SET_PSW_F1 (PSW_F0);
2121 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2127 tmp >>= 16; /* look at bits 0:43 */
2128 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2133 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2142 SET_GPR32 (OP[0], tmp);
2143 trace_output_32 (tmp);
2151 int shift = SEXT3 (OP[2]);
2153 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2154 SET_PSW_F1 (PSW_F0);
2156 tmp = SEXT40 (ACC (OP[1])) << shift;
2158 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2161 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2166 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2176 SET_GPR (OP[0], tmp);
2177 trace_output_16 (tmp);
2184 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2186 SET_RPT_E (PC + OP[1]);
2187 SET_RPT_C (GPR (OP[0]));
2189 if (GPR (OP[0]) == 0)
2191 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2192 State.exception = SIGILL;
2196 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2197 State.exception = SIGILL;
2199 trace_output_void ();
2206 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2208 SET_RPT_E (PC + OP[1]);
2213 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2214 State.exception = SIGILL;
2218 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2219 State.exception = SIGILL;
2221 trace_output_void ();
2228 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2229 SET_CREG (PSW_CR, DPSW);
2231 trace_output_void ();
2238 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2239 SET_CREG (PSW_CR, BPSW);
2241 trace_output_void ();
2249 trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2251 tmp = SEXT40(ACC (OP[1]));
2253 SET_PSW_F1 (PSW_F0);
2255 if (tmp > SEXT40(MAX32))
2260 else if (tmp < SEXT40(MIN32))
2267 tmp = (tmp & MASK32);
2271 SET_GPR32 (OP[0], tmp);
2273 trace_output_40 (tmp);
2282 trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2284 tmp = SEXT40(ACC (OP[1]));
2286 SET_PSW_F1 (PSW_F0);
2288 if (tmp > SEXT40(MAX32))
2293 else if (tmp < SEXT40(MIN32))
2304 SET_GPR (OP[0], tmp);
2306 trace_output_16 (OP[0]);
2315 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2316 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2319 if (tmp > SEXT40(MAX32))
2321 else if (tmp < SEXT40(MIN32))
2324 tmp = (tmp & MASK40);
2327 tmp = (tmp & MASK40);
2328 SET_ACC (OP[0], tmp);
2329 trace_output_40 (tmp);
2337 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2338 tmp = ((PSW_F0 == 0) ? 1 : 0);
2339 SET_GPR (OP[0], tmp);
2340 trace_output_16 (tmp);
2348 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2349 tmp = ((PSW_F0 == 1) ? 1 : 0);
2350 SET_GPR (OP[0], tmp);
2351 trace_output_16 (tmp);
2361 trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2363 reg = SEXT16 (GPR (OP[1]));
2365 if (reg >= 17 || reg <= -17)
2367 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
2368 State.exception = SIGILL;
2372 tmp = SEXT40 (ACC (OP[0]));
2374 if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2376 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
2377 State.exception = SIGILL;
2381 if (reg >= 0 && reg <= 16)
2383 tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2386 if (tmp > SEXT40(MAX32))
2388 else if (tmp < SEXT40(MIN32))
2391 tmp = (tmp & MASK40);
2394 tmp = (tmp & MASK40);
2398 tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2401 SET_ACC(OP[0], tmp);
2403 trace_output_40(tmp);
2410 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2412 trace_output_void ();
2420 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2421 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2422 SET_GPR (OP[0], tmp);
2423 trace_output_16 (tmp);
2431 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2432 if ((GPR (OP[1]) & 31) <= 16)
2433 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2436 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2437 State.exception = SIGILL;
2443 if (tmp > SEXT40(MAX32))
2445 else if (tmp < SEXT40(MIN32))
2448 tmp = (tmp & MASK40);
2451 tmp = (tmp & MASK40);
2452 SET_ACC (OP[0], tmp);
2453 trace_output_40 (tmp);
2461 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2462 tmp = (GPR (OP[0]) << OP[1]);
2463 SET_GPR (OP[0], tmp);
2464 trace_output_16 (tmp);
2476 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2477 tmp = SEXT40(ACC (OP[0])) << OP[1];
2481 if (tmp > SEXT40(MAX32))
2483 else if (tmp < SEXT40(MIN32))
2486 tmp = (tmp & MASK40);
2489 tmp = (tmp & MASK40);
2490 SET_ACC (OP[0], tmp);
2491 trace_output_40 (tmp);
2499 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2500 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2501 SET_GPR (OP[0], tmp);
2502 trace_output_16 (tmp);
2510 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2511 tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2512 SET_GPR (OP[0], tmp);
2513 trace_output_16 (tmp);
2520 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2521 if ((GPR (OP[1]) & 31) <= 16)
2523 int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2524 SET_ACC (OP[0], tmp);
2525 trace_output_40 (tmp);
2529 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2530 State.exception = SIGILL;
2540 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2541 tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2542 SET_GPR (OP[0], tmp);
2543 trace_output_16 (tmp);
2554 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2555 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2556 SET_ACC (OP[0], tmp);
2557 trace_output_40 (tmp);
2565 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2566 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2567 SET_GPR (OP[0], tmp);
2568 trace_output_16 (tmp);
2575 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2576 if ((GPR (OP[1]) & 31) <= 16)
2578 int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2579 SET_ACC (OP[0], tmp);
2580 trace_output_40 (tmp);
2584 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2585 State.exception = SIGILL;
2596 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2597 tmp = (GPR (OP[0]) >> OP[1]);
2598 SET_GPR (OP[0], tmp);
2599 trace_output_16 (tmp);
2610 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2611 tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2612 SET_ACC (OP[0], tmp);
2613 trace_output_40 (tmp);
2621 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2623 tmp = ((GPR (OP[0]) >> 1) | tmp);
2624 SET_GPR (OP[0], tmp);
2625 trace_output_16 (tmp);
2632 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2633 SW (OP[1] + GPR (OP[2]), GPR (OP[0]));
2634 trace_output_void ();
2641 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2642 SW (GPR (OP[1]), GPR (OP[0]));
2643 trace_output_void ();
2650 uint16 addr = GPR (OP[1]) - 2;
2651 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2654 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2655 State.exception = SIGILL;
2658 SW (addr, GPR (OP[0]));
2659 SET_GPR (OP[1], addr);
2660 trace_output_void ();
2667 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2668 SW (GPR (OP[1]), GPR (OP[0]));
2669 INC_ADDR (OP[1], 2);
2670 trace_output_void ();
2677 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2680 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2681 State.exception = SIGILL;
2684 SW (GPR (OP[1]), GPR (OP[0]));
2685 INC_ADDR (OP[1], -2);
2686 trace_output_void ();
2693 trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2694 SW (OP[1], GPR (OP[0]));
2695 trace_output_void ();
2702 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2703 SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0));
2704 SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1));
2705 trace_output_void ();
2712 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2713 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2714 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2715 trace_output_void ();
2722 uint16 addr = GPR (OP[1]) - 4;
2723 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2726 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2727 State.exception = SIGILL;
2730 SW (addr + 0, GPR (OP[0] + 0));
2731 SW (addr + 2, GPR (OP[0] + 1));
2732 SET_GPR (OP[1], addr);
2733 trace_output_void ();
2740 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2741 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2742 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2743 INC_ADDR (OP[1], 4);
2744 trace_output_void ();
2751 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2754 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2755 State.exception = SIGILL;
2758 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2759 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2760 INC_ADDR (OP[1], -4);
2761 trace_output_void ();
2768 trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2769 SW (OP [1] + 0, GPR (OP[0] + 0));
2770 SW (OP [1] + 2, GPR (OP[0] + 1));
2771 trace_output_void ();
2778 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2779 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2780 trace_output_void ();
2787 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2788 SB (GPR (OP[1]), GPR (OP[0]));
2789 trace_output_void ();
2796 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2797 State.exception = SIG_D10V_STOP;
2798 trace_output_void ();
2805 uint16 a = GPR (OP[0]);
2806 uint16 b = GPR (OP[1]);
2807 uint16 tmp = (a - b);
2808 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2809 /* see ../common/sim-alu.h for a more extensive discussion on how to
2810 compute the carry/overflow bits. */
2812 SET_GPR (OP[0], tmp);
2813 trace_output_16 (tmp);
2822 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2823 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
2826 if (tmp > SEXT40(MAX32))
2828 else if (tmp < SEXT40(MIN32))
2831 tmp = (tmp & MASK40);
2834 tmp = (tmp & MASK40);
2835 SET_ACC (OP[0], tmp);
2837 trace_output_40 (tmp);
2847 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2848 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
2851 if (tmp > SEXT40(MAX32))
2853 else if (tmp < SEXT40(MIN32))
2856 tmp = (tmp & MASK40);
2859 tmp = (tmp & MASK40);
2860 SET_ACC (OP[0], tmp);
2862 trace_output_40 (tmp);
2871 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2872 a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
2873 b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
2874 /* see ../common/sim-alu.h for a more extensive discussion on how to
2875 compute the carry/overflow bits */
2878 SET_GPR32 (OP[0], tmp);
2879 trace_output_32 (tmp);
2888 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2889 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
2890 SET_GPR32 (OP[0], tmp);
2891 trace_output_32 (tmp);
2900 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2901 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
2902 SET_GPR32 (OP[0], tmp);
2903 trace_output_32 (tmp);
2912 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2913 SET_PSW_F1 (PSW_F0);
2914 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
2915 if (tmp > SEXT40(MAX32))
2920 else if (tmp < SEXT40(MIN32))
2929 SET_GPR32 (OP[0], tmp);
2930 trace_output_32 (tmp);
2939 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2940 SET_PSW_F1 (PSW_F0);
2941 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
2942 if (tmp > SEXT40(MAX32))
2947 else if (tmp < SEXT40(MIN32))
2956 SET_GPR32 (OP[0], tmp);
2957 trace_output_32 (tmp);
2968 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2969 /* see ../common/sim-alu.h for a more extensive discussion on how to
2970 compute the carry/overflow bits. */
2971 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2972 tmp = ((unsigned)(unsigned16) GPR (OP[0])
2973 + (unsigned)(unsigned16) ( - OP[1]));
2974 SET_PSW_C (tmp >= (1 << 16));
2975 SET_GPR (OP[0], tmp);
2976 trace_output_16 (tmp);
2983 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2984 trace_output_void ();
2989 #if (DEBUG & DEBUG_TRAP) == 0
2991 uint16 vec = OP[0] + TRAP_VECTOR_START;
2994 SET_PSW (PSW & PSW_SM_BIT);
2998 #else /* if debugging use trap to print registers */
3001 static int first_time = 1;
3006 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
3007 for (i = 0; i < 16; i++)
3008 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
3009 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
3012 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3014 for (i = 0; i < 16; i++)
3015 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
3017 for (i = 0; i < 2; i++)
3018 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
3019 ((int)(ACC (i) >> 32) & 0xff),
3020 ((unsigned long) ACC (i)) & 0xffffffff);
3022 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
3023 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3024 (*d10v_callback->flush_stdout) (d10v_callback);
3028 case 15: /* new system call trap */
3029 /* Trap 15 is used for simulating low-level I/O */
3031 unsigned32 result = 0;
3034 /* Registers passed to trap 0 */
3036 #define FUNC GPR (4) /* function number */
3037 #define PARM1 GPR (0) /* optional parm 1 */
3038 #define PARM2 GPR (1) /* optional parm 2 */
3039 #define PARM3 GPR (2) /* optional parm 3 */
3040 #define PARM4 GPR (3) /* optional parm 3 */
3042 /* Registers set by trap 0 */
3044 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3045 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3046 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3048 /* Turn a pointer in a register into a pointer into real memory. */
3050 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3054 #if !defined(__GO32__) && !defined(_WIN32)
3055 case TARGET_SYS_fork:
3056 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3058 trace_output_16 (result);
3062 case TARGET_SYS_getpid:
3063 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3065 trace_output_16 (result);
3068 case TARGET_SYS_kill:
3069 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3070 if (PARM1 == getpid ())
3072 trace_output_void ();
3073 State.exception = PARM2;
3081 case 1: os_sig = SIGHUP; break;
3084 case 2: os_sig = SIGINT; break;
3087 case 3: os_sig = SIGQUIT; break;
3090 case 4: os_sig = SIGILL; break;
3093 case 5: os_sig = SIGTRAP; break;
3096 case 6: os_sig = SIGABRT; break;
3097 #elif defined(SIGIOT)
3098 case 6: os_sig = SIGIOT; break;
3101 case 7: os_sig = SIGEMT; break;
3104 case 8: os_sig = SIGFPE; break;
3107 case 9: os_sig = SIGKILL; break;
3110 case 10: os_sig = SIGBUS; break;
3113 case 11: os_sig = SIGSEGV; break;
3116 case 12: os_sig = SIGSYS; break;
3119 case 13: os_sig = SIGPIPE; break;
3122 case 14: os_sig = SIGALRM; break;
3125 case 15: os_sig = SIGTERM; break;
3128 case 16: os_sig = SIGURG; break;
3131 case 17: os_sig = SIGSTOP; break;
3134 case 18: os_sig = SIGTSTP; break;
3137 case 19: os_sig = SIGCONT; break;
3140 case 20: os_sig = SIGCHLD; break;
3141 #elif defined(SIGCLD)
3142 case 20: os_sig = SIGCLD; break;
3145 case 21: os_sig = SIGTTIN; break;
3148 case 22: os_sig = SIGTTOU; break;
3151 case 23: os_sig = SIGIO; break;
3152 #elif defined (SIGPOLL)
3153 case 23: os_sig = SIGPOLL; break;
3156 case 24: os_sig = SIGXCPU; break;
3159 case 25: os_sig = SIGXFSZ; break;
3162 case 26: os_sig = SIGVTALRM; break;
3165 case 27: os_sig = SIGPROF; break;
3168 case 28: os_sig = SIGWINCH; break;
3171 case 29: os_sig = SIGLOST; break;
3174 case 30: os_sig = SIGUSR1; break;
3177 case 31: os_sig = SIGUSR2; break;
3183 trace_output_void ();
3184 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3185 (*d10v_callback->flush_stdout) (d10v_callback);
3186 State.exception = SIGILL;
3190 RETVAL (kill (PARM1, PARM2));
3191 trace_output_16 (result);
3196 case TARGET_SYS_execve:
3197 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3198 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3199 (char **)MEMPTR (PARM3)));
3200 trace_output_16 (result);
3203 #ifdef TARGET_SYS_execv
3204 case TARGET_SYS_execv:
3205 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3206 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3207 trace_output_16 (result);
3211 case TARGET_SYS_pipe:
3216 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3218 RETVAL (pipe (host_fd));
3219 SW (buf, host_fd[0]);
3220 buf += sizeof(uint16);
3221 SW (buf, host_fd[1]);
3222 trace_output_16 (result);
3227 #ifdef TARGET_SYS_wait
3228 case TARGET_SYS_wait:
3231 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3232 RETVAL (wait (&status));
3235 trace_output_16 (result);
3241 case TARGET_SYS_getpid:
3242 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3244 trace_output_16 (result);
3247 case TARGET_SYS_kill:
3248 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3249 trace_output_void ();
3250 State.exception = PARM2;
3254 case TARGET_SYS_read:
3255 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3256 RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3258 trace_output_16 (result);
3261 case TARGET_SYS_write:
3262 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3264 RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3265 MEMPTR (PARM2), PARM3));
3267 RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3268 MEMPTR (PARM2), PARM3));
3269 trace_output_16 (result);
3272 case TARGET_SYS_lseek:
3273 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3274 RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3275 ((((unsigned long) PARM2) << 16)
3276 || (unsigned long) PARM3),
3278 trace_output_32 (result);
3281 case TARGET_SYS_close:
3282 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3283 RETVAL (d10v_callback->close (d10v_callback, PARM1));
3284 trace_output_16 (result);
3287 case TARGET_SYS_open:
3288 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3289 RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3290 trace_output_16 (result);
3293 case TARGET_SYS_exit:
3294 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3295 State.exception = SIG_D10V_EXIT;
3296 trace_output_void ();
3299 #ifdef TARGET_SYS_stat
3300 case TARGET_SYS_stat:
3301 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3302 /* stat system call */
3304 struct stat host_stat;
3307 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3311 /* The hard-coded offsets and sizes were determined by using
3312 * the D10V compiler on a test program that used struct stat.
3314 SW (buf, host_stat.st_dev);
3315 SW (buf+2, host_stat.st_ino);
3316 SW (buf+4, host_stat.st_mode);
3317 SW (buf+6, host_stat.st_nlink);
3318 SW (buf+8, host_stat.st_uid);
3319 SW (buf+10, host_stat.st_gid);
3320 SW (buf+12, host_stat.st_rdev);
3321 SLW (buf+16, host_stat.st_size);
3322 SLW (buf+20, host_stat.st_atime);
3323 SLW (buf+28, host_stat.st_mtime);
3324 SLW (buf+36, host_stat.st_ctime);
3326 trace_output_16 (result);
3330 case TARGET_SYS_chown:
3331 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3332 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3333 trace_output_16 (result);
3336 case TARGET_SYS_chmod:
3337 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3338 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3339 trace_output_16 (result);
3343 #ifdef TARGET_SYS_utime
3344 case TARGET_SYS_utime:
3345 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3346 /* Cast the second argument to void *, to avoid type mismatch
3347 if a prototype is present. */
3348 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3349 trace_output_16 (result);
3355 #ifdef TARGET_SYS_time
3356 case TARGET_SYS_time:
3357 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3358 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3359 trace_output_32 (result);
3365 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3367 if ((uint16) result == (uint16) -1)
3368 RETERR (d10v_callback->get_errno(d10v_callback));
3380 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3381 SET_PSW_F1 (PSW_F0);;
3382 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3383 trace_output_flag ();
3390 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3391 SET_PSW_F1 (PSW_F0);
3392 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3393 trace_output_flag ();
3400 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3402 trace_output_void ();
3410 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3411 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3412 SET_GPR (OP[0], tmp);
3413 trace_output_16 (tmp);
3421 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3422 tmp = (GPR (OP[1]) ^ OP[2]);
3423 SET_GPR (OP[0], tmp);
3424 trace_output_16 (tmp);