13 #include "targ-vals.h"
15 extern char *strrchr ();
47 PSW_MASK = (PSW_SM_BIT
62 move_to_cr (int cr, reg_t mask, reg_t val)
64 /* A MASK bit is set when the corresponding bit in the CR should
66 /* This assumes that (VAL & MASK) == 0 */
71 if ((mask & PSW_SM_BIT) == 0)
73 int new_sm = (val & PSW_SM_BIT) != 0;
74 SET_HELD_SP (PSW_SM, GPR (SP_IDX)); /* save old SP */
76 SET_GPR (SP_IDX, HELD_SP (new_sm)); /* restore new SP */
78 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
80 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
82 (*d10v_callback->printf_filtered)
84 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
86 State.exception = SIGILL;
89 /* keep an up-to-date psw around for tracing */
90 State.trace.psw = (State.trace.psw & mask) | val;
103 /* only issue an update if the register is being changed */
104 if ((State.cregs[cr] & ~mask) != val)
105 SLOT_PEND_MASK (State.cregs[cr], mask, val);
110 static void trace_input_func PARAMS ((char *name,
115 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
117 #ifndef SIZE_INSTRUCTION
118 #define SIZE_INSTRUCTION 8
121 #ifndef SIZE_OPERANDS
122 #define SIZE_OPERANDS 18
126 #define SIZE_VALUES 13
129 #ifndef SIZE_LOCATION
130 #define SIZE_LOCATION 20
137 #ifndef SIZE_LINE_NUMBER
138 #define SIZE_LINE_NUMBER 4
142 trace_input_func (name, in1, in2, in3)
155 const char *filename;
156 const char *functionname;
157 unsigned int linenumber;
160 if ((d10v_debug & DEBUG_TRACE) == 0)
163 switch (State.ins_type)
166 case INS_UNKNOWN: type = " ?"; break;
167 case INS_LEFT: type = " L"; break;
168 case INS_RIGHT: type = " R"; break;
169 case INS_LEFT_PARALLEL: type = "*L"; break;
170 case INS_RIGHT_PARALLEL: type = "*R"; break;
171 case INS_LEFT_COND_TEST: type = "?L"; break;
172 case INS_RIGHT_COND_TEST: type = "?R"; break;
173 case INS_LEFT_COND_EXE: type = "&L"; break;
174 case INS_RIGHT_COND_EXE: type = "&R"; break;
175 case INS_LONG: type = " B"; break;
178 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
179 (*d10v_callback->printf_filtered) (d10v_callback,
181 SIZE_PC, (unsigned)PC,
183 SIZE_INSTRUCTION, name);
188 byte_pc = decode_pc ();
189 if (text && byte_pc >= text_start && byte_pc < text_end)
191 filename = (const char *)0;
192 functionname = (const char *)0;
194 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
195 &filename, &functionname, &linenumber))
200 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
205 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
206 p += SIZE_LINE_NUMBER+2;
211 sprintf (p, "%s ", functionname);
216 char *q = strrchr (filename, '/');
217 sprintf (p, "%s ", (q) ? q+1 : filename);
226 (*d10v_callback->printf_filtered) (d10v_callback,
227 "0x%.*x %s: %-*.*s %-*s ",
228 SIZE_PC, (unsigned)PC,
230 SIZE_LOCATION, SIZE_LOCATION, buf,
231 SIZE_INSTRUCTION, name);
239 for (i = 0; i < 3; i++)
253 sprintf (p, "%sr%d", comma, OP[i]);
261 sprintf (p, "%scr%d", comma, OP[i]);
267 case OP_ACCUM_OUTPUT:
268 case OP_ACCUM_REVERSE:
269 sprintf (p, "%sa%d", comma, OP[i]);
275 sprintf (p, "%s%d", comma, OP[i]);
281 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
287 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
293 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
299 sprintf (p, "%s@r%d", comma, OP[i]);
305 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
311 sprintf (p, "%s@r%d+", comma, OP[i]);
317 sprintf (p, "%s@r%d-", comma, OP[i]);
323 sprintf (p, "%s@-r%d", comma, OP[i]);
331 sprintf (p, "%sf0", comma);
334 sprintf (p, "%sf1", comma);
337 sprintf (p, "%sc", comma);
345 if ((d10v_debug & DEBUG_VALUES) == 0)
349 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
354 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
357 for (i = 0; i < 3; i++)
363 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
369 case OP_ACCUM_OUTPUT:
371 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
379 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
380 (uint16) GPR (OP[i]));
384 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
385 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
390 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
391 (uint16) CREG (OP[i]));
395 case OP_ACCUM_REVERSE:
396 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
397 ((int)(ACC (OP[i]) >> 32) & 0xff),
398 ((unsigned long) ACC (OP[i])) & 0xffffffff);
402 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
407 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
408 (uint16)SEXT4(OP[i]));
412 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
413 (uint16)SEXT8(OP[i]));
417 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
418 (uint16)SEXT3(OP[i]));
423 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
427 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
431 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
437 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
439 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
440 (uint16)GPR (OP[i + 1]));
445 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
450 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
455 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
463 (*d10v_callback->flush_stdout) (d10v_callback);
467 do_trace_output_flush (void)
469 (*d10v_callback->flush_stdout) (d10v_callback);
473 do_trace_output_finish (void)
475 (*d10v_callback->printf_filtered) (d10v_callback,
476 " F0=%d F1=%d C=%d\n",
477 (State.trace.psw & PSW_F0_BIT) != 0,
478 (State.trace.psw & PSW_F1_BIT) != 0,
479 (State.trace.psw & PSW_C_BIT) != 0);
480 (*d10v_callback->flush_stdout) (d10v_callback);
484 trace_output_40 (uint64 val)
486 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
488 (*d10v_callback->printf_filtered) (d10v_callback,
489 " :: %*s0x%.2x%.8lx",
492 ((int)(val >> 32) & 0xff),
493 ((unsigned long) val) & 0xffffffff);
494 do_trace_output_finish ();
499 trace_output_32 (uint32 val)
501 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
503 (*d10v_callback->printf_filtered) (d10v_callback,
508 do_trace_output_finish ();
513 trace_output_16 (uint16 val)
515 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
517 (*d10v_callback->printf_filtered) (d10v_callback,
522 do_trace_output_finish ();
529 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
531 (*d10v_callback->printf_filtered) (d10v_callback, "\n");
532 do_trace_output_flush ();
539 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
541 (*d10v_callback->printf_filtered) (d10v_callback,
545 do_trace_output_finish ();
553 #define trace_input(NAME, IN1, IN2, IN3)
554 #define trace_output(RESULT)
562 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
572 SET_GPR (OP[0], tmp);
573 trace_output_16 (tmp);
581 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
584 tmp = SEXT40 (ACC (OP[0]));
590 if (tmp > SEXT40(MAX32))
592 else if (tmp < SEXT40(MIN32))
595 tmp = (tmp & MASK40);
598 tmp = (tmp & MASK40);
603 tmp = (tmp & MASK40);
606 SET_ACC (OP[0], tmp);
607 trace_output_40 (tmp);
614 uint16 a = GPR (OP[0]);
615 uint16 b = GPR (OP[1]);
616 uint16 tmp = (a + b);
617 trace_input ("add", OP_REG, OP_REG, OP_VOID);
619 SET_GPR (OP[0], tmp);
620 trace_output_16 (tmp);
628 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
630 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
633 if (tmp > SEXT40(MAX32))
635 else if (tmp < SEXT40(MIN32))
638 tmp = (tmp & MASK40);
641 tmp = (tmp & MASK40);
642 SET_ACC (OP[0], tmp);
643 trace_output_40 (tmp);
651 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
653 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
656 if (tmp > SEXT40(MAX32))
658 else if (tmp < SEXT40(MIN32))
661 tmp = (tmp & MASK40);
664 tmp = (tmp & MASK40);
665 SET_ACC (OP[0], tmp);
666 trace_output_40 (tmp);
674 uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
675 uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
676 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
679 SET_GPR (OP[0] + 0, (tmp >> 16));
680 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
681 trace_output_32 (tmp);
688 uint16 a = GPR (OP[1]);
690 uint16 tmp = (a + b);
691 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
693 SET_GPR (OP[0], tmp);
694 trace_output_16 (tmp);
702 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
704 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
705 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
706 SET_GPR (OP[0] + 1, (tmp & 0xffff));
707 trace_output_32 (tmp);
715 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
717 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
718 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
719 SET_GPR (OP[0] + 1, tmp & 0xffff);
720 trace_output_32 (tmp);
730 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
731 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
732 if (tmp > SEXT40(MAX32))
737 else if (tmp < SEXT40(MIN32))
746 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
747 SET_GPR (OP[0] + 1, (tmp & 0xffff));
748 trace_output_32 (tmp);
758 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
759 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
760 if (tmp > SEXT40(MAX32))
765 else if (tmp < SEXT40(MIN32))
774 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
775 SET_GPR (OP[0] + 1, (tmp & 0xffff));
776 trace_output_32 (tmp);
783 uint16 a = GPR (OP[0]);
790 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
792 SET_GPR (OP[0], tmp);
793 trace_output_16 (tmp);
800 uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
801 trace_input ("and", OP_REG, OP_REG, OP_VOID);
802 SET_GPR (OP[0], tmp);
803 trace_output_16 (tmp);
810 uint16 tmp = GPR (OP[1]) & OP[2];
811 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
812 SET_GPR (OP[0], tmp);
813 trace_output_16 (tmp);
821 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
822 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
823 SET_GPR (OP[0], tmp);
824 trace_output_16 (tmp);
831 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
832 SET_GPR (13, PC + 1);
833 JMP( PC + SEXT8 (OP[0]));
834 trace_output_void ();
841 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
842 SET_GPR (13, (PC + 1));
844 trace_output_void ();
852 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
853 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
854 SET_GPR (OP[0], tmp);
855 trace_output_16 (tmp);
862 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
863 JMP (PC + SEXT8 (OP[0]));
864 trace_output_void ();
871 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
873 trace_output_void ();
880 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
882 JMP (PC + SEXT8 (OP[0]));
883 trace_output_flag ();
890 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
893 trace_output_flag ();
900 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
902 JMP (PC + SEXT8 (OP[0]));
903 trace_output_flag ();
910 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
913 trace_output_flag ();
921 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
922 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
923 SET_GPR (OP[0], tmp);
924 trace_output_16 (tmp);
931 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
933 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
934 trace_output_flag ();
941 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
950 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
952 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
953 trace_output_flag ();
960 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
962 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
963 trace_output_flag ();
970 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
972 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
973 trace_output_flag ();
980 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
982 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
983 trace_output_flag ();
990 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
992 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
993 trace_output_flag ();
1000 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1001 SET_PSW_F1 (PSW_F0);
1002 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1003 trace_output_flag ();
1010 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1011 SET_PSW_F1 (PSW_F0);
1012 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1013 trace_output_flag ();
1020 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1021 SET_PSW_F1 (PSW_F0);
1022 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1023 trace_output_flag ();
1030 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1031 SET_PSW_F1 (PSW_F0);
1032 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1033 trace_output_flag ();
1040 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1041 SET_PSW_F1 (PSW_F0);
1042 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1043 trace_output_flag ();
1052 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1056 else if (OP[1] == 1)
1065 trace_output_flag ();
1072 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1074 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1075 The conditional below is for either of the instruction pairs
1076 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1077 where the dbt instruction should be interpreted.
1079 The module `sim-break' provides a more effective mechanism for
1080 detecting GDB planted breakpoints. The code below may,
1081 eventually, be changed to use that mechanism. */
1083 if (State.ins_type == INS_LEFT
1084 || State.ins_type == INS_RIGHT)
1086 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1089 SET_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1090 JMP (DBT_VECTOR_START);
1091 trace_output_void ();
1095 State.exception = SIGTRAP;
1103 uint16 foo, tmp, tmpf;
1107 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1108 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1109 tmp = (int16)foo - (int16)(GPR (OP[1]));
1110 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1111 hi = ((tmpf == 1) ? tmp : foo);
1112 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1113 SET_GPR (OP[0] + 0, hi);
1114 SET_GPR (OP[0] + 1, lo);
1115 trace_output_32 (((uint32) hi << 16) | lo);
1122 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1123 State.exe = (PSW_F0 == 0);
1124 trace_output_flag ();
1131 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1132 State.exe = (PSW_F0 != 0);
1133 trace_output_flag ();
1140 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1141 State.exe = (PSW_F1 == 0);
1142 trace_output_flag ();
1149 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1150 State.exe = (PSW_F1 != 0);
1151 trace_output_flag ();
1158 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1159 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1160 trace_output_flag ();
1167 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1168 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1169 trace_output_flag ();
1176 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1177 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1178 trace_output_flag ();
1185 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1186 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1187 trace_output_flag ();
1197 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1198 if (((int16)GPR (OP[1])) >= 0)
1199 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1201 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1208 SET_GPR (OP[0], (i - 1));
1209 trace_output_16 (i - 1);
1214 SET_GPR (OP[0], 16);
1215 trace_output_16 (16);
1225 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1226 tmp = SEXT40(ACC (OP[1]));
1228 tmp = ~tmp & MASK40;
1230 foo = 0x4000000000LL;
1235 SET_GPR (OP[0], i - 9);
1236 trace_output_16 (i - 9);
1241 SET_GPR (OP[0], 16);
1242 trace_output_16 (16);
1249 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1250 SET_GPR (13, PC + 1);
1252 trace_output_void ();
1259 trace_input ("jmp", OP_REG,
1260 (OP[0] == 13) ? OP_R0 : OP_VOID,
1261 (OP[0] == 13) ? OP_R1 : OP_VOID);
1264 trace_output_void ();
1272 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1273 tmp = RW (OP[1] + GPR (OP[2]));
1274 SET_GPR (OP[0], tmp);
1275 trace_output_16 (tmp);
1283 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1284 tmp = RW (GPR (OP[1]));
1285 SET_GPR (OP[0], tmp);
1287 INC_ADDR (OP[1], -2);
1288 trace_output_16 (tmp);
1296 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1297 tmp = RW (GPR (OP[1]));
1298 SET_GPR (OP[0], tmp);
1300 INC_ADDR (OP[1], 2);
1301 trace_output_16 (tmp);
1309 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1310 tmp = RW (GPR (OP[1]));
1311 SET_GPR (OP[0], tmp);
1312 trace_output_16 (tmp);
1320 uint16 addr = GPR (OP[2]);
1321 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1322 tmp = RLW (OP[1] + addr);
1323 SET_GPR32 (OP[0], tmp);
1324 trace_output_32 (tmp);
1331 uint16 addr = GPR (OP[1]);
1333 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1335 SET_GPR32 (OP[0], tmp);
1337 INC_ADDR (OP[1], -4);
1338 trace_output_32 (tmp);
1346 uint16 addr = GPR (OP[1]);
1347 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1349 SET_GPR32 (OP[0], tmp);
1351 INC_ADDR (OP[1], 4);
1352 trace_output_32 (tmp);
1359 uint16 addr = GPR (OP[1]);
1361 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1362 tmp = RLW (addr + 0);
1363 SET_GPR32 (OP[0], tmp);
1364 trace_output_32 (tmp);
1372 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1373 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1374 SET_GPR (OP[0], tmp);
1375 trace_output_16 (tmp);
1383 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1384 tmp = SEXT8 (RB (GPR (OP[1])));
1385 SET_GPR (OP[0], tmp);
1386 trace_output_16 (tmp);
1394 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1395 tmp = SEXT4 (OP[1]);
1396 SET_GPR (OP[0], tmp);
1397 trace_output_16 (tmp);
1405 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1407 SET_GPR (OP[0], tmp);
1408 trace_output_16 (tmp);
1416 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1417 tmp = RB (OP[1] + GPR (OP[2]));
1418 SET_GPR (OP[0], tmp);
1419 trace_output_16 (tmp);
1427 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1428 tmp = RB (GPR (OP[1]));
1429 SET_GPR (OP[0], tmp);
1430 trace_output_16 (tmp);
1439 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1440 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1443 tmp = SEXT40( (tmp << 1) & MASK40);
1445 if (PSW_ST && tmp > SEXT40(MAX32))
1448 tmp += SEXT40 (ACC (OP[0]));
1451 if (tmp > SEXT40(MAX32))
1453 else if (tmp < SEXT40(MIN32))
1456 tmp = (tmp & MASK40);
1459 tmp = (tmp & MASK40);
1460 SET_ACC (OP[0], tmp);
1461 trace_output_40 (tmp);
1470 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1471 tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1473 tmp = SEXT40 ((tmp << 1) & MASK40);
1474 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1475 SET_ACC (OP[0], tmp);
1476 trace_output_40 (tmp);
1487 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1488 src1 = (uint16) GPR (OP[1]);
1489 src2 = (uint16) GPR (OP[2]);
1493 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1494 SET_ACC (OP[0], tmp);
1495 trace_output_40 (tmp);
1503 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1504 SET_PSW_F1 (PSW_F0);
1505 if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1515 SET_GPR (OP[0], tmp);
1516 trace_output_16 (tmp);
1525 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1526 SET_PSW_F1 (PSW_F0);
1527 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1528 if (tmp > SEXT40 (ACC (OP[0])))
1530 tmp = (tmp & MASK40);
1538 SET_ACC (OP[0], tmp);
1539 trace_output_40 (tmp);
1547 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1548 SET_PSW_F1 (PSW_F0);
1549 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1559 SET_ACC (OP[0], tmp);
1560 trace_output_40 (tmp);
1569 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1570 SET_PSW_F1 (PSW_F0);
1571 if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1581 SET_GPR (OP[0], tmp);
1582 trace_output_16 (tmp);
1591 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1592 SET_PSW_F1 (PSW_F0);
1593 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1594 if (tmp < SEXT40(ACC (OP[0])))
1596 tmp = (tmp & MASK40);
1604 SET_ACC (OP[0], tmp);
1605 trace_output_40 (tmp);
1613 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1614 SET_PSW_F1 (PSW_F0);
1615 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1625 SET_ACC (OP[0], tmp);
1626 trace_output_40 (tmp);
1635 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1636 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1639 tmp = SEXT40 ((tmp << 1) & MASK40);
1641 if (PSW_ST && tmp > SEXT40(MAX32))
1644 tmp = SEXT40(ACC (OP[0])) - tmp;
1647 if (tmp > SEXT40(MAX32))
1649 else if (tmp < SEXT40(MIN32))
1652 tmp = (tmp & MASK40);
1656 tmp = (tmp & MASK40);
1658 SET_ACC (OP[0], tmp);
1659 trace_output_40 (tmp);
1668 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1669 tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1671 tmp = SEXT40( (tmp << 1) & MASK40);
1672 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1673 SET_ACC (OP[0], tmp);
1674 trace_output_40 (tmp);
1685 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1686 src1 = (uint16) GPR (OP[1]);
1687 src2 = (uint16) GPR (OP[2]);
1691 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1692 SET_ACC (OP[0], tmp);
1693 trace_output_40 (tmp);
1701 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1702 tmp = GPR (OP[0]) * GPR (OP[1]);
1703 SET_GPR (OP[0], tmp);
1704 trace_output_16 (tmp);
1713 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1714 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1717 tmp = SEXT40 ((tmp << 1) & MASK40);
1719 if (PSW_ST && tmp > SEXT40(MAX32))
1722 tmp = (tmp & MASK40);
1723 SET_ACC (OP[0], tmp);
1724 trace_output_40 (tmp);
1733 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1734 tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1738 tmp = (tmp & MASK40);
1739 SET_ACC (OP[0], tmp);
1740 trace_output_40 (tmp);
1751 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1752 src1 = (uint16) GPR (OP[1]);
1753 src2 = (uint16) GPR (OP[2]);
1757 tmp = (tmp & MASK40);
1758 SET_ACC (OP[0], tmp);
1759 trace_output_40 (tmp);
1767 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1769 SET_GPR (OP[0], tmp);
1770 trace_output_16 (tmp);
1778 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1779 tmp = GPR32 (OP[1]);
1780 SET_GPR32 (OP[0], tmp);
1781 trace_output_32 (tmp);
1789 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1791 SET_GPR32 (OP[0], tmp);
1792 trace_output_32 (tmp);
1800 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1801 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1802 SET_ACC (OP[1], tmp);
1803 trace_output_40 (tmp);
1811 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1813 SET_ACC (OP[0], tmp);
1814 trace_output_40 (tmp);
1822 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1823 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1824 SET_GPR (OP[0], tmp);
1825 trace_output_16 (tmp);
1833 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1837 SET_GPR (OP[0], tmp);
1841 trace_output_16 (tmp);
1849 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1853 SET_GPR (OP[0], tmp);
1857 trace_output_16 (tmp);
1865 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1866 tmp = ((ACC (OP[1]) >> 32) & 0xff);
1867 SET_GPR (OP[0], tmp);
1868 trace_output_16 (tmp);
1876 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1877 tmp = (ACC (OP[1]) >> 16);
1878 SET_GPR (OP[0], tmp);
1879 trace_output_16 (tmp);
1887 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1889 SET_GPR (OP[0], tmp);
1890 trace_output_16 (tmp);
1898 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1900 SET_GPR (OP[0], tmp);
1901 trace_output_16 (tmp);
1909 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1910 tmp = ((ACC (OP[1]) & MASK32)
1911 | ((int64)(GPR (OP[0]) & 0xff) << 32));
1912 SET_ACC (OP[1], tmp);
1913 trace_output_40 (tmp);
1921 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1922 tmp = ACC (OP[1]) & 0xffff;
1923 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
1924 SET_ACC (OP[1], tmp);
1925 trace_output_40 (tmp);
1933 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1934 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
1935 SET_ACC (OP[1], tmp);
1936 trace_output_40 (tmp);
1944 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1946 tmp = SET_CREG (OP[1], tmp);
1947 trace_output_16 (tmp);
1955 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
1956 tmp = (GPR (OP[1]) & 0xff);
1957 SET_GPR (OP[0], tmp);
1958 trace_output_16 (tmp);
1966 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
1967 tmp = - GPR (OP[0]);
1968 SET_GPR (OP[0], tmp);
1969 trace_output_16 (tmp);
1978 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
1979 tmp = -SEXT40(ACC (OP[0]));
1982 if (tmp > SEXT40(MAX32))
1984 else if (tmp < SEXT40(MIN32))
1987 tmp = (tmp & MASK40);
1990 tmp = (tmp & MASK40);
1991 SET_ACC (OP[0], tmp);
1992 trace_output_40 (tmp);
2000 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2002 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2003 switch (State.ins_type)
2006 ins_type_counters[ (int)INS_UNKNOWN ]++;
2009 case INS_LEFT_PARALLEL:
2010 /* Don't count a parallel op that includes a NOP as a true parallel op */
2011 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2012 ins_type_counters[ (int)INS_RIGHT ]++;
2013 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2017 case INS_LEFT_COND_EXE:
2018 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2021 case INS_RIGHT_PARALLEL:
2022 /* Don't count a parallel op that includes a NOP as a true parallel op */
2023 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2024 ins_type_counters[ (int)INS_LEFT ]++;
2025 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2029 case INS_RIGHT_COND_EXE:
2030 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2034 trace_output_void ();
2042 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2044 SET_GPR (OP[0], tmp);
2045 trace_output_16 (tmp);
2053 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2054 tmp = (GPR (OP[0]) | GPR (OP[1]));
2055 SET_GPR (OP[0], tmp);
2056 trace_output_16 (tmp);
2064 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2065 tmp = (GPR (OP[1]) | OP[2]);
2066 SET_GPR (OP[0], tmp);
2067 trace_output_16 (tmp);
2075 int shift = SEXT3 (OP[2]);
2077 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2080 (*d10v_callback->printf_filtered) (d10v_callback,
2081 "ERROR at PC 0x%x: instruction only valid for A0\n",
2083 State.exception = SIGILL;
2086 SET_PSW_F1 (PSW_F0);
2087 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2093 tmp >>= 16; /* look at bits 0:43 */
2094 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2099 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2108 SET_GPR32 (OP[0], tmp);
2109 trace_output_32 (tmp);
2117 int shift = SEXT3 (OP[2]);
2119 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2120 SET_PSW_F1 (PSW_F0);
2122 tmp = SEXT40 (ACC (OP[1])) << shift;
2124 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2127 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2132 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2142 SET_GPR (OP[0], tmp);
2143 trace_output_16 (tmp);
2150 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2152 SET_RPT_E (PC + OP[1]);
2153 SET_RPT_C (GPR (OP[0]));
2155 if (GPR (OP[0]) == 0)
2157 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2158 State.exception = SIGILL;
2162 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2163 State.exception = SIGILL;
2165 trace_output_void ();
2172 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2174 SET_RPT_E (PC + OP[1]);
2179 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2180 State.exception = SIGILL;
2184 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2185 State.exception = SIGILL;
2187 trace_output_void ();
2194 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2195 SET_CREG (PSW_CR, DPSW);
2197 trace_output_void ();
2204 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2205 SET_CREG (PSW_CR, BPSW);
2207 trace_output_void ();
2216 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2217 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2220 if (tmp > SEXT40(MAX32))
2222 else if (tmp < SEXT40(MIN32))
2225 tmp = (tmp & MASK40);
2228 tmp = (tmp & MASK40);
2229 SET_ACC (OP[0], tmp);
2230 trace_output_40 (tmp);
2238 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2239 tmp = ((PSW_F0 == 0) ? 1 : 0);
2240 SET_GPR (OP[0], tmp);
2241 trace_output_16 (tmp);
2249 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2250 tmp = ((PSW_F0 == 1) ? 1 : 0);
2251 SET_GPR (OP[0], tmp);
2252 trace_output_16 (tmp);
2259 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2261 trace_output_void ();
2269 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2270 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2271 SET_GPR (OP[0], tmp);
2272 trace_output_16 (tmp);
2280 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2281 if ((GPR (OP[1]) & 31) <= 16)
2282 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2285 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2286 State.exception = SIGILL;
2292 if (tmp > SEXT40(MAX32))
2294 else if (tmp < SEXT40(MIN32))
2297 tmp = (tmp & MASK40);
2300 tmp = (tmp & MASK40);
2301 SET_ACC (OP[0], tmp);
2302 trace_output_40 (tmp);
2310 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2311 tmp = (GPR (OP[0]) << OP[1]);
2312 SET_GPR (OP[0], tmp);
2313 trace_output_16 (tmp);
2325 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2326 tmp = SEXT40(ACC (OP[0])) << OP[1];
2330 if (tmp > SEXT40(MAX32))
2332 else if (tmp < SEXT40(MIN32))
2335 tmp = (tmp & MASK40);
2338 tmp = (tmp & MASK40);
2339 SET_ACC (OP[0], tmp);
2340 trace_output_40 (tmp);
2348 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2349 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2350 SET_GPR (OP[0], tmp);
2351 trace_output_16 (tmp);
2359 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2360 tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2361 SET_GPR (OP[0], tmp);
2362 trace_output_16 (tmp);
2369 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2370 if ((GPR (OP[1]) & 31) <= 16)
2372 int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2373 SET_ACC (OP[0], tmp);
2374 trace_output_40 (tmp);
2378 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2379 State.exception = SIGILL;
2389 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2390 tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2391 SET_GPR (OP[0], tmp);
2392 trace_output_16 (tmp);
2403 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2404 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2405 SET_ACC (OP[0], tmp);
2406 trace_output_40 (tmp);
2414 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2415 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2416 SET_GPR (OP[0], tmp);
2417 trace_output_16 (tmp);
2424 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2425 if ((GPR (OP[1]) & 31) <= 16)
2427 int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2428 SET_ACC (OP[0], tmp);
2429 trace_output_40 (tmp);
2433 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2434 State.exception = SIGILL;
2445 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2446 tmp = (GPR (OP[0]) >> OP[1]);
2447 SET_GPR (OP[0], tmp);
2448 trace_output_16 (tmp);
2459 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2460 tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2461 SET_ACC (OP[0], tmp);
2462 trace_output_40 (tmp);
2470 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2472 tmp = ((GPR (OP[0]) >> 1) | tmp);
2473 SET_GPR (OP[0], tmp);
2474 trace_output_16 (tmp);
2481 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2482 SW (OP[1] + GPR (OP[2]), GPR (OP[0]));
2483 trace_output_void ();
2490 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2491 SW (GPR (OP[1]), GPR (OP[0]));
2492 trace_output_void ();
2499 uint16 addr = GPR (OP[1]) - 2;
2500 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2503 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2504 State.exception = SIGILL;
2507 SW (addr, GPR (OP[0]));
2508 SET_GPR (OP[1], addr);
2509 trace_output_void ();
2516 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2517 SW (GPR (OP[1]), GPR (OP[0]));
2518 INC_ADDR (OP[1], 2);
2519 trace_output_void ();
2526 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2529 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2530 State.exception = SIGILL;
2533 SW (GPR (OP[1]), GPR (OP[0]));
2534 INC_ADDR (OP[1], -2);
2535 trace_output_void ();
2542 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2543 SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0));
2544 SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1));
2545 trace_output_void ();
2552 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2553 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2554 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2555 trace_output_void ();
2562 uint16 addr = GPR (OP[1]) - 4;
2563 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2566 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2567 State.exception = SIGILL;
2570 SW (addr + 0, GPR (OP[0] + 0));
2571 SW (addr + 2, GPR (OP[0] + 1));
2572 SET_GPR (OP[1], addr);
2573 trace_output_void ();
2580 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2581 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2582 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2583 INC_ADDR (OP[1], 4);
2584 trace_output_void ();
2591 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2594 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2595 State.exception = SIGILL;
2598 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2599 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2600 INC_ADDR (OP[1], -4);
2601 trace_output_void ();
2608 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2609 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2610 trace_output_void ();
2617 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2618 SB (GPR (OP[1]), GPR (OP[0]));
2619 trace_output_void ();
2626 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2627 State.exception = SIG_D10V_STOP;
2628 trace_output_void ();
2635 uint16 a = GPR (OP[0]);
2636 uint16 b = GPR (OP[1]);
2637 uint16 tmp = (a - b);
2638 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2639 /* see ../common/sim-alu.h for a more extensive discussion on how to
2640 compute the carry/overflow bits. */
2642 SET_GPR (OP[0], tmp);
2643 trace_output_16 (tmp);
2652 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2653 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
2656 if (tmp > SEXT40(MAX32))
2658 else if (tmp < SEXT40(MIN32))
2661 tmp = (tmp & MASK40);
2664 tmp = (tmp & MASK40);
2665 SET_ACC (OP[0], tmp);
2667 trace_output_40 (tmp);
2677 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2678 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
2681 if (tmp > SEXT40(MAX32))
2683 else if (tmp < SEXT40(MIN32))
2686 tmp = (tmp & MASK40);
2689 tmp = (tmp & MASK40);
2690 SET_ACC (OP[0], tmp);
2692 trace_output_40 (tmp);
2701 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2702 a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
2703 b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
2704 /* see ../common/sim-alu.h for a more extensive discussion on how to
2705 compute the carry/overflow bits */
2708 SET_GPR32 (OP[0], tmp);
2709 trace_output_32 (tmp);
2718 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2719 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
2720 SET_GPR32 (OP[0], tmp);
2721 trace_output_32 (tmp);
2730 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2731 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
2732 SET_GPR32 (OP[0], tmp);
2733 trace_output_32 (tmp);
2742 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2743 SET_PSW_F1 (PSW_F0);
2744 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
2745 if (tmp > SEXT40(MAX32))
2750 else if (tmp < SEXT40(MIN32))
2759 SET_GPR32 (OP[0], tmp);
2760 trace_output_32 (tmp);
2769 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2770 SET_PSW_F1 (PSW_F0);
2771 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
2772 if (tmp > SEXT40(MAX32))
2777 else if (tmp < SEXT40(MIN32))
2786 SET_GPR32 (OP[0], tmp);
2787 trace_output_32 (tmp);
2798 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2799 /* see ../common/sim-alu.h for a more extensive discussion on how to
2800 compute the carry/overflow bits. */
2801 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2802 tmp = ((unsigned)(unsigned16) GPR (OP[0])
2803 + (unsigned)(unsigned16) ( - OP[1]));
2804 SET_PSW_C (tmp >= (1 << 16));
2805 SET_GPR (OP[0], tmp);
2806 trace_output_16 (tmp);
2813 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2814 trace_output_void ();
2819 #if (DEBUG & DEBUG_TRAP) == 0
2821 uint16 vec = OP[0] + TRAP_VECTOR_START;
2824 SET_PSW (PSW & PSW_SM_BIT);
2828 #else /* if debugging use trap to print registers */
2831 static int first_time = 1;
2836 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
2837 for (i = 0; i < 16; i++)
2838 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
2839 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
2842 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
2844 for (i = 0; i < 16; i++)
2845 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
2847 for (i = 0; i < 2; i++)
2848 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
2849 ((int)(ACC (i) >> 32) & 0xff),
2850 ((unsigned long) ACC (i)) & 0xffffffff);
2852 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
2853 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
2854 (*d10v_callback->flush_stdout) (d10v_callback);
2858 case 15: /* new system call trap */
2859 /* Trap 15 is used for simulating low-level I/O */
2861 unsigned32 result = 0;
2864 /* Registers passed to trap 0 */
2866 #define FUNC GPR (4) /* function number */
2867 #define PARM1 GPR (0) /* optional parm 1 */
2868 #define PARM2 GPR (1) /* optional parm 2 */
2869 #define PARM3 GPR (2) /* optional parm 3 */
2870 #define PARM4 GPR (3) /* optional parm 3 */
2872 /* Registers set by trap 0 */
2874 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
2875 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
2876 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
2878 /* Turn a pointer in a register into a pointer into real memory. */
2880 #define MEMPTR(x) ((char *)(dmem_addr(x)))
2884 #if !defined(__GO32__) && !defined(_WIN32)
2885 case TARGET_SYS_fork:
2886 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
2888 trace_output_16 (result);
2892 case TARGET_SYS_getpid:
2893 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
2895 trace_output_16 (result);
2898 case TARGET_SYS_kill:
2899 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
2900 if (PARM1 == getpid ())
2902 trace_output_void ();
2903 State.exception = PARM2;
2911 case 1: os_sig = SIGHUP; break;
2914 case 2: os_sig = SIGINT; break;
2917 case 3: os_sig = SIGQUIT; break;
2920 case 4: os_sig = SIGILL; break;
2923 case 5: os_sig = SIGTRAP; break;
2926 case 6: os_sig = SIGABRT; break;
2927 #elif defined(SIGIOT)
2928 case 6: os_sig = SIGIOT; break;
2931 case 7: os_sig = SIGEMT; break;
2934 case 8: os_sig = SIGFPE; break;
2937 case 9: os_sig = SIGKILL; break;
2940 case 10: os_sig = SIGBUS; break;
2943 case 11: os_sig = SIGSEGV; break;
2946 case 12: os_sig = SIGSYS; break;
2949 case 13: os_sig = SIGPIPE; break;
2952 case 14: os_sig = SIGALRM; break;
2955 case 15: os_sig = SIGTERM; break;
2958 case 16: os_sig = SIGURG; break;
2961 case 17: os_sig = SIGSTOP; break;
2964 case 18: os_sig = SIGTSTP; break;
2967 case 19: os_sig = SIGCONT; break;
2970 case 20: os_sig = SIGCHLD; break;
2971 #elif defined(SIGCLD)
2972 case 20: os_sig = SIGCLD; break;
2975 case 21: os_sig = SIGTTIN; break;
2978 case 22: os_sig = SIGTTOU; break;
2981 case 23: os_sig = SIGIO; break;
2982 #elif defined (SIGPOLL)
2983 case 23: os_sig = SIGPOLL; break;
2986 case 24: os_sig = SIGXCPU; break;
2989 case 25: os_sig = SIGXFSZ; break;
2992 case 26: os_sig = SIGVTALRM; break;
2995 case 27: os_sig = SIGPROF; break;
2998 case 28: os_sig = SIGWINCH; break;
3001 case 29: os_sig = SIGLOST; break;
3004 case 30: os_sig = SIGUSR1; break;
3007 case 31: os_sig = SIGUSR2; break;
3013 trace_output_void ();
3014 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3015 (*d10v_callback->flush_stdout) (d10v_callback);
3016 State.exception = SIGILL;
3020 RETVAL (kill (PARM1, PARM2));
3021 trace_output_16 (result);
3026 case TARGET_SYS_execve:
3027 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3028 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3029 (char **)MEMPTR (PARM3)));
3030 trace_output_16 (result);
3033 #ifdef TARGET_SYS_execv
3034 case TARGET_SYS_execv:
3035 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3036 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3037 trace_output_16 (result);
3041 case TARGET_SYS_pipe:
3046 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3048 RETVAL (pipe (host_fd));
3049 SW (buf, host_fd[0]);
3050 buf += sizeof(uint16);
3051 SW (buf, host_fd[1]);
3052 trace_output_16 (result);
3057 #ifdef TARGET_SYS_wait
3058 case TARGET_SYS_wait:
3061 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3062 RETVAL (wait (&status));
3065 trace_output_16 (result);
3071 case TARGET_SYS_getpid:
3072 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3074 trace_output_16 (result);
3077 case TARGET_SYS_kill:
3078 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3079 trace_output_void ();
3080 State.exception = PARM2;
3084 case TARGET_SYS_read:
3085 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3086 RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3088 trace_output_16 (result);
3091 case TARGET_SYS_write:
3092 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3094 RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3095 MEMPTR (PARM2), PARM3));
3097 RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3098 MEMPTR (PARM2), PARM3));
3099 trace_output_16 (result);
3102 case TARGET_SYS_lseek:
3103 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3104 RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3105 ((((unsigned long) PARM2) << 16)
3106 || (unsigned long) PARM3),
3108 trace_output_32 (result);
3111 case TARGET_SYS_close:
3112 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3113 RETVAL (d10v_callback->close (d10v_callback, PARM1));
3114 trace_output_16 (result);
3117 case TARGET_SYS_open:
3118 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3119 RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3120 trace_output_16 (result);
3123 case TARGET_SYS_exit:
3124 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3125 State.exception = SIG_D10V_EXIT;
3126 trace_output_void ();
3129 #ifdef TARGET_SYS_stat
3130 case TARGET_SYS_stat:
3131 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3132 /* stat system call */
3134 struct stat host_stat;
3137 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3141 /* The hard-coded offsets and sizes were determined by using
3142 * the D10V compiler on a test program that used struct stat.
3144 SW (buf, host_stat.st_dev);
3145 SW (buf+2, host_stat.st_ino);
3146 SW (buf+4, host_stat.st_mode);
3147 SW (buf+6, host_stat.st_nlink);
3148 SW (buf+8, host_stat.st_uid);
3149 SW (buf+10, host_stat.st_gid);
3150 SW (buf+12, host_stat.st_rdev);
3151 SLW (buf+16, host_stat.st_size);
3152 SLW (buf+20, host_stat.st_atime);
3153 SLW (buf+28, host_stat.st_mtime);
3154 SLW (buf+36, host_stat.st_ctime);
3156 trace_output_16 (result);
3160 case TARGET_SYS_chown:
3161 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3162 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3163 trace_output_16 (result);
3166 case TARGET_SYS_chmod:
3167 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3168 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3169 trace_output_16 (result);
3173 #ifdef TARGET_SYS_utime
3174 case TARGET_SYS_utime:
3175 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3176 /* Cast the second argument to void *, to avoid type mismatch
3177 if a prototype is present. */
3178 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3179 trace_output_16 (result);
3185 #ifdef TARGET_SYS_time
3186 case TARGET_SYS_time:
3187 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3188 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3189 trace_output_32 (result);
3195 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3197 if ((uint16) result == (uint16) -1)
3198 RETERR (d10v_callback->get_errno(d10v_callback));
3210 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3211 SET_PSW_F1 (PSW_F0);;
3212 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3213 trace_output_flag ();
3220 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3221 SET_PSW_F1 (PSW_F0);
3222 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3223 trace_output_flag ();
3230 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3232 trace_output_void ();
3240 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3241 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3242 SET_GPR (OP[0], tmp);
3243 trace_output_16 (tmp);
3251 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3252 tmp = (GPR (OP[1]) ^ OP[2]);
3253 SET_GPR (OP[0], tmp);
3254 trace_output_16 (tmp);