13 #include "targ-vals.h"
15 extern char *strrchr ();
48 PSW_MASK = (PSW_SM_BIT
59 /* The following bits in the PSW _can't_ be set by instructions such
61 PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
65 move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
67 /* A MASK bit is set when the corresponding bit in the CR should
69 /* This assumes that (VAL & MASK) == 0 */
77 if ((mask & PSW_SM_BIT) == 0)
79 int new_psw_sm = (val & PSW_SM_BIT) != 0;
81 SET_HELD_SP (PSW_SM, GPR (SP_IDX));
82 if (PSW_SM != new_psw_sm)
84 SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
86 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
88 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
90 (*d10v_callback->printf_filtered)
92 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
94 State.exception = SIGILL;
97 /* keep an up-to-date psw around for tracing */
98 State.trace.psw = (State.trace.psw & mask) | val;
102 /* Just like PSW, mask things like DM out. */
115 /* only issue an update if the register is being changed */
116 if ((State.cregs[cr] & ~mask) != val)
117 SLOT_PEND_MASK (State.cregs[cr], mask, val);
122 static void trace_input_func PARAMS ((char *name,
127 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
129 #ifndef SIZE_INSTRUCTION
130 #define SIZE_INSTRUCTION 8
133 #ifndef SIZE_OPERANDS
134 #define SIZE_OPERANDS 18
138 #define SIZE_VALUES 13
141 #ifndef SIZE_LOCATION
142 #define SIZE_LOCATION 20
149 #ifndef SIZE_LINE_NUMBER
150 #define SIZE_LINE_NUMBER 4
154 trace_input_func (name, in1, in2, in3)
167 const char *filename;
168 const char *functionname;
169 unsigned int linenumber;
172 if ((d10v_debug & DEBUG_TRACE) == 0)
175 switch (State.ins_type)
178 case INS_UNKNOWN: type = " ?"; break;
179 case INS_LEFT: type = " L"; break;
180 case INS_RIGHT: type = " R"; break;
181 case INS_LEFT_PARALLEL: type = "*L"; break;
182 case INS_RIGHT_PARALLEL: type = "*R"; break;
183 case INS_LEFT_COND_TEST: type = "?L"; break;
184 case INS_RIGHT_COND_TEST: type = "?R"; break;
185 case INS_LEFT_COND_EXE: type = "&L"; break;
186 case INS_RIGHT_COND_EXE: type = "&R"; break;
187 case INS_LONG: type = " B"; break;
190 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
191 (*d10v_callback->printf_filtered) (d10v_callback,
193 SIZE_PC, (unsigned)PC,
195 SIZE_INSTRUCTION, name);
200 byte_pc = decode_pc ();
201 if (text && byte_pc >= text_start && byte_pc < text_end)
203 filename = (const char *)0;
204 functionname = (const char *)0;
206 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
207 &filename, &functionname, &linenumber))
212 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
217 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
218 p += SIZE_LINE_NUMBER+2;
223 sprintf (p, "%s ", functionname);
228 char *q = strrchr (filename, '/');
229 sprintf (p, "%s ", (q) ? q+1 : filename);
238 (*d10v_callback->printf_filtered) (d10v_callback,
239 "0x%.*x %s: %-*.*s %-*s ",
240 SIZE_PC, (unsigned)PC,
242 SIZE_LOCATION, SIZE_LOCATION, buf,
243 SIZE_INSTRUCTION, name);
251 for (i = 0; i < 3; i++)
265 sprintf (p, "%sr%d", comma, OP[i]);
273 sprintf (p, "%scr%d", comma, OP[i]);
279 case OP_ACCUM_OUTPUT:
280 case OP_ACCUM_REVERSE:
281 sprintf (p, "%sa%d", comma, OP[i]);
287 sprintf (p, "%s%d", comma, OP[i]);
293 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
299 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
305 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
311 sprintf (p, "%s@r%d", comma, OP[i]);
317 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
323 sprintf (p, "%s@%d", comma, OP[i]);
329 sprintf (p, "%s@r%d+", comma, OP[i]);
335 sprintf (p, "%s@r%d-", comma, OP[i]);
341 sprintf (p, "%s@-r%d", comma, OP[i]);
349 sprintf (p, "%sf0", comma);
352 sprintf (p, "%sf1", comma);
355 sprintf (p, "%sc", comma);
363 if ((d10v_debug & DEBUG_VALUES) == 0)
367 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
372 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
375 for (i = 0; i < 3; i++)
381 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
387 case OP_ACCUM_OUTPUT:
389 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
397 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
398 (uint16) GPR (OP[i]));
402 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
406 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
407 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
412 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
413 (uint16) CREG (OP[i]));
417 case OP_ACCUM_REVERSE:
418 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
419 ((int)(ACC (OP[i]) >> 32) & 0xff),
420 ((unsigned long) ACC (OP[i])) & 0xffffffff);
424 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
429 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
430 (uint16)SEXT4(OP[i]));
434 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
435 (uint16)SEXT8(OP[i]));
439 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
440 (uint16)SEXT3(OP[i]));
445 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
449 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
453 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
459 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
461 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
462 (uint16)GPR (OP[i + 1]));
467 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
472 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
477 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
485 (*d10v_callback->flush_stdout) (d10v_callback);
489 do_trace_output_flush (void)
491 (*d10v_callback->flush_stdout) (d10v_callback);
495 do_trace_output_finish (void)
497 (*d10v_callback->printf_filtered) (d10v_callback,
498 " F0=%d F1=%d C=%d\n",
499 (State.trace.psw & PSW_F0_BIT) != 0,
500 (State.trace.psw & PSW_F1_BIT) != 0,
501 (State.trace.psw & PSW_C_BIT) != 0);
502 (*d10v_callback->flush_stdout) (d10v_callback);
506 trace_output_40 (uint64 val)
508 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
510 (*d10v_callback->printf_filtered) (d10v_callback,
511 " :: %*s0x%.2x%.8lx",
514 ((int)(val >> 32) & 0xff),
515 ((unsigned long) val) & 0xffffffff);
516 do_trace_output_finish ();
521 trace_output_32 (uint32 val)
523 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
525 (*d10v_callback->printf_filtered) (d10v_callback,
530 do_trace_output_finish ();
535 trace_output_16 (uint16 val)
537 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
539 (*d10v_callback->printf_filtered) (d10v_callback,
544 do_trace_output_finish ();
551 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
553 (*d10v_callback->printf_filtered) (d10v_callback, "\n");
554 do_trace_output_flush ();
561 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
563 (*d10v_callback->printf_filtered) (d10v_callback,
567 do_trace_output_finish ();
575 #define trace_input(NAME, IN1, IN2, IN3)
576 #define trace_output(RESULT)
584 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
594 SET_GPR (OP[0], tmp);
595 trace_output_16 (tmp);
603 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
606 tmp = SEXT40 (ACC (OP[0]));
612 if (tmp > SEXT40(MAX32))
614 else if (tmp < SEXT40(MIN32))
617 tmp = (tmp & MASK40);
620 tmp = (tmp & MASK40);
625 tmp = (tmp & MASK40);
628 SET_ACC (OP[0], tmp);
629 trace_output_40 (tmp);
636 uint16 a = GPR (OP[0]);
637 uint16 b = GPR (OP[1]);
638 uint16 tmp = (a + b);
639 trace_input ("add", OP_REG, OP_REG, OP_VOID);
641 SET_GPR (OP[0], tmp);
642 trace_output_16 (tmp);
650 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
652 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
655 if (tmp > SEXT40(MAX32))
657 else if (tmp < SEXT40(MIN32))
660 tmp = (tmp & MASK40);
663 tmp = (tmp & MASK40);
664 SET_ACC (OP[0], tmp);
665 trace_output_40 (tmp);
673 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
675 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
678 if (tmp > SEXT40(MAX32))
680 else if (tmp < SEXT40(MIN32))
683 tmp = (tmp & MASK40);
686 tmp = (tmp & MASK40);
687 SET_ACC (OP[0], tmp);
688 trace_output_40 (tmp);
696 uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
697 uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
698 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
701 SET_GPR (OP[0] + 0, (tmp >> 16));
702 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
703 trace_output_32 (tmp);
710 uint16 a = GPR (OP[1]);
712 uint16 tmp = (a + b);
713 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
715 SET_GPR (OP[0], tmp);
716 trace_output_16 (tmp);
724 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
726 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
727 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
728 SET_GPR (OP[0] + 1, (tmp & 0xffff));
729 trace_output_32 (tmp);
737 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
739 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
740 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
741 SET_GPR (OP[0] + 1, tmp & 0xffff);
742 trace_output_32 (tmp);
752 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
753 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
754 if (tmp > SEXT40(MAX32))
759 else if (tmp < SEXT40(MIN32))
768 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
769 SET_GPR (OP[0] + 1, (tmp & 0xffff));
770 trace_output_32 (tmp);
780 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
781 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
782 if (tmp > SEXT40(MAX32))
787 else if (tmp < SEXT40(MIN32))
796 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
797 SET_GPR (OP[0] + 1, (tmp & 0xffff));
798 trace_output_32 (tmp);
805 uint16 a = GPR (OP[0]);
812 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
814 SET_GPR (OP[0], tmp);
815 trace_output_16 (tmp);
822 uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
823 trace_input ("and", OP_REG, OP_REG, OP_VOID);
824 SET_GPR (OP[0], tmp);
825 trace_output_16 (tmp);
832 uint16 tmp = GPR (OP[1]) & OP[2];
833 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
834 SET_GPR (OP[0], tmp);
835 trace_output_16 (tmp);
843 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
844 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
845 SET_GPR (OP[0], tmp);
846 trace_output_16 (tmp);
853 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
854 SET_GPR (13, PC + 1);
855 JMP( PC + SEXT8 (OP[0]));
856 trace_output_void ();
863 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
864 SET_GPR (13, (PC + 1));
866 trace_output_void ();
874 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
875 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
876 SET_GPR (OP[0], tmp);
877 trace_output_16 (tmp);
884 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
885 JMP (PC + SEXT8 (OP[0]));
886 trace_output_void ();
893 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
895 trace_output_void ();
902 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
904 JMP (PC + SEXT8 (OP[0]));
905 trace_output_flag ();
912 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
915 trace_output_flag ();
922 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
924 JMP (PC + SEXT8 (OP[0]));
925 trace_output_flag ();
932 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
935 trace_output_flag ();
943 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
944 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
945 SET_GPR (OP[0], tmp);
946 trace_output_16 (tmp);
953 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
955 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
956 trace_output_flag ();
963 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
972 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
974 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
975 trace_output_flag ();
982 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
984 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
985 trace_output_flag ();
992 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
994 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
995 trace_output_flag ();
1002 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
1003 SET_PSW_F1 (PSW_F0);
1004 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
1005 trace_output_flag ();
1012 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1013 SET_PSW_F1 (PSW_F0);
1014 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1015 trace_output_flag ();
1022 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1023 SET_PSW_F1 (PSW_F0);
1024 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1025 trace_output_flag ();
1032 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1033 SET_PSW_F1 (PSW_F0);
1034 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1035 trace_output_flag ();
1042 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1043 SET_PSW_F1 (PSW_F0);
1044 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1045 trace_output_flag ();
1052 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1053 SET_PSW_F1 (PSW_F0);
1054 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1055 trace_output_flag ();
1062 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1063 SET_PSW_F1 (PSW_F0);
1064 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1065 trace_output_flag ();
1074 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1078 else if (OP[1] == 1)
1087 trace_output_flag ();
1094 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1096 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1097 The conditional below is for either of the instruction pairs
1098 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1099 where the dbt instruction should be interpreted.
1101 The module `sim-break' provides a more effective mechanism for
1102 detecting GDB planted breakpoints. The code below may,
1103 eventually, be changed to use that mechanism. */
1105 if (State.ins_type == INS_LEFT
1106 || State.ins_type == INS_RIGHT)
1108 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1111 SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1112 JMP (DBT_VECTOR_START);
1113 trace_output_void ();
1117 State.exception = SIGTRAP;
1125 uint16 foo, tmp, tmpf;
1129 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1130 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1131 tmp = (int16)foo - (int16)(GPR (OP[1]));
1132 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1133 hi = ((tmpf == 1) ? tmp : foo);
1134 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1135 SET_GPR (OP[0] + 0, hi);
1136 SET_GPR (OP[0] + 1, lo);
1137 trace_output_32 (((uint32) hi << 16) | lo);
1144 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1145 State.exe = (PSW_F0 == 0);
1146 trace_output_flag ();
1153 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1154 State.exe = (PSW_F0 != 0);
1155 trace_output_flag ();
1162 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1163 State.exe = (PSW_F1 == 0);
1164 trace_output_flag ();
1171 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1172 State.exe = (PSW_F1 != 0);
1173 trace_output_flag ();
1180 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1181 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1182 trace_output_flag ();
1189 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1190 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1191 trace_output_flag ();
1198 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1199 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1200 trace_output_flag ();
1207 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1208 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1209 trace_output_flag ();
1219 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1220 if (((int16)GPR (OP[1])) >= 0)
1221 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1223 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1230 SET_GPR (OP[0], (i - 1));
1231 trace_output_16 (i - 1);
1236 SET_GPR (OP[0], 16);
1237 trace_output_16 (16);
1247 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1248 tmp = SEXT40(ACC (OP[1]));
1250 tmp = ~tmp & MASK40;
1252 foo = 0x4000000000LL;
1257 SET_GPR (OP[0], i - 9);
1258 trace_output_16 (i - 9);
1263 SET_GPR (OP[0], 16);
1264 trace_output_16 (16);
1271 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1272 SET_GPR (13, PC + 1);
1274 trace_output_void ();
1281 trace_input ("jmp", OP_REG,
1282 (OP[0] == 13) ? OP_R0 : OP_VOID,
1283 (OP[0] == 13) ? OP_R1 : OP_VOID);
1286 trace_output_void ();
1294 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1295 tmp = RW (OP[1] + GPR (OP[2]));
1296 SET_GPR (OP[0], tmp);
1297 trace_output_16 (tmp);
1305 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1306 tmp = RW (GPR (OP[1]));
1307 SET_GPR (OP[0], tmp);
1309 INC_ADDR (OP[1], -2);
1310 trace_output_16 (tmp);
1318 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1319 tmp = RW (GPR (OP[1]));
1320 SET_GPR (OP[0], tmp);
1322 INC_ADDR (OP[1], 2);
1323 trace_output_16 (tmp);
1331 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1332 tmp = RW (GPR (OP[1]));
1333 SET_GPR (OP[0], tmp);
1334 trace_output_16 (tmp);
1343 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1345 SET_GPR (OP[0], tmp);
1346 trace_output_16 (tmp);
1354 uint16 addr = GPR (OP[2]);
1355 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1356 tmp = RLW (OP[1] + addr);
1357 SET_GPR32 (OP[0], tmp);
1358 trace_output_32 (tmp);
1365 uint16 addr = GPR (OP[1]);
1367 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1369 SET_GPR32 (OP[0], tmp);
1370 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1371 INC_ADDR (OP[1], -4);
1372 trace_output_32 (tmp);
1380 uint16 addr = GPR (OP[1]);
1381 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1383 SET_GPR32 (OP[0], tmp);
1384 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1385 INC_ADDR (OP[1], 4);
1386 trace_output_32 (tmp);
1393 uint16 addr = GPR (OP[1]);
1395 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1396 tmp = RLW (addr + 0);
1397 SET_GPR32 (OP[0], tmp);
1398 trace_output_32 (tmp);
1407 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1409 SET_GPR32 (OP[0], tmp);
1410 trace_output_32 (tmp);
1418 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1419 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1420 SET_GPR (OP[0], tmp);
1421 trace_output_16 (tmp);
1429 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1430 tmp = SEXT8 (RB (GPR (OP[1])));
1431 SET_GPR (OP[0], tmp);
1432 trace_output_16 (tmp);
1440 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1441 tmp = SEXT4 (OP[1]);
1442 SET_GPR (OP[0], tmp);
1443 trace_output_16 (tmp);
1451 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1453 SET_GPR (OP[0], tmp);
1454 trace_output_16 (tmp);
1462 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1463 tmp = RB (OP[1] + GPR (OP[2]));
1464 SET_GPR (OP[0], tmp);
1465 trace_output_16 (tmp);
1473 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1474 tmp = RB (GPR (OP[1]));
1475 SET_GPR (OP[0], tmp);
1476 trace_output_16 (tmp);
1485 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1486 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1489 tmp = SEXT40( (tmp << 1) & MASK40);
1491 if (PSW_ST && tmp > SEXT40(MAX32))
1494 tmp += SEXT40 (ACC (OP[0]));
1497 if (tmp > SEXT40(MAX32))
1499 else if (tmp < SEXT40(MIN32))
1502 tmp = (tmp & MASK40);
1505 tmp = (tmp & MASK40);
1506 SET_ACC (OP[0], tmp);
1507 trace_output_40 (tmp);
1516 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1517 tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1519 tmp = SEXT40 ((tmp << 1) & MASK40);
1520 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1521 SET_ACC (OP[0], tmp);
1522 trace_output_40 (tmp);
1533 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1534 src1 = (uint16) GPR (OP[1]);
1535 src2 = (uint16) GPR (OP[2]);
1539 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1540 SET_ACC (OP[0], tmp);
1541 trace_output_40 (tmp);
1549 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1550 SET_PSW_F1 (PSW_F0);
1551 if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1561 SET_GPR (OP[0], tmp);
1562 trace_output_16 (tmp);
1571 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1572 SET_PSW_F1 (PSW_F0);
1573 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1574 if (tmp > SEXT40 (ACC (OP[0])))
1576 tmp = (tmp & MASK40);
1584 SET_ACC (OP[0], tmp);
1585 trace_output_40 (tmp);
1593 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1594 SET_PSW_F1 (PSW_F0);
1595 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1605 SET_ACC (OP[0], tmp);
1606 trace_output_40 (tmp);
1615 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1616 SET_PSW_F1 (PSW_F0);
1617 if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1627 SET_GPR (OP[0], tmp);
1628 trace_output_16 (tmp);
1637 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1638 SET_PSW_F1 (PSW_F0);
1639 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1640 if (tmp < SEXT40(ACC (OP[0])))
1642 tmp = (tmp & MASK40);
1650 SET_ACC (OP[0], tmp);
1651 trace_output_40 (tmp);
1659 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1660 SET_PSW_F1 (PSW_F0);
1661 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1671 SET_ACC (OP[0], tmp);
1672 trace_output_40 (tmp);
1681 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1682 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1685 tmp = SEXT40 ((tmp << 1) & MASK40);
1687 if (PSW_ST && tmp > SEXT40(MAX32))
1690 tmp = SEXT40(ACC (OP[0])) - tmp;
1693 if (tmp > SEXT40(MAX32))
1695 else if (tmp < SEXT40(MIN32))
1698 tmp = (tmp & MASK40);
1702 tmp = (tmp & MASK40);
1704 SET_ACC (OP[0], tmp);
1705 trace_output_40 (tmp);
1714 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1715 tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1717 tmp = SEXT40( (tmp << 1) & MASK40);
1718 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1719 SET_ACC (OP[0], tmp);
1720 trace_output_40 (tmp);
1731 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1732 src1 = (uint16) GPR (OP[1]);
1733 src2 = (uint16) GPR (OP[2]);
1737 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1738 SET_ACC (OP[0], tmp);
1739 trace_output_40 (tmp);
1747 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1748 tmp = GPR (OP[0]) * GPR (OP[1]);
1749 SET_GPR (OP[0], tmp);
1750 trace_output_16 (tmp);
1759 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1760 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1763 tmp = SEXT40 ((tmp << 1) & MASK40);
1765 if (PSW_ST && tmp > SEXT40(MAX32))
1768 tmp = (tmp & MASK40);
1769 SET_ACC (OP[0], tmp);
1770 trace_output_40 (tmp);
1779 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1780 tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1784 tmp = (tmp & MASK40);
1785 SET_ACC (OP[0], tmp);
1786 trace_output_40 (tmp);
1797 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1798 src1 = (uint16) GPR (OP[1]);
1799 src2 = (uint16) GPR (OP[2]);
1803 tmp = (tmp & MASK40);
1804 SET_ACC (OP[0], tmp);
1805 trace_output_40 (tmp);
1813 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1815 SET_GPR (OP[0], tmp);
1816 trace_output_16 (tmp);
1824 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1825 tmp = GPR32 (OP[1]);
1826 SET_GPR32 (OP[0], tmp);
1827 trace_output_32 (tmp);
1835 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1837 SET_GPR32 (OP[0], tmp);
1838 trace_output_32 (tmp);
1846 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1847 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1848 SET_ACC (OP[1], tmp);
1849 trace_output_40 (tmp);
1857 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1859 SET_ACC (OP[0], tmp);
1860 trace_output_40 (tmp);
1868 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1869 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1870 SET_GPR (OP[0], tmp);
1871 trace_output_16 (tmp);
1879 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1883 SET_GPR (OP[0], tmp);
1887 trace_output_16 (tmp);
1895 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1899 SET_GPR (OP[0], tmp);
1903 trace_output_16 (tmp);
1911 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1912 tmp = ((ACC (OP[1]) >> 32) & 0xff);
1913 SET_GPR (OP[0], tmp);
1914 trace_output_16 (tmp);
1922 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1923 tmp = (ACC (OP[1]) >> 16);
1924 SET_GPR (OP[0], tmp);
1925 trace_output_16 (tmp);
1933 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1935 SET_GPR (OP[0], tmp);
1936 trace_output_16 (tmp);
1944 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1946 SET_GPR (OP[0], tmp);
1947 trace_output_16 (tmp);
1955 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1956 tmp = ((ACC (OP[1]) & MASK32)
1957 | ((int64)(GPR (OP[0]) & 0xff) << 32));
1958 SET_ACC (OP[1], tmp);
1959 trace_output_40 (tmp);
1967 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1968 tmp = ACC (OP[1]) & 0xffff;
1969 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
1970 SET_ACC (OP[1], tmp);
1971 trace_output_40 (tmp);
1979 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
1980 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
1981 SET_ACC (OP[1], tmp);
1982 trace_output_40 (tmp);
1990 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
1992 tmp = SET_CREG (OP[1], tmp);
1993 trace_output_16 (tmp);
2001 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2002 tmp = (GPR (OP[1]) & 0xff);
2003 SET_GPR (OP[0], tmp);
2004 trace_output_16 (tmp);
2012 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2013 tmp = - GPR (OP[0]);
2014 SET_GPR (OP[0], tmp);
2015 trace_output_16 (tmp);
2024 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2025 tmp = -SEXT40(ACC (OP[0]));
2028 if (tmp > SEXT40(MAX32))
2030 else if (tmp < SEXT40(MIN32))
2033 tmp = (tmp & MASK40);
2036 tmp = (tmp & MASK40);
2037 SET_ACC (OP[0], tmp);
2038 trace_output_40 (tmp);
2046 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2048 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2049 switch (State.ins_type)
2052 ins_type_counters[ (int)INS_UNKNOWN ]++;
2055 case INS_LEFT_PARALLEL:
2056 /* Don't count a parallel op that includes a NOP as a true parallel op */
2057 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2058 ins_type_counters[ (int)INS_RIGHT ]++;
2059 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2063 case INS_LEFT_COND_EXE:
2064 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2067 case INS_RIGHT_PARALLEL:
2068 /* Don't count a parallel op that includes a NOP as a true parallel op */
2069 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2070 ins_type_counters[ (int)INS_LEFT ]++;
2071 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2075 case INS_RIGHT_COND_EXE:
2076 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2080 trace_output_void ();
2088 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2090 SET_GPR (OP[0], tmp);
2091 trace_output_16 (tmp);
2099 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2100 tmp = (GPR (OP[0]) | GPR (OP[1]));
2101 SET_GPR (OP[0], tmp);
2102 trace_output_16 (tmp);
2110 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2111 tmp = (GPR (OP[1]) | OP[2]);
2112 SET_GPR (OP[0], tmp);
2113 trace_output_16 (tmp);
2121 int shift = SEXT3 (OP[2]);
2123 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2126 (*d10v_callback->printf_filtered) (d10v_callback,
2127 "ERROR at PC 0x%x: instruction only valid for A0\n",
2129 State.exception = SIGILL;
2132 SET_PSW_F1 (PSW_F0);
2133 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2139 tmp >>= 16; /* look at bits 0:43 */
2140 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2145 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2154 SET_GPR32 (OP[0], tmp);
2155 trace_output_32 (tmp);
2163 int shift = SEXT3 (OP[2]);
2165 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2166 SET_PSW_F1 (PSW_F0);
2168 tmp = SEXT40 (ACC (OP[1])) << shift;
2170 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2173 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2178 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2188 SET_GPR (OP[0], tmp);
2189 trace_output_16 (tmp);
2196 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2198 SET_RPT_E (PC + OP[1]);
2199 SET_RPT_C (GPR (OP[0]));
2201 if (GPR (OP[0]) == 0)
2203 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2204 State.exception = SIGILL;
2208 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2209 State.exception = SIGILL;
2211 trace_output_void ();
2218 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2220 SET_RPT_E (PC + OP[1]);
2225 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2226 State.exception = SIGILL;
2230 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2231 State.exception = SIGILL;
2233 trace_output_void ();
2240 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2241 SET_CREG (PSW_CR, DPSW);
2243 trace_output_void ();
2250 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2251 SET_CREG (PSW_CR, BPSW);
2253 trace_output_void ();
2261 trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2263 tmp = SEXT40(ACC (OP[1]));
2265 SET_PSW_F1 (PSW_F0);
2267 if (tmp > SEXT40(MAX32))
2272 else if (tmp < SEXT40(MIN32))
2279 tmp = (tmp & MASK32);
2283 SET_GPR32 (OP[0], tmp);
2285 trace_output_40 (tmp);
2294 trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2296 tmp = SEXT40(ACC (OP[1]));
2298 SET_PSW_F1 (PSW_F0);
2300 if (tmp > SEXT40(MAX32))
2305 else if (tmp < SEXT40(MIN32))
2316 SET_GPR (OP[0], tmp);
2318 trace_output_16 (OP[0]);
2327 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2328 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2331 if (tmp > SEXT40(MAX32))
2333 else if (tmp < SEXT40(MIN32))
2336 tmp = (tmp & MASK40);
2339 tmp = (tmp & MASK40);
2340 SET_ACC (OP[0], tmp);
2341 trace_output_40 (tmp);
2349 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2350 tmp = ((PSW_F0 == 0) ? 1 : 0);
2351 SET_GPR (OP[0], tmp);
2352 trace_output_16 (tmp);
2360 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2361 tmp = ((PSW_F0 == 1) ? 1 : 0);
2362 SET_GPR (OP[0], tmp);
2363 trace_output_16 (tmp);
2373 trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2375 reg = SEXT16 (GPR (OP[1]));
2377 if (reg >= 17 || reg <= -17)
2379 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
2380 State.exception = SIGILL;
2384 tmp = SEXT40 (ACC (OP[0]));
2386 if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2388 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
2389 State.exception = SIGILL;
2393 if (reg >= 0 && reg <= 16)
2395 tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2398 if (tmp > SEXT40(MAX32))
2400 else if (tmp < SEXT40(MIN32))
2403 tmp = (tmp & MASK40);
2406 tmp = (tmp & MASK40);
2410 tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2413 SET_ACC(OP[0], tmp);
2415 trace_output_40(tmp);
2422 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2424 trace_output_void ();
2432 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2433 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2434 SET_GPR (OP[0], tmp);
2435 trace_output_16 (tmp);
2443 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2444 if ((GPR (OP[1]) & 31) <= 16)
2445 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2448 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2449 State.exception = SIGILL;
2455 if (tmp > SEXT40(MAX32))
2457 else if (tmp < SEXT40(MIN32))
2460 tmp = (tmp & MASK40);
2463 tmp = (tmp & MASK40);
2464 SET_ACC (OP[0], tmp);
2465 trace_output_40 (tmp);
2473 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2474 tmp = (GPR (OP[0]) << OP[1]);
2475 SET_GPR (OP[0], tmp);
2476 trace_output_16 (tmp);
2488 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2489 tmp = SEXT40(ACC (OP[0])) << OP[1];
2493 if (tmp > SEXT40(MAX32))
2495 else if (tmp < SEXT40(MIN32))
2498 tmp = (tmp & MASK40);
2501 tmp = (tmp & MASK40);
2502 SET_ACC (OP[0], tmp);
2503 trace_output_40 (tmp);
2511 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2512 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2513 SET_GPR (OP[0], tmp);
2514 trace_output_16 (tmp);
2522 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2523 tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2524 SET_GPR (OP[0], tmp);
2525 trace_output_16 (tmp);
2532 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2533 if ((GPR (OP[1]) & 31) <= 16)
2535 int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2536 SET_ACC (OP[0], tmp);
2537 trace_output_40 (tmp);
2541 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2542 State.exception = SIGILL;
2552 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2553 tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2554 SET_GPR (OP[0], tmp);
2555 trace_output_16 (tmp);
2566 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2567 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2568 SET_ACC (OP[0], tmp);
2569 trace_output_40 (tmp);
2577 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2578 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2579 SET_GPR (OP[0], tmp);
2580 trace_output_16 (tmp);
2587 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2588 if ((GPR (OP[1]) & 31) <= 16)
2590 int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2591 SET_ACC (OP[0], tmp);
2592 trace_output_40 (tmp);
2596 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2597 State.exception = SIGILL;
2608 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2609 tmp = (GPR (OP[0]) >> OP[1]);
2610 SET_GPR (OP[0], tmp);
2611 trace_output_16 (tmp);
2622 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2623 tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2624 SET_ACC (OP[0], tmp);
2625 trace_output_40 (tmp);
2633 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2635 tmp = ((GPR (OP[0]) >> 1) | tmp);
2636 SET_GPR (OP[0], tmp);
2637 trace_output_16 (tmp);
2644 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2645 SW (OP[1] + GPR (OP[2]), GPR (OP[0]));
2646 trace_output_void ();
2653 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2654 SW (GPR (OP[1]), GPR (OP[0]));
2655 trace_output_void ();
2662 uint16 addr = GPR (OP[1]) - 2;
2663 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2666 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2667 State.exception = SIGILL;
2670 SW (addr, GPR (OP[0]));
2671 SET_GPR (OP[1], addr);
2672 trace_output_void ();
2679 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2680 SW (GPR (OP[1]), GPR (OP[0]));
2681 INC_ADDR (OP[1], 2);
2682 trace_output_void ();
2689 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2692 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2693 State.exception = SIGILL;
2696 SW (GPR (OP[1]), GPR (OP[0]));
2697 INC_ADDR (OP[1], -2);
2698 trace_output_void ();
2705 trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2706 SW (OP[1], GPR (OP[0]));
2707 trace_output_void ();
2714 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2715 SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0));
2716 SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1));
2717 trace_output_void ();
2724 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2725 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2726 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2727 trace_output_void ();
2734 uint16 addr = GPR (OP[1]) - 4;
2735 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2738 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2739 State.exception = SIGILL;
2742 SW (addr + 0, GPR (OP[0] + 0));
2743 SW (addr + 2, GPR (OP[0] + 1));
2744 SET_GPR (OP[1], addr);
2745 trace_output_void ();
2752 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2753 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2754 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2755 INC_ADDR (OP[1], 4);
2756 trace_output_void ();
2763 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2766 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2767 State.exception = SIGILL;
2770 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2771 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2772 INC_ADDR (OP[1], -4);
2773 trace_output_void ();
2780 trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2781 SW (OP [1] + 0, GPR (OP[0] + 0));
2782 SW (OP [1] + 2, GPR (OP[0] + 1));
2783 trace_output_void ();
2790 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2791 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2792 trace_output_void ();
2799 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2800 SB (GPR (OP[1]), GPR (OP[0]));
2801 trace_output_void ();
2808 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2809 State.exception = SIG_D10V_STOP;
2810 trace_output_void ();
2817 uint16 a = GPR (OP[0]);
2818 uint16 b = GPR (OP[1]);
2819 uint16 tmp = (a - b);
2820 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2821 /* see ../common/sim-alu.h for a more extensive discussion on how to
2822 compute the carry/overflow bits. */
2824 SET_GPR (OP[0], tmp);
2825 trace_output_16 (tmp);
2834 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2835 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
2838 if (tmp > SEXT40(MAX32))
2840 else if (tmp < SEXT40(MIN32))
2843 tmp = (tmp & MASK40);
2846 tmp = (tmp & MASK40);
2847 SET_ACC (OP[0], tmp);
2849 trace_output_40 (tmp);
2859 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2860 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
2863 if (tmp > SEXT40(MAX32))
2865 else if (tmp < SEXT40(MIN32))
2868 tmp = (tmp & MASK40);
2871 tmp = (tmp & MASK40);
2872 SET_ACC (OP[0], tmp);
2874 trace_output_40 (tmp);
2883 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2884 a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
2885 b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
2886 /* see ../common/sim-alu.h for a more extensive discussion on how to
2887 compute the carry/overflow bits */
2890 SET_GPR32 (OP[0], tmp);
2891 trace_output_32 (tmp);
2900 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2901 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
2902 SET_GPR32 (OP[0], tmp);
2903 trace_output_32 (tmp);
2912 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2913 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
2914 SET_GPR32 (OP[0], tmp);
2915 trace_output_32 (tmp);
2924 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2925 SET_PSW_F1 (PSW_F0);
2926 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
2927 if (tmp > SEXT40(MAX32))
2932 else if (tmp < SEXT40(MIN32))
2941 SET_GPR32 (OP[0], tmp);
2942 trace_output_32 (tmp);
2951 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2952 SET_PSW_F1 (PSW_F0);
2953 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
2954 if (tmp > SEXT40(MAX32))
2959 else if (tmp < SEXT40(MIN32))
2968 SET_GPR32 (OP[0], tmp);
2969 trace_output_32 (tmp);
2980 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
2981 /* see ../common/sim-alu.h for a more extensive discussion on how to
2982 compute the carry/overflow bits. */
2983 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
2984 tmp = ((unsigned)(unsigned16) GPR (OP[0])
2985 + (unsigned)(unsigned16) ( - OP[1]));
2986 SET_PSW_C (tmp >= (1 << 16));
2987 SET_GPR (OP[0], tmp);
2988 trace_output_16 (tmp);
2995 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
2996 trace_output_void ();
3001 #if (DEBUG & DEBUG_TRAP) == 0
3003 uint16 vec = OP[0] + TRAP_VECTOR_START;
3006 SET_PSW (PSW & PSW_SM_BIT);
3010 #else /* if debugging use trap to print registers */
3013 static int first_time = 1;
3018 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
3019 for (i = 0; i < 16; i++)
3020 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
3021 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
3024 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3026 for (i = 0; i < 16; i++)
3027 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
3029 for (i = 0; i < 2; i++)
3030 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
3031 ((int)(ACC (i) >> 32) & 0xff),
3032 ((unsigned long) ACC (i)) & 0xffffffff);
3034 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
3035 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3036 (*d10v_callback->flush_stdout) (d10v_callback);
3040 case 15: /* new system call trap */
3041 /* Trap 15 is used for simulating low-level I/O */
3043 unsigned32 result = 0;
3046 /* Registers passed to trap 0 */
3048 #define FUNC GPR (4) /* function number */
3049 #define PARM1 GPR (0) /* optional parm 1 */
3050 #define PARM2 GPR (1) /* optional parm 2 */
3051 #define PARM3 GPR (2) /* optional parm 3 */
3052 #define PARM4 GPR (3) /* optional parm 3 */
3054 /* Registers set by trap 0 */
3056 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3057 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3058 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3060 /* Turn a pointer in a register into a pointer into real memory. */
3062 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3066 #if !defined(__GO32__) && !defined(_WIN32)
3067 case TARGET_SYS_fork:
3068 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3070 trace_output_16 (result);
3074 case TARGET_SYS_getpid:
3075 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3077 trace_output_16 (result);
3080 case TARGET_SYS_kill:
3081 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3082 if (PARM1 == getpid ())
3084 trace_output_void ();
3085 State.exception = PARM2;
3093 case 1: os_sig = SIGHUP; break;
3096 case 2: os_sig = SIGINT; break;
3099 case 3: os_sig = SIGQUIT; break;
3102 case 4: os_sig = SIGILL; break;
3105 case 5: os_sig = SIGTRAP; break;
3108 case 6: os_sig = SIGABRT; break;
3109 #elif defined(SIGIOT)
3110 case 6: os_sig = SIGIOT; break;
3113 case 7: os_sig = SIGEMT; break;
3116 case 8: os_sig = SIGFPE; break;
3119 case 9: os_sig = SIGKILL; break;
3122 case 10: os_sig = SIGBUS; break;
3125 case 11: os_sig = SIGSEGV; break;
3128 case 12: os_sig = SIGSYS; break;
3131 case 13: os_sig = SIGPIPE; break;
3134 case 14: os_sig = SIGALRM; break;
3137 case 15: os_sig = SIGTERM; break;
3140 case 16: os_sig = SIGURG; break;
3143 case 17: os_sig = SIGSTOP; break;
3146 case 18: os_sig = SIGTSTP; break;
3149 case 19: os_sig = SIGCONT; break;
3152 case 20: os_sig = SIGCHLD; break;
3153 #elif defined(SIGCLD)
3154 case 20: os_sig = SIGCLD; break;
3157 case 21: os_sig = SIGTTIN; break;
3160 case 22: os_sig = SIGTTOU; break;
3163 case 23: os_sig = SIGIO; break;
3164 #elif defined (SIGPOLL)
3165 case 23: os_sig = SIGPOLL; break;
3168 case 24: os_sig = SIGXCPU; break;
3171 case 25: os_sig = SIGXFSZ; break;
3174 case 26: os_sig = SIGVTALRM; break;
3177 case 27: os_sig = SIGPROF; break;
3180 case 28: os_sig = SIGWINCH; break;
3183 case 29: os_sig = SIGLOST; break;
3186 case 30: os_sig = SIGUSR1; break;
3189 case 31: os_sig = SIGUSR2; break;
3195 trace_output_void ();
3196 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3197 (*d10v_callback->flush_stdout) (d10v_callback);
3198 State.exception = SIGILL;
3202 RETVAL (kill (PARM1, PARM2));
3203 trace_output_16 (result);
3208 case TARGET_SYS_execve:
3209 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3210 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3211 (char **)MEMPTR (PARM3)));
3212 trace_output_16 (result);
3215 #ifdef TARGET_SYS_execv
3216 case TARGET_SYS_execv:
3217 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3218 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3219 trace_output_16 (result);
3223 case TARGET_SYS_pipe:
3228 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3230 RETVAL (pipe (host_fd));
3231 SW (buf, host_fd[0]);
3232 buf += sizeof(uint16);
3233 SW (buf, host_fd[1]);
3234 trace_output_16 (result);
3239 #ifdef TARGET_SYS_wait
3240 case TARGET_SYS_wait:
3243 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3244 RETVAL (wait (&status));
3247 trace_output_16 (result);
3253 case TARGET_SYS_getpid:
3254 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3256 trace_output_16 (result);
3259 case TARGET_SYS_kill:
3260 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3261 trace_output_void ();
3262 State.exception = PARM2;
3266 case TARGET_SYS_read:
3267 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3268 RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3270 trace_output_16 (result);
3273 case TARGET_SYS_write:
3274 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3276 RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3277 MEMPTR (PARM2), PARM3));
3279 RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3280 MEMPTR (PARM2), PARM3));
3281 trace_output_16 (result);
3284 case TARGET_SYS_lseek:
3285 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3286 RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3287 ((((unsigned long) PARM2) << 16)
3288 || (unsigned long) PARM3),
3290 trace_output_32 (result);
3293 case TARGET_SYS_close:
3294 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3295 RETVAL (d10v_callback->close (d10v_callback, PARM1));
3296 trace_output_16 (result);
3299 case TARGET_SYS_open:
3300 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3301 RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3302 trace_output_16 (result);
3305 case TARGET_SYS_exit:
3306 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3307 State.exception = SIG_D10V_EXIT;
3308 trace_output_void ();
3311 #ifdef TARGET_SYS_stat
3312 case TARGET_SYS_stat:
3313 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3314 /* stat system call */
3316 struct stat host_stat;
3319 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3323 /* The hard-coded offsets and sizes were determined by using
3324 * the D10V compiler on a test program that used struct stat.
3326 SW (buf, host_stat.st_dev);
3327 SW (buf+2, host_stat.st_ino);
3328 SW (buf+4, host_stat.st_mode);
3329 SW (buf+6, host_stat.st_nlink);
3330 SW (buf+8, host_stat.st_uid);
3331 SW (buf+10, host_stat.st_gid);
3332 SW (buf+12, host_stat.st_rdev);
3333 SLW (buf+16, host_stat.st_size);
3334 SLW (buf+20, host_stat.st_atime);
3335 SLW (buf+28, host_stat.st_mtime);
3336 SLW (buf+36, host_stat.st_ctime);
3338 trace_output_16 (result);
3342 case TARGET_SYS_chown:
3343 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3344 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3345 trace_output_16 (result);
3348 case TARGET_SYS_chmod:
3349 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3350 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3351 trace_output_16 (result);
3355 #ifdef TARGET_SYS_utime
3356 case TARGET_SYS_utime:
3357 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3358 /* Cast the second argument to void *, to avoid type mismatch
3359 if a prototype is present. */
3360 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3361 trace_output_16 (result);
3367 #ifdef TARGET_SYS_time
3368 case TARGET_SYS_time:
3369 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3370 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3371 trace_output_32 (result);
3377 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3379 if ((uint16) result == (uint16) -1)
3380 RETERR (d10v_callback->get_errno(d10v_callback));
3392 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3393 SET_PSW_F1 (PSW_F0);;
3394 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3395 trace_output_flag ();
3402 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3403 SET_PSW_F1 (PSW_F0);
3404 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3405 trace_output_flag ();
3412 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3414 trace_output_void ();
3422 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3423 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3424 SET_GPR (OP[0], tmp);
3425 trace_output_16 (tmp);
3433 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3434 tmp = (GPR (OP[1]) ^ OP[2]);
3435 SET_GPR (OP[0], tmp);
3436 trace_output_16 (tmp);