13 #include "targ-vals.h"
15 extern char *strrchr ();
48 PSW_MASK = (PSW_SM_BIT
59 /* The following bits in the PSW _can't_ be set by instructions such
61 PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
65 move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
67 /* A MASK bit is set when the corresponding bit in the CR should
69 /* This assumes that (VAL & MASK) == 0 */
77 if ((mask & PSW_SM_BIT) == 0)
79 int new_psw_sm = (val & PSW_SM_BIT) != 0;
81 SET_HELD_SP (PSW_SM, GPR (SP_IDX));
82 if (PSW_SM != new_psw_sm)
84 SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
86 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
88 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
90 (*d10v_callback->printf_filtered)
92 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
94 State.exception = SIGILL;
97 /* keep an up-to-date psw around for tracing */
98 State.trace.psw = (State.trace.psw & mask) | val;
102 /* Just like PSW, mask things like DM out. */
115 /* only issue an update if the register is being changed */
116 if ((State.cregs[cr] & ~mask) != val)
117 SLOT_PEND_MASK (State.cregs[cr], mask, val);
122 static void trace_input_func PARAMS ((char *name,
127 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
129 #ifndef SIZE_INSTRUCTION
130 #define SIZE_INSTRUCTION 8
133 #ifndef SIZE_OPERANDS
134 #define SIZE_OPERANDS 18
138 #define SIZE_VALUES 13
141 #ifndef SIZE_LOCATION
142 #define SIZE_LOCATION 20
149 #ifndef SIZE_LINE_NUMBER
150 #define SIZE_LINE_NUMBER 4
154 trace_input_func (name, in1, in2, in3)
167 const char *filename;
168 const char *functionname;
169 unsigned int linenumber;
172 if ((d10v_debug & DEBUG_TRACE) == 0)
175 switch (State.ins_type)
178 case INS_UNKNOWN: type = " ?"; break;
179 case INS_LEFT: type = " L"; break;
180 case INS_RIGHT: type = " R"; break;
181 case INS_LEFT_PARALLEL: type = "*L"; break;
182 case INS_RIGHT_PARALLEL: type = "*R"; break;
183 case INS_LEFT_COND_TEST: type = "?L"; break;
184 case INS_RIGHT_COND_TEST: type = "?R"; break;
185 case INS_LEFT_COND_EXE: type = "&L"; break;
186 case INS_RIGHT_COND_EXE: type = "&R"; break;
187 case INS_LONG: type = " B"; break;
190 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
191 (*d10v_callback->printf_filtered) (d10v_callback,
193 SIZE_PC, (unsigned)PC,
195 SIZE_INSTRUCTION, name);
200 byte_pc = decode_pc ();
201 if (text && byte_pc >= text_start && byte_pc < text_end)
203 filename = (const char *)0;
204 functionname = (const char *)0;
206 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
207 &filename, &functionname, &linenumber))
212 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
217 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
218 p += SIZE_LINE_NUMBER+2;
223 sprintf (p, "%s ", functionname);
228 char *q = strrchr (filename, '/');
229 sprintf (p, "%s ", (q) ? q+1 : filename);
238 (*d10v_callback->printf_filtered) (d10v_callback,
239 "0x%.*x %s: %-*.*s %-*s ",
240 SIZE_PC, (unsigned)PC,
242 SIZE_LOCATION, SIZE_LOCATION, buf,
243 SIZE_INSTRUCTION, name);
251 for (i = 0; i < 3; i++)
265 sprintf (p, "%sr%d", comma, OP[i]);
273 sprintf (p, "%scr%d", comma, OP[i]);
279 case OP_ACCUM_OUTPUT:
280 case OP_ACCUM_REVERSE:
281 sprintf (p, "%sa%d", comma, OP[i]);
287 sprintf (p, "%s%d", comma, OP[i]);
293 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
299 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
305 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
311 sprintf (p, "%s@r%d", comma, OP[i]);
317 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
323 sprintf (p, "%s@%d", comma, OP[i]);
329 sprintf (p, "%s@r%d+", comma, OP[i]);
335 sprintf (p, "%s@r%d-", comma, OP[i]);
341 sprintf (p, "%s@-r%d", comma, OP[i]);
349 sprintf (p, "%sf0", comma);
352 sprintf (p, "%sf1", comma);
355 sprintf (p, "%sc", comma);
363 if ((d10v_debug & DEBUG_VALUES) == 0)
367 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
372 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
375 for (i = 0; i < 3; i++)
381 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
387 case OP_ACCUM_OUTPUT:
389 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
397 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
398 (uint16) GPR (OP[i]));
402 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
406 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
407 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
412 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
413 (uint16) CREG (OP[i]));
417 case OP_ACCUM_REVERSE:
418 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
419 ((int)(ACC (OP[i]) >> 32) & 0xff),
420 ((unsigned long) ACC (OP[i])) & 0xffffffff);
424 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
429 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
430 (uint16)SEXT4(OP[i]));
434 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
435 (uint16)SEXT8(OP[i]));
439 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
440 (uint16)SEXT3(OP[i]));
445 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
449 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
453 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
459 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
461 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
462 (uint16)GPR (OP[i + 1]));
467 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
472 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
477 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
485 (*d10v_callback->flush_stdout) (d10v_callback);
489 do_trace_output_flush (void)
491 (*d10v_callback->flush_stdout) (d10v_callback);
495 do_trace_output_finish (void)
497 (*d10v_callback->printf_filtered) (d10v_callback,
498 " F0=%d F1=%d C=%d\n",
499 (State.trace.psw & PSW_F0_BIT) != 0,
500 (State.trace.psw & PSW_F1_BIT) != 0,
501 (State.trace.psw & PSW_C_BIT) != 0);
502 (*d10v_callback->flush_stdout) (d10v_callback);
506 trace_output_40 (uint64 val)
508 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
510 (*d10v_callback->printf_filtered) (d10v_callback,
511 " :: %*s0x%.2x%.8lx",
514 ((int)(val >> 32) & 0xff),
515 ((unsigned long) val) & 0xffffffff);
516 do_trace_output_finish ();
521 trace_output_32 (uint32 val)
523 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
525 (*d10v_callback->printf_filtered) (d10v_callback,
530 do_trace_output_finish ();
535 trace_output_16 (uint16 val)
537 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
539 (*d10v_callback->printf_filtered) (d10v_callback,
544 do_trace_output_finish ();
551 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
553 (*d10v_callback->printf_filtered) (d10v_callback, "\n");
554 do_trace_output_flush ();
561 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
563 (*d10v_callback->printf_filtered) (d10v_callback,
567 do_trace_output_finish ();
575 #define trace_input(NAME, IN1, IN2, IN3)
576 #define trace_output(RESULT)
584 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
594 SET_GPR (OP[0], tmp);
595 trace_output_16 (tmp);
603 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
606 tmp = SEXT40 (ACC (OP[0]));
612 if (tmp > SEXT40(MAX32))
614 else if (tmp < SEXT40(MIN32))
617 tmp = (tmp & MASK40);
620 tmp = (tmp & MASK40);
625 tmp = (tmp & MASK40);
628 SET_ACC (OP[0], tmp);
629 trace_output_40 (tmp);
636 uint16 a = GPR (OP[0]);
637 uint16 b = GPR (OP[1]);
638 uint16 tmp = (a + b);
639 trace_input ("add", OP_REG, OP_REG, OP_VOID);
641 SET_GPR (OP[0], tmp);
642 trace_output_16 (tmp);
650 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
652 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
655 if (tmp > SEXT40(MAX32))
657 else if (tmp < SEXT40(MIN32))
660 tmp = (tmp & MASK40);
663 tmp = (tmp & MASK40);
664 SET_ACC (OP[0], tmp);
665 trace_output_40 (tmp);
673 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
675 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
678 if (tmp > SEXT40(MAX32))
680 else if (tmp < SEXT40(MIN32))
683 tmp = (tmp & MASK40);
686 tmp = (tmp & MASK40);
687 SET_ACC (OP[0], tmp);
688 trace_output_40 (tmp);
696 uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
697 uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
698 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
701 SET_GPR (OP[0] + 0, (tmp >> 16));
702 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
703 trace_output_32 (tmp);
710 uint16 a = GPR (OP[1]);
712 uint16 tmp = (a + b);
713 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
715 SET_GPR (OP[0], tmp);
716 trace_output_16 (tmp);
724 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
726 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
727 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
728 SET_GPR (OP[0] + 1, (tmp & 0xffff));
729 trace_output_32 (tmp);
737 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
739 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
740 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
741 SET_GPR (OP[0] + 1, tmp & 0xffff);
742 trace_output_32 (tmp);
752 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
753 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
754 if (tmp > SEXT40(MAX32))
759 else if (tmp < SEXT40(MIN32))
768 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
769 SET_GPR (OP[0] + 1, (tmp & 0xffff));
770 trace_output_32 (tmp);
780 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
781 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
782 if (tmp > SEXT40(MAX32))
787 else if (tmp < SEXT40(MIN32))
796 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
797 SET_GPR (OP[0] + 1, (tmp & 0xffff));
798 trace_output_32 (tmp);
805 uint16 a = GPR (OP[0]);
812 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
814 SET_GPR (OP[0], tmp);
815 trace_output_16 (tmp);
822 uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
823 trace_input ("and", OP_REG, OP_REG, OP_VOID);
824 SET_GPR (OP[0], tmp);
825 trace_output_16 (tmp);
832 uint16 tmp = GPR (OP[1]) & OP[2];
833 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
834 SET_GPR (OP[0], tmp);
835 trace_output_16 (tmp);
843 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
844 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
845 SET_GPR (OP[0], tmp);
846 trace_output_16 (tmp);
853 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
854 SET_GPR (13, PC + 1);
855 JMP( PC + SEXT8 (OP[0]));
856 trace_output_void ();
863 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
864 SET_GPR (13, (PC + 1));
866 trace_output_void ();
874 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
875 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
876 SET_GPR (OP[0], tmp);
877 trace_output_16 (tmp);
884 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
885 JMP (PC + SEXT8 (OP[0]));
886 trace_output_void ();
893 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
895 trace_output_void ();
902 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
904 JMP (PC + SEXT8 (OP[0]));
905 trace_output_flag ();
912 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
915 trace_output_flag ();
922 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
924 JMP (PC + SEXT8 (OP[0]));
925 trace_output_flag ();
932 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
935 trace_output_flag ();
943 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
944 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
945 SET_GPR (OP[0], tmp);
946 trace_output_16 (tmp);
953 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
955 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
956 trace_output_flag ();
963 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
972 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
974 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
975 trace_output_flag ();
982 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
984 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
985 trace_output_flag ();
992 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
994 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
995 trace_output_flag ();
1002 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
1003 SET_PSW_F1 (PSW_F0);
1004 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
1005 trace_output_flag ();
1012 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1013 SET_PSW_F1 (PSW_F0);
1014 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1015 trace_output_flag ();
1022 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1023 SET_PSW_F1 (PSW_F0);
1024 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1025 trace_output_flag ();
1032 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1033 SET_PSW_F1 (PSW_F0);
1034 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1035 trace_output_flag ();
1042 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1043 SET_PSW_F1 (PSW_F0);
1044 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1045 trace_output_flag ();
1052 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1053 SET_PSW_F1 (PSW_F0);
1054 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1055 trace_output_flag ();
1062 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1063 SET_PSW_F1 (PSW_F0);
1064 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1065 trace_output_flag ();
1074 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1078 else if (OP[1] == 1)
1087 trace_output_flag ();
1096 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1100 else if (OP[1] == 1)
1109 trace_output_flag ();
1116 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1118 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1119 The conditional below is for either of the instruction pairs
1120 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1121 where the dbt instruction should be interpreted.
1123 The module `sim-break' provides a more effective mechanism for
1124 detecting GDB planted breakpoints. The code below may,
1125 eventually, be changed to use that mechanism. */
1127 if (State.ins_type == INS_LEFT
1128 || State.ins_type == INS_RIGHT)
1130 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1133 SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1134 JMP (DBT_VECTOR_START);
1135 trace_output_void ();
1139 State.exception = SIGTRAP;
1147 uint16 foo, tmp, tmpf;
1151 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1152 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1153 tmp = (int16)foo - (int16)(GPR (OP[1]));
1154 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1155 hi = ((tmpf == 1) ? tmp : foo);
1156 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1157 SET_GPR (OP[0] + 0, hi);
1158 SET_GPR (OP[0] + 1, lo);
1159 trace_output_32 (((uint32) hi << 16) | lo);
1166 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1167 State.exe = (PSW_F0 == 0);
1168 trace_output_flag ();
1175 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1176 State.exe = (PSW_F0 != 0);
1177 trace_output_flag ();
1184 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1185 State.exe = (PSW_F1 == 0);
1186 trace_output_flag ();
1193 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1194 State.exe = (PSW_F1 != 0);
1195 trace_output_flag ();
1202 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1203 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1204 trace_output_flag ();
1211 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1212 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1213 trace_output_flag ();
1220 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1221 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1222 trace_output_flag ();
1229 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1230 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1231 trace_output_flag ();
1241 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1242 if (((int16)GPR (OP[1])) >= 0)
1243 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1245 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1252 SET_GPR (OP[0], (i - 1));
1253 trace_output_16 (i - 1);
1258 SET_GPR (OP[0], 16);
1259 trace_output_16 (16);
1269 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1270 tmp = SEXT40(ACC (OP[1]));
1272 tmp = ~tmp & MASK40;
1274 foo = 0x4000000000LL;
1279 SET_GPR (OP[0], i - 9);
1280 trace_output_16 (i - 9);
1285 SET_GPR (OP[0], 16);
1286 trace_output_16 (16);
1293 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1294 SET_GPR (13, PC + 1);
1296 trace_output_void ();
1303 trace_input ("jmp", OP_REG,
1304 (OP[0] == 13) ? OP_R0 : OP_VOID,
1305 (OP[0] == 13) ? OP_R1 : OP_VOID);
1308 trace_output_void ();
1316 uint16 addr = OP[1] + GPR (OP[2]);
1317 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1320 State.exception = SIG_D10V_BUS;
1321 State.pc_changed = 1; /* Don't increment the PC. */
1322 trace_output_void ();
1326 SET_GPR (OP[0], tmp);
1327 trace_output_16 (tmp);
1335 uint16 addr = GPR (OP[1]);
1336 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1339 State.exception = SIG_D10V_BUS;
1340 State.pc_changed = 1; /* Don't increment the PC. */
1341 trace_output_void ();
1345 SET_GPR (OP[0], tmp);
1347 INC_ADDR (OP[1], -2);
1348 trace_output_16 (tmp);
1356 uint16 addr = GPR (OP[1]);
1357 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1360 State.exception = SIG_D10V_BUS;
1361 State.pc_changed = 1; /* Don't increment the PC. */
1362 trace_output_void ();
1366 SET_GPR (OP[0], tmp);
1368 INC_ADDR (OP[1], 2);
1369 trace_output_16 (tmp);
1377 uint16 addr = GPR (OP[1]);
1378 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1381 State.exception = SIG_D10V_BUS;
1382 State.pc_changed = 1; /* Don't increment the PC. */
1383 trace_output_void ();
1387 SET_GPR (OP[0], tmp);
1388 trace_output_16 (tmp);
1396 uint16 addr = OP[1];
1397 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1400 State.exception = SIG_D10V_BUS;
1401 State.pc_changed = 1; /* Don't increment the PC. */
1402 trace_output_void ();
1406 SET_GPR (OP[0], tmp);
1407 trace_output_16 (tmp);
1415 uint16 addr = OP[1] + GPR (OP[2]);
1416 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1419 State.exception = SIG_D10V_BUS;
1420 State.pc_changed = 1; /* Don't increment the PC. */
1421 trace_output_void ();
1425 SET_GPR32 (OP[0], tmp);
1426 trace_output_32 (tmp);
1433 uint16 addr = GPR (OP[1]);
1435 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1438 State.exception = SIG_D10V_BUS;
1439 State.pc_changed = 1; /* Don't increment the PC. */
1440 trace_output_void ();
1444 SET_GPR32 (OP[0], tmp);
1445 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1446 INC_ADDR (OP[1], -4);
1447 trace_output_32 (tmp);
1455 uint16 addr = GPR (OP[1]);
1456 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1459 State.exception = SIG_D10V_BUS;
1460 State.pc_changed = 1; /* Don't increment the PC. */
1461 trace_output_void ();
1465 SET_GPR32 (OP[0], tmp);
1466 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1467 INC_ADDR (OP[1], 4);
1468 trace_output_32 (tmp);
1475 uint16 addr = GPR (OP[1]);
1477 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1480 State.exception = SIG_D10V_BUS;
1481 State.pc_changed = 1; /* Don't increment the PC. */
1482 trace_output_void ();
1486 SET_GPR32 (OP[0], tmp);
1487 trace_output_32 (tmp);
1495 uint16 addr = OP[1];
1496 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1499 State.exception = SIG_D10V_BUS;
1500 State.pc_changed = 1; /* Don't increment the PC. */
1501 trace_output_void ();
1505 SET_GPR32 (OP[0], tmp);
1506 trace_output_32 (tmp);
1514 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1515 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1516 SET_GPR (OP[0], tmp);
1517 trace_output_16 (tmp);
1525 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1526 tmp = SEXT8 (RB (GPR (OP[1])));
1527 SET_GPR (OP[0], tmp);
1528 trace_output_16 (tmp);
1536 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1537 tmp = SEXT4 (OP[1]);
1538 SET_GPR (OP[0], tmp);
1539 trace_output_16 (tmp);
1547 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1549 SET_GPR (OP[0], tmp);
1550 trace_output_16 (tmp);
1558 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1559 tmp = RB (OP[1] + GPR (OP[2]));
1560 SET_GPR (OP[0], tmp);
1561 trace_output_16 (tmp);
1569 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1570 tmp = RB (GPR (OP[1]));
1571 SET_GPR (OP[0], tmp);
1572 trace_output_16 (tmp);
1581 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1582 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1585 tmp = SEXT40( (tmp << 1) & MASK40);
1587 if (PSW_ST && tmp > SEXT40(MAX32))
1590 tmp += SEXT40 (ACC (OP[0]));
1593 if (tmp > SEXT40(MAX32))
1595 else if (tmp < SEXT40(MIN32))
1598 tmp = (tmp & MASK40);
1601 tmp = (tmp & MASK40);
1602 SET_ACC (OP[0], tmp);
1603 trace_output_40 (tmp);
1612 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1613 tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1615 tmp = SEXT40 ((tmp << 1) & MASK40);
1616 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1617 SET_ACC (OP[0], tmp);
1618 trace_output_40 (tmp);
1629 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1630 src1 = (uint16) GPR (OP[1]);
1631 src2 = (uint16) GPR (OP[2]);
1635 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1636 SET_ACC (OP[0], tmp);
1637 trace_output_40 (tmp);
1645 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1646 SET_PSW_F1 (PSW_F0);
1647 if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1657 SET_GPR (OP[0], tmp);
1658 trace_output_16 (tmp);
1667 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1668 SET_PSW_F1 (PSW_F0);
1669 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1670 if (tmp > SEXT40 (ACC (OP[0])))
1672 tmp = (tmp & MASK40);
1680 SET_ACC (OP[0], tmp);
1681 trace_output_40 (tmp);
1689 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1690 SET_PSW_F1 (PSW_F0);
1691 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1701 SET_ACC (OP[0], tmp);
1702 trace_output_40 (tmp);
1711 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1712 SET_PSW_F1 (PSW_F0);
1713 if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1723 SET_GPR (OP[0], tmp);
1724 trace_output_16 (tmp);
1733 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1734 SET_PSW_F1 (PSW_F0);
1735 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1736 if (tmp < SEXT40(ACC (OP[0])))
1738 tmp = (tmp & MASK40);
1746 SET_ACC (OP[0], tmp);
1747 trace_output_40 (tmp);
1755 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1756 SET_PSW_F1 (PSW_F0);
1757 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1767 SET_ACC (OP[0], tmp);
1768 trace_output_40 (tmp);
1777 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1778 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1781 tmp = SEXT40 ((tmp << 1) & MASK40);
1783 if (PSW_ST && tmp > SEXT40(MAX32))
1786 tmp = SEXT40(ACC (OP[0])) - tmp;
1789 if (tmp > SEXT40(MAX32))
1791 else if (tmp < SEXT40(MIN32))
1794 tmp = (tmp & MASK40);
1798 tmp = (tmp & MASK40);
1800 SET_ACC (OP[0], tmp);
1801 trace_output_40 (tmp);
1810 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1811 tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1813 tmp = SEXT40( (tmp << 1) & MASK40);
1814 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1815 SET_ACC (OP[0], tmp);
1816 trace_output_40 (tmp);
1827 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1828 src1 = (uint16) GPR (OP[1]);
1829 src2 = (uint16) GPR (OP[2]);
1833 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1834 SET_ACC (OP[0], tmp);
1835 trace_output_40 (tmp);
1843 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1844 tmp = GPR (OP[0]) * GPR (OP[1]);
1845 SET_GPR (OP[0], tmp);
1846 trace_output_16 (tmp);
1855 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1856 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1859 tmp = SEXT40 ((tmp << 1) & MASK40);
1861 if (PSW_ST && tmp > SEXT40(MAX32))
1864 tmp = (tmp & MASK40);
1865 SET_ACC (OP[0], tmp);
1866 trace_output_40 (tmp);
1875 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1876 tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1880 tmp = (tmp & MASK40);
1881 SET_ACC (OP[0], tmp);
1882 trace_output_40 (tmp);
1893 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1894 src1 = (uint16) GPR (OP[1]);
1895 src2 = (uint16) GPR (OP[2]);
1899 tmp = (tmp & MASK40);
1900 SET_ACC (OP[0], tmp);
1901 trace_output_40 (tmp);
1909 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1911 SET_GPR (OP[0], tmp);
1912 trace_output_16 (tmp);
1920 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1921 tmp = GPR32 (OP[1]);
1922 SET_GPR32 (OP[0], tmp);
1923 trace_output_32 (tmp);
1931 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1933 SET_GPR32 (OP[0], tmp);
1934 trace_output_32 (tmp);
1942 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1943 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1944 SET_ACC (OP[1], tmp);
1945 trace_output_40 (tmp);
1953 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1955 SET_ACC (OP[0], tmp);
1956 trace_output_40 (tmp);
1964 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1965 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1966 SET_GPR (OP[0], tmp);
1967 trace_output_16 (tmp);
1975 trace_input ("mvf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1979 SET_GPR (OP[0], tmp);
1983 trace_output_16 (tmp);
1991 trace_input ("mvf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1995 SET_GPR (OP[0], tmp);
1999 trace_output_16 (tmp);
2007 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2008 tmp = ((ACC (OP[1]) >> 32) & 0xff);
2009 SET_GPR (OP[0], tmp);
2010 trace_output_16 (tmp);
2018 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2019 tmp = (ACC (OP[1]) >> 16);
2020 SET_GPR (OP[0], tmp);
2021 trace_output_16 (tmp);
2029 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2031 SET_GPR (OP[0], tmp);
2032 trace_output_16 (tmp);
2040 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2042 SET_GPR (OP[0], tmp);
2043 trace_output_16 (tmp);
2051 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2052 tmp = ((ACC (OP[1]) & MASK32)
2053 | ((int64)(GPR (OP[0]) & 0xff) << 32));
2054 SET_ACC (OP[1], tmp);
2055 trace_output_40 (tmp);
2063 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2064 tmp = ACC (OP[1]) & 0xffff;
2065 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
2066 SET_ACC (OP[1], tmp);
2067 trace_output_40 (tmp);
2075 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
2076 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
2077 SET_ACC (OP[1], tmp);
2078 trace_output_40 (tmp);
2086 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2088 tmp = SET_CREG (OP[1], tmp);
2089 trace_output_16 (tmp);
2097 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2098 tmp = (GPR (OP[1]) & 0xff);
2099 SET_GPR (OP[0], tmp);
2100 trace_output_16 (tmp);
2108 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2109 tmp = - GPR (OP[0]);
2110 SET_GPR (OP[0], tmp);
2111 trace_output_16 (tmp);
2120 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2121 tmp = -SEXT40(ACC (OP[0]));
2124 if (tmp > SEXT40(MAX32))
2126 else if (tmp < SEXT40(MIN32))
2129 tmp = (tmp & MASK40);
2132 tmp = (tmp & MASK40);
2133 SET_ACC (OP[0], tmp);
2134 trace_output_40 (tmp);
2142 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2144 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2145 switch (State.ins_type)
2148 ins_type_counters[ (int)INS_UNKNOWN ]++;
2151 case INS_LEFT_PARALLEL:
2152 /* Don't count a parallel op that includes a NOP as a true parallel op */
2153 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2154 ins_type_counters[ (int)INS_RIGHT ]++;
2155 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2159 case INS_LEFT_COND_EXE:
2160 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2163 case INS_RIGHT_PARALLEL:
2164 /* Don't count a parallel op that includes a NOP as a true parallel op */
2165 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2166 ins_type_counters[ (int)INS_LEFT ]++;
2167 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2171 case INS_RIGHT_COND_EXE:
2172 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2176 trace_output_void ();
2184 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2186 SET_GPR (OP[0], tmp);
2187 trace_output_16 (tmp);
2195 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2196 tmp = (GPR (OP[0]) | GPR (OP[1]));
2197 SET_GPR (OP[0], tmp);
2198 trace_output_16 (tmp);
2206 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2207 tmp = (GPR (OP[1]) | OP[2]);
2208 SET_GPR (OP[0], tmp);
2209 trace_output_16 (tmp);
2217 int shift = SEXT3 (OP[2]);
2219 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2222 (*d10v_callback->printf_filtered) (d10v_callback,
2223 "ERROR at PC 0x%x: instruction only valid for A0\n",
2225 State.exception = SIGILL;
2228 SET_PSW_F1 (PSW_F0);
2229 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2235 tmp >>= 16; /* look at bits 0:43 */
2236 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2241 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2250 SET_GPR32 (OP[0], tmp);
2251 trace_output_32 (tmp);
2259 int shift = SEXT3 (OP[2]);
2261 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2262 SET_PSW_F1 (PSW_F0);
2264 tmp = SEXT40 (ACC (OP[1])) << shift;
2266 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2269 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2274 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2284 SET_GPR (OP[0], tmp);
2285 trace_output_16 (tmp);
2292 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2294 SET_RPT_E (PC + OP[1]);
2295 SET_RPT_C (GPR (OP[0]));
2297 if (GPR (OP[0]) == 0)
2299 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2300 State.exception = SIGILL;
2304 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2305 State.exception = SIGILL;
2307 trace_output_void ();
2314 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2316 SET_RPT_E (PC + OP[1]);
2321 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2322 State.exception = SIGILL;
2326 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2327 State.exception = SIGILL;
2329 trace_output_void ();
2336 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2337 SET_CREG (PSW_CR, DPSW);
2339 trace_output_void ();
2346 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2347 SET_CREG (PSW_CR, BPSW);
2349 trace_output_void ();
2357 trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2359 tmp = SEXT40(ACC (OP[1]));
2361 SET_PSW_F1 (PSW_F0);
2363 if (tmp > SEXT40(MAX32))
2368 else if (tmp < SEXT40(MIN32))
2375 tmp = (tmp & MASK32);
2379 SET_GPR32 (OP[0], tmp);
2381 trace_output_40 (tmp);
2390 trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2392 tmp = SEXT40(ACC (OP[1]));
2394 SET_PSW_F1 (PSW_F0);
2396 if (tmp > SEXT40(MAX32))
2401 else if (tmp < SEXT40(MIN32))
2412 SET_GPR (OP[0], tmp);
2414 trace_output_16 (OP[0]);
2423 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2424 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2427 if (tmp > SEXT40(MAX32))
2429 else if (tmp < SEXT40(MIN32))
2432 tmp = (tmp & MASK40);
2435 tmp = (tmp & MASK40);
2436 SET_ACC (OP[0], tmp);
2437 trace_output_40 (tmp);
2445 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2446 tmp = ((PSW_F0 == 0) ? 1 : 0);
2447 SET_GPR (OP[0], tmp);
2448 trace_output_16 (tmp);
2456 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2457 tmp = ((PSW_F0 == 1) ? 1 : 0);
2458 SET_GPR (OP[0], tmp);
2459 trace_output_16 (tmp);
2469 trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2471 reg = SEXT16 (GPR (OP[1]));
2473 if (reg >= 17 || reg <= -17)
2475 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
2476 State.exception = SIGILL;
2480 tmp = SEXT40 (ACC (OP[0]));
2482 if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2484 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
2485 State.exception = SIGILL;
2489 if (reg >= 0 && reg <= 16)
2491 tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2494 if (tmp > SEXT40(MAX32))
2496 else if (tmp < SEXT40(MIN32))
2499 tmp = (tmp & MASK40);
2502 tmp = (tmp & MASK40);
2506 tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2509 SET_ACC(OP[0], tmp);
2511 trace_output_40(tmp);
2518 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2520 trace_output_void ();
2528 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2529 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2530 SET_GPR (OP[0], tmp);
2531 trace_output_16 (tmp);
2539 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2540 if ((GPR (OP[1]) & 31) <= 16)
2541 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2544 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2545 State.exception = SIGILL;
2551 if (tmp > SEXT40(MAX32))
2553 else if (tmp < SEXT40(MIN32))
2556 tmp = (tmp & MASK40);
2559 tmp = (tmp & MASK40);
2560 SET_ACC (OP[0], tmp);
2561 trace_output_40 (tmp);
2569 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2570 tmp = (GPR (OP[0]) << OP[1]);
2571 SET_GPR (OP[0], tmp);
2572 trace_output_16 (tmp);
2584 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2585 tmp = SEXT40(ACC (OP[0])) << OP[1];
2589 if (tmp > SEXT40(MAX32))
2591 else if (tmp < SEXT40(MIN32))
2594 tmp = (tmp & MASK40);
2597 tmp = (tmp & MASK40);
2598 SET_ACC (OP[0], tmp);
2599 trace_output_40 (tmp);
2607 trace_input ("slx", OP_REG, OP_VOID, OP_VOID);
2608 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2609 SET_GPR (OP[0], tmp);
2610 trace_output_16 (tmp);
2618 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2619 tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2620 SET_GPR (OP[0], tmp);
2621 trace_output_16 (tmp);
2628 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2629 if ((GPR (OP[1]) & 31) <= 16)
2631 int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2632 SET_ACC (OP[0], tmp);
2633 trace_output_40 (tmp);
2637 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2638 State.exception = SIGILL;
2648 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2649 tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2650 SET_GPR (OP[0], tmp);
2651 trace_output_16 (tmp);
2662 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2663 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2664 SET_ACC (OP[0], tmp);
2665 trace_output_40 (tmp);
2673 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2674 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2675 SET_GPR (OP[0], tmp);
2676 trace_output_16 (tmp);
2683 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2684 if ((GPR (OP[1]) & 31) <= 16)
2686 int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2687 SET_ACC (OP[0], tmp);
2688 trace_output_40 (tmp);
2692 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2693 State.exception = SIGILL;
2704 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2705 tmp = (GPR (OP[0]) >> OP[1]);
2706 SET_GPR (OP[0], tmp);
2707 trace_output_16 (tmp);
2718 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2719 tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2720 SET_ACC (OP[0], tmp);
2721 trace_output_40 (tmp);
2729 trace_input ("srx", OP_REG, OP_VOID, OP_VOID);
2731 tmp = ((GPR (OP[0]) >> 1) | tmp);
2732 SET_GPR (OP[0], tmp);
2733 trace_output_16 (tmp);
2740 uint16 addr = OP[1] + GPR (OP[2]);
2741 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2744 State.exception = SIG_D10V_BUS;
2745 State.pc_changed = 1; /* Don't increment the PC. */
2746 trace_output_void ();
2749 SW (addr, GPR (OP[0]));
2750 trace_output_void ();
2757 uint16 addr = GPR (OP[1]);
2758 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2761 State.exception = SIG_D10V_BUS;
2762 State.pc_changed = 1; /* Don't increment the PC. */
2763 trace_output_void ();
2766 SW (addr, GPR (OP[0]));
2767 trace_output_void ();
2775 uint16 addr = GPR (OP[1]) - 2;
2776 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2779 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2780 State.exception = SIGILL;
2785 State.exception = SIG_D10V_BUS;
2786 State.pc_changed = 1; /* Don't increment the PC. */
2787 trace_output_void ();
2790 SW (addr, GPR (OP[0]));
2791 SET_GPR (OP[1], addr);
2792 trace_output_void ();
2799 uint16 addr = GPR (OP[1]);
2800 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2803 State.exception = SIG_D10V_BUS;
2804 State.pc_changed = 1; /* Don't increment the PC. */
2805 trace_output_void ();
2808 SW (addr, GPR (OP[0]));
2809 INC_ADDR (OP[1], 2);
2810 trace_output_void ();
2817 uint16 addr = GPR (OP[1]);
2818 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2821 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2822 State.exception = SIGILL;
2827 State.exception = SIG_D10V_BUS;
2828 State.pc_changed = 1; /* Don't increment the PC. */
2829 trace_output_void ();
2832 SW (addr, GPR (OP[0]));
2833 INC_ADDR (OP[1], -2);
2834 trace_output_void ();
2841 uint16 addr = OP[1];
2842 trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2845 State.exception = SIG_D10V_BUS;
2846 State.pc_changed = 1; /* Don't increment the PC. */
2847 trace_output_void ();
2850 SW (addr, GPR (OP[0]));
2851 trace_output_void ();
2858 uint16 addr = GPR (OP[2])+ OP[1];
2859 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2862 State.exception = SIG_D10V_BUS;
2863 State.pc_changed = 1; /* Don't increment the PC. */
2864 trace_output_void ();
2867 SW (addr + 0, GPR (OP[0] + 0));
2868 SW (addr + 2, GPR (OP[0] + 1));
2869 trace_output_void ();
2876 uint16 addr = GPR (OP[1]);
2877 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2880 State.exception = SIG_D10V_BUS;
2881 State.pc_changed = 1; /* Don't increment the PC. */
2882 trace_output_void ();
2885 SW (addr + 0, GPR (OP[0] + 0));
2886 SW (addr + 2, GPR (OP[0] + 1));
2887 trace_output_void ();
2894 uint16 addr = GPR (OP[1]) - 4;
2895 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2898 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2899 State.exception = SIGILL;
2904 State.exception = SIG_D10V_BUS;
2905 State.pc_changed = 1; /* Don't increment the PC. */
2906 trace_output_void ();
2909 SW (addr + 0, GPR (OP[0] + 0));
2910 SW (addr + 2, GPR (OP[0] + 1));
2911 SET_GPR (OP[1], addr);
2912 trace_output_void ();
2919 uint16 addr = GPR (OP[1]);
2920 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2923 State.exception = SIG_D10V_BUS;
2924 State.pc_changed = 1; /* Don't increment the PC. */
2925 trace_output_void ();
2928 SW (addr + 0, GPR (OP[0] + 0));
2929 SW (addr + 2, GPR (OP[0] + 1));
2930 INC_ADDR (OP[1], 4);
2931 trace_output_void ();
2938 uint16 addr = GPR (OP[1]);
2939 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2942 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2943 State.exception = SIGILL;
2948 State.exception = SIG_D10V_BUS;
2949 State.pc_changed = 1; /* Don't increment the PC. */
2950 trace_output_void ();
2953 SW (addr + 0, GPR (OP[0] + 0));
2954 SW (addr + 2, GPR (OP[0] + 1));
2955 INC_ADDR (OP[1], -4);
2956 trace_output_void ();
2963 uint16 addr = OP[1];
2964 trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2967 State.exception = SIG_D10V_BUS;
2968 State.pc_changed = 1; /* Don't increment the PC. */
2969 trace_output_void ();
2972 SW (addr + 0, GPR (OP[0] + 0));
2973 SW (addr + 2, GPR (OP[0] + 1));
2974 trace_output_void ();
2981 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2982 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2983 trace_output_void ();
2990 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2991 SB (GPR (OP[1]), GPR (OP[0]));
2992 trace_output_void ();
2999 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
3000 State.exception = SIG_D10V_STOP;
3001 trace_output_void ();
3008 uint16 a = GPR (OP[0]);
3009 uint16 b = GPR (OP[1]);
3010 uint16 tmp = (a - b);
3011 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
3012 /* see ../common/sim-alu.h for a more extensive discussion on how to
3013 compute the carry/overflow bits. */
3015 SET_GPR (OP[0], tmp);
3016 trace_output_16 (tmp);
3025 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
3026 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
3029 if (tmp > SEXT40(MAX32))
3031 else if (tmp < SEXT40(MIN32))
3034 tmp = (tmp & MASK40);
3037 tmp = (tmp & MASK40);
3038 SET_ACC (OP[0], tmp);
3040 trace_output_40 (tmp);
3050 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
3051 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
3054 if (tmp > SEXT40(MAX32))
3056 else if (tmp < SEXT40(MIN32))
3059 tmp = (tmp & MASK40);
3062 tmp = (tmp & MASK40);
3063 SET_ACC (OP[0], tmp);
3065 trace_output_40 (tmp);
3074 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
3075 a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
3076 b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
3077 /* see ../common/sim-alu.h for a more extensive discussion on how to
3078 compute the carry/overflow bits */
3081 SET_GPR32 (OP[0], tmp);
3082 trace_output_32 (tmp);
3091 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3092 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
3093 SET_GPR32 (OP[0], tmp);
3094 trace_output_32 (tmp);
3103 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3104 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
3105 SET_GPR32 (OP[0], tmp);
3106 trace_output_32 (tmp);
3115 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3116 SET_PSW_F1 (PSW_F0);
3117 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
3118 if (tmp > SEXT40(MAX32))
3123 else if (tmp < SEXT40(MIN32))
3132 SET_GPR32 (OP[0], tmp);
3133 trace_output_32 (tmp);
3142 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3143 SET_PSW_F1 (PSW_F0);
3144 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
3145 if (tmp > SEXT40(MAX32))
3150 else if (tmp < SEXT40(MIN32))
3159 SET_GPR32 (OP[0], tmp);
3160 trace_output_32 (tmp);
3171 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
3172 /* see ../common/sim-alu.h for a more extensive discussion on how to
3173 compute the carry/overflow bits. */
3174 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3175 tmp = ((unsigned)(unsigned16) GPR (OP[0])
3176 + (unsigned)(unsigned16) ( - OP[1]));
3177 SET_PSW_C (tmp >= (1 << 16));
3178 SET_GPR (OP[0], tmp);
3179 trace_output_16 (tmp);
3186 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
3187 trace_output_void ();
3192 #if (DEBUG & DEBUG_TRAP) == 0
3194 uint16 vec = OP[0] + TRAP_VECTOR_START;
3197 SET_PSW (PSW & PSW_SM_BIT);
3201 #else /* if debugging use trap to print registers */
3204 static int first_time = 1;
3209 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
3210 for (i = 0; i < 16; i++)
3211 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
3212 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
3215 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3217 for (i = 0; i < 16; i++)
3218 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
3220 for (i = 0; i < 2; i++)
3221 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
3222 ((int)(ACC (i) >> 32) & 0xff),
3223 ((unsigned long) ACC (i)) & 0xffffffff);
3225 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
3226 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3227 (*d10v_callback->flush_stdout) (d10v_callback);
3231 case 15: /* new system call trap */
3232 /* Trap 15 is used for simulating low-level I/O */
3234 unsigned32 result = 0;
3237 /* Registers passed to trap 0 */
3239 #define FUNC GPR (4) /* function number */
3240 #define PARM1 GPR (0) /* optional parm 1 */
3241 #define PARM2 GPR (1) /* optional parm 2 */
3242 #define PARM3 GPR (2) /* optional parm 3 */
3243 #define PARM4 GPR (3) /* optional parm 3 */
3245 /* Registers set by trap 0 */
3247 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3248 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3249 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3251 /* Turn a pointer in a register into a pointer into real memory. */
3253 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3257 #if !defined(__GO32__) && !defined(_WIN32)
3258 case TARGET_SYS_fork:
3259 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3261 trace_output_16 (result);
3265 case TARGET_SYS_getpid:
3266 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3268 trace_output_16 (result);
3271 case TARGET_SYS_kill:
3272 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3273 if (PARM1 == getpid ())
3275 trace_output_void ();
3276 State.exception = PARM2;
3284 case 1: os_sig = SIGHUP; break;
3287 case 2: os_sig = SIGINT; break;
3290 case 3: os_sig = SIGQUIT; break;
3293 case 4: os_sig = SIGILL; break;
3296 case 5: os_sig = SIGTRAP; break;
3299 case 6: os_sig = SIGABRT; break;
3300 #elif defined(SIGIOT)
3301 case 6: os_sig = SIGIOT; break;
3304 case 7: os_sig = SIGEMT; break;
3307 case 8: os_sig = SIGFPE; break;
3310 case 9: os_sig = SIGKILL; break;
3313 case 10: os_sig = SIGBUS; break;
3316 case 11: os_sig = SIGSEGV; break;
3319 case 12: os_sig = SIGSYS; break;
3322 case 13: os_sig = SIGPIPE; break;
3325 case 14: os_sig = SIGALRM; break;
3328 case 15: os_sig = SIGTERM; break;
3331 case 16: os_sig = SIGURG; break;
3334 case 17: os_sig = SIGSTOP; break;
3337 case 18: os_sig = SIGTSTP; break;
3340 case 19: os_sig = SIGCONT; break;
3343 case 20: os_sig = SIGCHLD; break;
3344 #elif defined(SIGCLD)
3345 case 20: os_sig = SIGCLD; break;
3348 case 21: os_sig = SIGTTIN; break;
3351 case 22: os_sig = SIGTTOU; break;
3354 case 23: os_sig = SIGIO; break;
3355 #elif defined (SIGPOLL)
3356 case 23: os_sig = SIGPOLL; break;
3359 case 24: os_sig = SIGXCPU; break;
3362 case 25: os_sig = SIGXFSZ; break;
3365 case 26: os_sig = SIGVTALRM; break;
3368 case 27: os_sig = SIGPROF; break;
3371 case 28: os_sig = SIGWINCH; break;
3374 case 29: os_sig = SIGLOST; break;
3377 case 30: os_sig = SIGUSR1; break;
3380 case 31: os_sig = SIGUSR2; break;
3386 trace_output_void ();
3387 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3388 (*d10v_callback->flush_stdout) (d10v_callback);
3389 State.exception = SIGILL;
3393 RETVAL (kill (PARM1, PARM2));
3394 trace_output_16 (result);
3399 case TARGET_SYS_execve:
3400 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3401 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3402 (char **)MEMPTR (PARM3)));
3403 trace_output_16 (result);
3406 #ifdef TARGET_SYS_execv
3407 case TARGET_SYS_execv:
3408 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3409 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3410 trace_output_16 (result);
3414 case TARGET_SYS_pipe:
3419 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3421 RETVAL (pipe (host_fd));
3422 SW (buf, host_fd[0]);
3423 buf += sizeof(uint16);
3424 SW (buf, host_fd[1]);
3425 trace_output_16 (result);
3430 #ifdef TARGET_SYS_wait
3431 case TARGET_SYS_wait:
3434 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3435 RETVAL (wait (&status));
3438 trace_output_16 (result);
3444 case TARGET_SYS_getpid:
3445 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3447 trace_output_16 (result);
3450 case TARGET_SYS_kill:
3451 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3452 trace_output_void ();
3453 State.exception = PARM2;
3457 case TARGET_SYS_read:
3458 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3459 RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3461 trace_output_16 (result);
3464 case TARGET_SYS_write:
3465 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3467 RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3468 MEMPTR (PARM2), PARM3));
3470 RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3471 MEMPTR (PARM2), PARM3));
3472 trace_output_16 (result);
3475 case TARGET_SYS_lseek:
3476 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3477 RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3478 ((((unsigned long) PARM2) << 16)
3479 || (unsigned long) PARM3),
3481 trace_output_32 (result);
3484 case TARGET_SYS_close:
3485 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3486 RETVAL (d10v_callback->close (d10v_callback, PARM1));
3487 trace_output_16 (result);
3490 case TARGET_SYS_open:
3491 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3492 RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3493 trace_output_16 (result);
3496 case TARGET_SYS_exit:
3497 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3498 State.exception = SIG_D10V_EXIT;
3499 trace_output_void ();
3502 #ifdef TARGET_SYS_stat
3503 case TARGET_SYS_stat:
3504 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3505 /* stat system call */
3507 struct stat host_stat;
3510 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3514 /* The hard-coded offsets and sizes were determined by using
3515 * the D10V compiler on a test program that used struct stat.
3517 SW (buf, host_stat.st_dev);
3518 SW (buf+2, host_stat.st_ino);
3519 SW (buf+4, host_stat.st_mode);
3520 SW (buf+6, host_stat.st_nlink);
3521 SW (buf+8, host_stat.st_uid);
3522 SW (buf+10, host_stat.st_gid);
3523 SW (buf+12, host_stat.st_rdev);
3524 SLW (buf+16, host_stat.st_size);
3525 SLW (buf+20, host_stat.st_atime);
3526 SLW (buf+28, host_stat.st_mtime);
3527 SLW (buf+36, host_stat.st_ctime);
3529 trace_output_16 (result);
3533 case TARGET_SYS_chown:
3534 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3535 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3536 trace_output_16 (result);
3539 case TARGET_SYS_chmod:
3540 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3541 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3542 trace_output_16 (result);
3546 #ifdef TARGET_SYS_utime
3547 case TARGET_SYS_utime:
3548 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3549 /* Cast the second argument to void *, to avoid type mismatch
3550 if a prototype is present. */
3551 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3552 trace_output_16 (result);
3558 #ifdef TARGET_SYS_time
3559 case TARGET_SYS_time:
3560 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3561 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3562 trace_output_32 (result);
3568 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3570 if ((uint16) result == (uint16) -1)
3571 RETERR (d10v_callback->get_errno(d10v_callback));
3583 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3584 SET_PSW_F1 (PSW_F0);;
3585 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3586 trace_output_flag ();
3593 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3594 SET_PSW_F1 (PSW_F0);
3595 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3596 trace_output_flag ();
3603 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3605 trace_output_void ();
3613 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3614 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3615 SET_GPR (OP[0], tmp);
3616 trace_output_16 (tmp);
3624 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3625 tmp = (GPR (OP[1]) ^ OP[2]);
3626 SET_GPR (OP[0], tmp);
3627 trace_output_16 (tmp);