13 #include "targ-vals.h"
15 extern char *strrchr ();
48 PSW_MASK = (PSW_SM_BIT
59 /* The following bits in the PSW _can't_ be set by instructions such
61 PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
65 move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
67 /* A MASK bit is set when the corresponding bit in the CR should
69 /* This assumes that (VAL & MASK) == 0 */
77 if ((mask & PSW_SM_BIT) == 0)
79 int new_psw_sm = (val & PSW_SM_BIT) != 0;
81 SET_HELD_SP (PSW_SM, GPR (SP_IDX));
82 if (PSW_SM != new_psw_sm)
84 SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
86 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
88 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
90 (*d10v_callback->printf_filtered)
92 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
94 State.exception = SIGILL;
97 /* keep an up-to-date psw around for tracing */
98 State.trace.psw = (State.trace.psw & mask) | val;
102 /* Just like PSW, mask things like DM out. */
115 /* only issue an update if the register is being changed */
116 if ((State.cregs[cr] & ~mask) != val)
117 SLOT_PEND_MASK (State.cregs[cr], mask, val);
122 static void trace_input_func PARAMS ((char *name,
127 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
129 #ifndef SIZE_INSTRUCTION
130 #define SIZE_INSTRUCTION 8
133 #ifndef SIZE_OPERANDS
134 #define SIZE_OPERANDS 18
138 #define SIZE_VALUES 13
141 #ifndef SIZE_LOCATION
142 #define SIZE_LOCATION 20
149 #ifndef SIZE_LINE_NUMBER
150 #define SIZE_LINE_NUMBER 4
154 trace_input_func (name, in1, in2, in3)
167 const char *filename;
168 const char *functionname;
169 unsigned int linenumber;
172 if ((d10v_debug & DEBUG_TRACE) == 0)
175 switch (State.ins_type)
178 case INS_UNKNOWN: type = " ?"; break;
179 case INS_LEFT: type = " L"; break;
180 case INS_RIGHT: type = " R"; break;
181 case INS_LEFT_PARALLEL: type = "*L"; break;
182 case INS_RIGHT_PARALLEL: type = "*R"; break;
183 case INS_LEFT_COND_TEST: type = "?L"; break;
184 case INS_RIGHT_COND_TEST: type = "?R"; break;
185 case INS_LEFT_COND_EXE: type = "&L"; break;
186 case INS_RIGHT_COND_EXE: type = "&R"; break;
187 case INS_LONG: type = " B"; break;
190 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
191 (*d10v_callback->printf_filtered) (d10v_callback,
193 SIZE_PC, (unsigned)PC,
195 SIZE_INSTRUCTION, name);
200 byte_pc = decode_pc ();
201 if (text && byte_pc >= text_start && byte_pc < text_end)
203 filename = (const char *)0;
204 functionname = (const char *)0;
206 if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
207 &filename, &functionname, &linenumber))
212 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
217 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
218 p += SIZE_LINE_NUMBER+2;
223 sprintf (p, "%s ", functionname);
228 char *q = strrchr (filename, '/');
229 sprintf (p, "%s ", (q) ? q+1 : filename);
238 (*d10v_callback->printf_filtered) (d10v_callback,
239 "0x%.*x %s: %-*.*s %-*s ",
240 SIZE_PC, (unsigned)PC,
242 SIZE_LOCATION, SIZE_LOCATION, buf,
243 SIZE_INSTRUCTION, name);
251 for (i = 0; i < 3; i++)
265 sprintf (p, "%sr%d", comma, OP[i]);
273 sprintf (p, "%scr%d", comma, OP[i]);
279 case OP_ACCUM_OUTPUT:
280 case OP_ACCUM_REVERSE:
281 sprintf (p, "%sa%d", comma, OP[i]);
287 sprintf (p, "%s%d", comma, OP[i]);
293 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
299 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
305 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
311 sprintf (p, "%s@r%d", comma, OP[i]);
317 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
323 sprintf (p, "%s@%d", comma, OP[i]);
329 sprintf (p, "%s@r%d+", comma, OP[i]);
335 sprintf (p, "%s@r%d-", comma, OP[i]);
341 sprintf (p, "%s@-r%d", comma, OP[i]);
349 sprintf (p, "%sf0", comma);
352 sprintf (p, "%sf1", comma);
355 sprintf (p, "%sc", comma);
363 if ((d10v_debug & DEBUG_VALUES) == 0)
367 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
372 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
375 for (i = 0; i < 3; i++)
381 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
387 case OP_ACCUM_OUTPUT:
389 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
397 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
398 (uint16) GPR (OP[i]));
402 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
406 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
407 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
412 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
413 (uint16) CREG (OP[i]));
417 case OP_ACCUM_REVERSE:
418 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
419 ((int)(ACC (OP[i]) >> 32) & 0xff),
420 ((unsigned long) ACC (OP[i])) & 0xffffffff);
424 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
429 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
430 (uint16)SEXT4(OP[i]));
434 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
435 (uint16)SEXT8(OP[i]));
439 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
440 (uint16)SEXT3(OP[i]));
445 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
449 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
453 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
459 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
461 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
462 (uint16)GPR (OP[i + 1]));
467 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
472 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
477 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
485 (*d10v_callback->flush_stdout) (d10v_callback);
489 do_trace_output_flush (void)
491 (*d10v_callback->flush_stdout) (d10v_callback);
495 do_trace_output_finish (void)
497 (*d10v_callback->printf_filtered) (d10v_callback,
498 " F0=%d F1=%d C=%d\n",
499 (State.trace.psw & PSW_F0_BIT) != 0,
500 (State.trace.psw & PSW_F1_BIT) != 0,
501 (State.trace.psw & PSW_C_BIT) != 0);
502 (*d10v_callback->flush_stdout) (d10v_callback);
506 trace_output_40 (uint64 val)
508 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
510 (*d10v_callback->printf_filtered) (d10v_callback,
511 " :: %*s0x%.2x%.8lx",
514 ((int)(val >> 32) & 0xff),
515 ((unsigned long) val) & 0xffffffff);
516 do_trace_output_finish ();
521 trace_output_32 (uint32 val)
523 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
525 (*d10v_callback->printf_filtered) (d10v_callback,
530 do_trace_output_finish ();
535 trace_output_16 (uint16 val)
537 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
539 (*d10v_callback->printf_filtered) (d10v_callback,
544 do_trace_output_finish ();
551 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
553 (*d10v_callback->printf_filtered) (d10v_callback, "\n");
554 do_trace_output_flush ();
561 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
563 (*d10v_callback->printf_filtered) (d10v_callback,
567 do_trace_output_finish ();
575 #define trace_input(NAME, IN1, IN2, IN3)
576 #define trace_output(RESULT)
584 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
594 SET_GPR (OP[0], tmp);
595 trace_output_16 (tmp);
603 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
606 tmp = SEXT40 (ACC (OP[0]));
612 if (tmp > SEXT40(MAX32))
614 else if (tmp < SEXT40(MIN32))
617 tmp = (tmp & MASK40);
620 tmp = (tmp & MASK40);
625 tmp = (tmp & MASK40);
628 SET_ACC (OP[0], tmp);
629 trace_output_40 (tmp);
636 uint16 a = GPR (OP[0]);
637 uint16 b = GPR (OP[1]);
638 uint16 tmp = (a + b);
639 trace_input ("add", OP_REG, OP_REG, OP_VOID);
641 SET_GPR (OP[0], tmp);
642 trace_output_16 (tmp);
650 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
652 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
655 if (tmp > SEXT40(MAX32))
657 else if (tmp < SEXT40(MIN32))
660 tmp = (tmp & MASK40);
663 tmp = (tmp & MASK40);
664 SET_ACC (OP[0], tmp);
665 trace_output_40 (tmp);
673 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
675 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
678 if (tmp > SEXT40(MAX32))
680 else if (tmp < SEXT40(MIN32))
683 tmp = (tmp & MASK40);
686 tmp = (tmp & MASK40);
687 SET_ACC (OP[0], tmp);
688 trace_output_40 (tmp);
696 uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
697 uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
698 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
701 SET_GPR (OP[0] + 0, (tmp >> 16));
702 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
703 trace_output_32 (tmp);
710 uint16 a = GPR (OP[1]);
712 uint16 tmp = (a + b);
713 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
715 SET_GPR (OP[0], tmp);
716 trace_output_16 (tmp);
724 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
726 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
727 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
728 SET_GPR (OP[0] + 1, (tmp & 0xffff));
729 trace_output_32 (tmp);
737 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
739 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
740 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
741 SET_GPR (OP[0] + 1, tmp & 0xffff);
742 trace_output_32 (tmp);
752 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
753 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
754 if (tmp > SEXT40(MAX32))
759 else if (tmp < SEXT40(MIN32))
768 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
769 SET_GPR (OP[0] + 1, (tmp & 0xffff));
770 trace_output_32 (tmp);
780 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
781 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
782 if (tmp > SEXT40(MAX32))
787 else if (tmp < SEXT40(MIN32))
796 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
797 SET_GPR (OP[0] + 1, (tmp & 0xffff));
798 trace_output_32 (tmp);
805 uint16 a = GPR (OP[0]);
812 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
814 SET_GPR (OP[0], tmp);
815 trace_output_16 (tmp);
822 uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
823 trace_input ("and", OP_REG, OP_REG, OP_VOID);
824 SET_GPR (OP[0], tmp);
825 trace_output_16 (tmp);
832 uint16 tmp = GPR (OP[1]) & OP[2];
833 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
834 SET_GPR (OP[0], tmp);
835 trace_output_16 (tmp);
843 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
844 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
845 SET_GPR (OP[0], tmp);
846 trace_output_16 (tmp);
853 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
854 SET_GPR (13, PC + 1);
855 JMP( PC + SEXT8 (OP[0]));
856 trace_output_void ();
863 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
864 SET_GPR (13, (PC + 1));
866 trace_output_void ();
874 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
875 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
876 SET_GPR (OP[0], tmp);
877 trace_output_16 (tmp);
884 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
885 JMP (PC + SEXT8 (OP[0]));
886 trace_output_void ();
893 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
895 trace_output_void ();
902 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
904 JMP (PC + SEXT8 (OP[0]));
905 trace_output_flag ();
912 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
915 trace_output_flag ();
922 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
924 JMP (PC + SEXT8 (OP[0]));
925 trace_output_flag ();
932 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
935 trace_output_flag ();
943 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
944 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
945 SET_GPR (OP[0], tmp);
946 trace_output_16 (tmp);
953 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
955 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
956 trace_output_flag ();
963 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
972 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
974 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
975 trace_output_flag ();
982 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
984 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
985 trace_output_flag ();
992 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
994 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
995 trace_output_flag ();
1002 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
1003 SET_PSW_F1 (PSW_F0);
1004 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
1005 trace_output_flag ();
1012 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1013 SET_PSW_F1 (PSW_F0);
1014 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1015 trace_output_flag ();
1022 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1023 SET_PSW_F1 (PSW_F0);
1024 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1025 trace_output_flag ();
1032 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1033 SET_PSW_F1 (PSW_F0);
1034 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1035 trace_output_flag ();
1042 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1043 SET_PSW_F1 (PSW_F0);
1044 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1045 trace_output_flag ();
1052 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1053 SET_PSW_F1 (PSW_F0);
1054 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1055 trace_output_flag ();
1062 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1063 SET_PSW_F1 (PSW_F0);
1064 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1065 trace_output_flag ();
1074 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1078 else if (OP[1] == 1)
1087 trace_output_flag ();
1096 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1100 else if (OP[1] == 1)
1109 trace_output_flag ();
1116 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1118 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1119 The conditional below is for either of the instruction pairs
1120 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1121 where the dbt instruction should be interpreted.
1123 The module `sim-break' provides a more effective mechanism for
1124 detecting GDB planted breakpoints. The code below may,
1125 eventually, be changed to use that mechanism. */
1127 if (State.ins_type == INS_LEFT
1128 || State.ins_type == INS_RIGHT)
1130 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1133 SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1134 JMP (DBT_VECTOR_START);
1135 trace_output_void ();
1139 State.exception = SIGTRAP;
1147 uint16 foo, tmp, tmpf;
1151 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1152 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1153 tmp = (int16)foo - (int16)(GPR (OP[1]));
1154 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1155 hi = ((tmpf == 1) ? tmp : foo);
1156 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1157 SET_GPR (OP[0] + 0, hi);
1158 SET_GPR (OP[0] + 1, lo);
1159 trace_output_32 (((uint32) hi << 16) | lo);
1166 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1167 State.exe = (PSW_F0 == 0);
1168 trace_output_flag ();
1175 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1176 State.exe = (PSW_F0 != 0);
1177 trace_output_flag ();
1184 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1185 State.exe = (PSW_F1 == 0);
1186 trace_output_flag ();
1193 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1194 State.exe = (PSW_F1 != 0);
1195 trace_output_flag ();
1202 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1203 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1204 trace_output_flag ();
1211 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1212 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1213 trace_output_flag ();
1220 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1221 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1222 trace_output_flag ();
1229 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1230 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1231 trace_output_flag ();
1241 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1242 if (((int16)GPR (OP[1])) >= 0)
1243 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1245 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1252 SET_GPR (OP[0], (i - 1));
1253 trace_output_16 (i - 1);
1258 SET_GPR (OP[0], 16);
1259 trace_output_16 (16);
1269 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1270 tmp = SEXT40(ACC (OP[1]));
1272 tmp = ~tmp & MASK40;
1274 foo = 0x4000000000LL;
1279 SET_GPR (OP[0], i - 9);
1280 trace_output_16 (i - 9);
1285 SET_GPR (OP[0], 16);
1286 trace_output_16 (16);
1293 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1294 SET_GPR (13, PC + 1);
1296 trace_output_void ();
1303 trace_input ("jmp", OP_REG,
1304 (OP[0] == 13) ? OP_R0 : OP_VOID,
1305 (OP[0] == 13) ? OP_R1 : OP_VOID);
1308 trace_output_void ();
1316 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1317 tmp = RW (OP[1] + GPR (OP[2]));
1318 SET_GPR (OP[0], tmp);
1319 trace_output_16 (tmp);
1327 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1328 tmp = RW (GPR (OP[1]));
1329 SET_GPR (OP[0], tmp);
1331 INC_ADDR (OP[1], -2);
1332 trace_output_16 (tmp);
1340 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1341 tmp = RW (GPR (OP[1]));
1342 SET_GPR (OP[0], tmp);
1344 INC_ADDR (OP[1], 2);
1345 trace_output_16 (tmp);
1353 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1354 tmp = RW (GPR (OP[1]));
1355 SET_GPR (OP[0], tmp);
1356 trace_output_16 (tmp);
1365 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1367 SET_GPR (OP[0], tmp);
1368 trace_output_16 (tmp);
1376 uint16 addr = GPR (OP[2]);
1377 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1378 tmp = RLW (OP[1] + addr);
1379 SET_GPR32 (OP[0], tmp);
1380 trace_output_32 (tmp);
1387 uint16 addr = GPR (OP[1]);
1389 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1391 SET_GPR32 (OP[0], tmp);
1392 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1393 INC_ADDR (OP[1], -4);
1394 trace_output_32 (tmp);
1402 uint16 addr = GPR (OP[1]);
1403 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1405 SET_GPR32 (OP[0], tmp);
1406 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1407 INC_ADDR (OP[1], 4);
1408 trace_output_32 (tmp);
1415 uint16 addr = GPR (OP[1]);
1417 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1418 tmp = RLW (addr + 0);
1419 SET_GPR32 (OP[0], tmp);
1420 trace_output_32 (tmp);
1429 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1431 SET_GPR32 (OP[0], tmp);
1432 trace_output_32 (tmp);
1440 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1441 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1442 SET_GPR (OP[0], tmp);
1443 trace_output_16 (tmp);
1451 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1452 tmp = SEXT8 (RB (GPR (OP[1])));
1453 SET_GPR (OP[0], tmp);
1454 trace_output_16 (tmp);
1462 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1463 tmp = SEXT4 (OP[1]);
1464 SET_GPR (OP[0], tmp);
1465 trace_output_16 (tmp);
1473 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1475 SET_GPR (OP[0], tmp);
1476 trace_output_16 (tmp);
1484 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1485 tmp = RB (OP[1] + GPR (OP[2]));
1486 SET_GPR (OP[0], tmp);
1487 trace_output_16 (tmp);
1495 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1496 tmp = RB (GPR (OP[1]));
1497 SET_GPR (OP[0], tmp);
1498 trace_output_16 (tmp);
1507 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1508 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1511 tmp = SEXT40( (tmp << 1) & MASK40);
1513 if (PSW_ST && tmp > SEXT40(MAX32))
1516 tmp += SEXT40 (ACC (OP[0]));
1519 if (tmp > SEXT40(MAX32))
1521 else if (tmp < SEXT40(MIN32))
1524 tmp = (tmp & MASK40);
1527 tmp = (tmp & MASK40);
1528 SET_ACC (OP[0], tmp);
1529 trace_output_40 (tmp);
1538 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1539 tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1541 tmp = SEXT40 ((tmp << 1) & MASK40);
1542 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1543 SET_ACC (OP[0], tmp);
1544 trace_output_40 (tmp);
1555 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1556 src1 = (uint16) GPR (OP[1]);
1557 src2 = (uint16) GPR (OP[2]);
1561 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1562 SET_ACC (OP[0], tmp);
1563 trace_output_40 (tmp);
1571 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1572 SET_PSW_F1 (PSW_F0);
1573 if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1583 SET_GPR (OP[0], tmp);
1584 trace_output_16 (tmp);
1593 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1594 SET_PSW_F1 (PSW_F0);
1595 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1596 if (tmp > SEXT40 (ACC (OP[0])))
1598 tmp = (tmp & MASK40);
1606 SET_ACC (OP[0], tmp);
1607 trace_output_40 (tmp);
1615 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1616 SET_PSW_F1 (PSW_F0);
1617 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1627 SET_ACC (OP[0], tmp);
1628 trace_output_40 (tmp);
1637 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1638 SET_PSW_F1 (PSW_F0);
1639 if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1649 SET_GPR (OP[0], tmp);
1650 trace_output_16 (tmp);
1659 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1660 SET_PSW_F1 (PSW_F0);
1661 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1662 if (tmp < SEXT40(ACC (OP[0])))
1664 tmp = (tmp & MASK40);
1672 SET_ACC (OP[0], tmp);
1673 trace_output_40 (tmp);
1681 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1682 SET_PSW_F1 (PSW_F0);
1683 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1693 SET_ACC (OP[0], tmp);
1694 trace_output_40 (tmp);
1703 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1704 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1707 tmp = SEXT40 ((tmp << 1) & MASK40);
1709 if (PSW_ST && tmp > SEXT40(MAX32))
1712 tmp = SEXT40(ACC (OP[0])) - tmp;
1715 if (tmp > SEXT40(MAX32))
1717 else if (tmp < SEXT40(MIN32))
1720 tmp = (tmp & MASK40);
1724 tmp = (tmp & MASK40);
1726 SET_ACC (OP[0], tmp);
1727 trace_output_40 (tmp);
1736 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1737 tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1739 tmp = SEXT40( (tmp << 1) & MASK40);
1740 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1741 SET_ACC (OP[0], tmp);
1742 trace_output_40 (tmp);
1753 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1754 src1 = (uint16) GPR (OP[1]);
1755 src2 = (uint16) GPR (OP[2]);
1759 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1760 SET_ACC (OP[0], tmp);
1761 trace_output_40 (tmp);
1769 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1770 tmp = GPR (OP[0]) * GPR (OP[1]);
1771 SET_GPR (OP[0], tmp);
1772 trace_output_16 (tmp);
1781 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1782 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1785 tmp = SEXT40 ((tmp << 1) & MASK40);
1787 if (PSW_ST && tmp > SEXT40(MAX32))
1790 tmp = (tmp & MASK40);
1791 SET_ACC (OP[0], tmp);
1792 trace_output_40 (tmp);
1801 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1802 tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1806 tmp = (tmp & MASK40);
1807 SET_ACC (OP[0], tmp);
1808 trace_output_40 (tmp);
1819 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1820 src1 = (uint16) GPR (OP[1]);
1821 src2 = (uint16) GPR (OP[2]);
1825 tmp = (tmp & MASK40);
1826 SET_ACC (OP[0], tmp);
1827 trace_output_40 (tmp);
1835 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1837 SET_GPR (OP[0], tmp);
1838 trace_output_16 (tmp);
1846 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1847 tmp = GPR32 (OP[1]);
1848 SET_GPR32 (OP[0], tmp);
1849 trace_output_32 (tmp);
1857 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1859 SET_GPR32 (OP[0], tmp);
1860 trace_output_32 (tmp);
1868 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1869 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1870 SET_ACC (OP[1], tmp);
1871 trace_output_40 (tmp);
1879 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1881 SET_ACC (OP[0], tmp);
1882 trace_output_40 (tmp);
1890 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1891 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1892 SET_GPR (OP[0], tmp);
1893 trace_output_16 (tmp);
1901 trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1905 SET_GPR (OP[0], tmp);
1909 trace_output_16 (tmp);
1917 trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1921 SET_GPR (OP[0], tmp);
1925 trace_output_16 (tmp);
1933 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1934 tmp = ((ACC (OP[1]) >> 32) & 0xff);
1935 SET_GPR (OP[0], tmp);
1936 trace_output_16 (tmp);
1944 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1945 tmp = (ACC (OP[1]) >> 16);
1946 SET_GPR (OP[0], tmp);
1947 trace_output_16 (tmp);
1955 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1957 SET_GPR (OP[0], tmp);
1958 trace_output_16 (tmp);
1966 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
1968 SET_GPR (OP[0], tmp);
1969 trace_output_16 (tmp);
1977 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
1978 tmp = ((ACC (OP[1]) & MASK32)
1979 | ((int64)(GPR (OP[0]) & 0xff) << 32));
1980 SET_ACC (OP[1], tmp);
1981 trace_output_40 (tmp);
1989 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
1990 tmp = ACC (OP[1]) & 0xffff;
1991 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
1992 SET_ACC (OP[1], tmp);
1993 trace_output_40 (tmp);
2001 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
2002 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
2003 SET_ACC (OP[1], tmp);
2004 trace_output_40 (tmp);
2012 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2014 tmp = SET_CREG (OP[1], tmp);
2015 trace_output_16 (tmp);
2023 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2024 tmp = (GPR (OP[1]) & 0xff);
2025 SET_GPR (OP[0], tmp);
2026 trace_output_16 (tmp);
2034 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2035 tmp = - GPR (OP[0]);
2036 SET_GPR (OP[0], tmp);
2037 trace_output_16 (tmp);
2046 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2047 tmp = -SEXT40(ACC (OP[0]));
2050 if (tmp > SEXT40(MAX32))
2052 else if (tmp < SEXT40(MIN32))
2055 tmp = (tmp & MASK40);
2058 tmp = (tmp & MASK40);
2059 SET_ACC (OP[0], tmp);
2060 trace_output_40 (tmp);
2068 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2070 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2071 switch (State.ins_type)
2074 ins_type_counters[ (int)INS_UNKNOWN ]++;
2077 case INS_LEFT_PARALLEL:
2078 /* Don't count a parallel op that includes a NOP as a true parallel op */
2079 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2080 ins_type_counters[ (int)INS_RIGHT ]++;
2081 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2085 case INS_LEFT_COND_EXE:
2086 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2089 case INS_RIGHT_PARALLEL:
2090 /* Don't count a parallel op that includes a NOP as a true parallel op */
2091 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2092 ins_type_counters[ (int)INS_LEFT ]++;
2093 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2097 case INS_RIGHT_COND_EXE:
2098 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2102 trace_output_void ();
2110 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2112 SET_GPR (OP[0], tmp);
2113 trace_output_16 (tmp);
2121 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2122 tmp = (GPR (OP[0]) | GPR (OP[1]));
2123 SET_GPR (OP[0], tmp);
2124 trace_output_16 (tmp);
2132 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2133 tmp = (GPR (OP[1]) | OP[2]);
2134 SET_GPR (OP[0], tmp);
2135 trace_output_16 (tmp);
2143 int shift = SEXT3 (OP[2]);
2145 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2148 (*d10v_callback->printf_filtered) (d10v_callback,
2149 "ERROR at PC 0x%x: instruction only valid for A0\n",
2151 State.exception = SIGILL;
2154 SET_PSW_F1 (PSW_F0);
2155 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2161 tmp >>= 16; /* look at bits 0:43 */
2162 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2167 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2176 SET_GPR32 (OP[0], tmp);
2177 trace_output_32 (tmp);
2185 int shift = SEXT3 (OP[2]);
2187 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2188 SET_PSW_F1 (PSW_F0);
2190 tmp = SEXT40 (ACC (OP[1])) << shift;
2192 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2195 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2200 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2210 SET_GPR (OP[0], tmp);
2211 trace_output_16 (tmp);
2218 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2220 SET_RPT_E (PC + OP[1]);
2221 SET_RPT_C (GPR (OP[0]));
2223 if (GPR (OP[0]) == 0)
2225 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2226 State.exception = SIGILL;
2230 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2231 State.exception = SIGILL;
2233 trace_output_void ();
2240 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2242 SET_RPT_E (PC + OP[1]);
2247 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2248 State.exception = SIGILL;
2252 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2253 State.exception = SIGILL;
2255 trace_output_void ();
2262 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2263 SET_CREG (PSW_CR, DPSW);
2265 trace_output_void ();
2272 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2273 SET_CREG (PSW_CR, BPSW);
2275 trace_output_void ();
2283 trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2285 tmp = SEXT40(ACC (OP[1]));
2287 SET_PSW_F1 (PSW_F0);
2289 if (tmp > SEXT40(MAX32))
2294 else if (tmp < SEXT40(MIN32))
2301 tmp = (tmp & MASK32);
2305 SET_GPR32 (OP[0], tmp);
2307 trace_output_40 (tmp);
2316 trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2318 tmp = SEXT40(ACC (OP[1]));
2320 SET_PSW_F1 (PSW_F0);
2322 if (tmp > SEXT40(MAX32))
2327 else if (tmp < SEXT40(MIN32))
2338 SET_GPR (OP[0], tmp);
2340 trace_output_16 (OP[0]);
2349 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2350 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2353 if (tmp > SEXT40(MAX32))
2355 else if (tmp < SEXT40(MIN32))
2358 tmp = (tmp & MASK40);
2361 tmp = (tmp & MASK40);
2362 SET_ACC (OP[0], tmp);
2363 trace_output_40 (tmp);
2371 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2372 tmp = ((PSW_F0 == 0) ? 1 : 0);
2373 SET_GPR (OP[0], tmp);
2374 trace_output_16 (tmp);
2382 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2383 tmp = ((PSW_F0 == 1) ? 1 : 0);
2384 SET_GPR (OP[0], tmp);
2385 trace_output_16 (tmp);
2395 trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2397 reg = SEXT16 (GPR (OP[1]));
2399 if (reg >= 17 || reg <= -17)
2401 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
2402 State.exception = SIGILL;
2406 tmp = SEXT40 (ACC (OP[0]));
2408 if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2410 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
2411 State.exception = SIGILL;
2415 if (reg >= 0 && reg <= 16)
2417 tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2420 if (tmp > SEXT40(MAX32))
2422 else if (tmp < SEXT40(MIN32))
2425 tmp = (tmp & MASK40);
2428 tmp = (tmp & MASK40);
2432 tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2435 SET_ACC(OP[0], tmp);
2437 trace_output_40(tmp);
2444 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2446 trace_output_void ();
2454 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2455 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2456 SET_GPR (OP[0], tmp);
2457 trace_output_16 (tmp);
2465 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2466 if ((GPR (OP[1]) & 31) <= 16)
2467 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2470 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2471 State.exception = SIGILL;
2477 if (tmp > SEXT40(MAX32))
2479 else if (tmp < SEXT40(MIN32))
2482 tmp = (tmp & MASK40);
2485 tmp = (tmp & MASK40);
2486 SET_ACC (OP[0], tmp);
2487 trace_output_40 (tmp);
2495 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2496 tmp = (GPR (OP[0]) << OP[1]);
2497 SET_GPR (OP[0], tmp);
2498 trace_output_16 (tmp);
2510 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2511 tmp = SEXT40(ACC (OP[0])) << OP[1];
2515 if (tmp > SEXT40(MAX32))
2517 else if (tmp < SEXT40(MIN32))
2520 tmp = (tmp & MASK40);
2523 tmp = (tmp & MASK40);
2524 SET_ACC (OP[0], tmp);
2525 trace_output_40 (tmp);
2533 trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
2534 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2535 SET_GPR (OP[0], tmp);
2536 trace_output_16 (tmp);
2544 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2545 tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2546 SET_GPR (OP[0], tmp);
2547 trace_output_16 (tmp);
2554 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2555 if ((GPR (OP[1]) & 31) <= 16)
2557 int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2558 SET_ACC (OP[0], tmp);
2559 trace_output_40 (tmp);
2563 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2564 State.exception = SIGILL;
2574 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2575 tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2576 SET_GPR (OP[0], tmp);
2577 trace_output_16 (tmp);
2588 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2589 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2590 SET_ACC (OP[0], tmp);
2591 trace_output_40 (tmp);
2599 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2600 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2601 SET_GPR (OP[0], tmp);
2602 trace_output_16 (tmp);
2609 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2610 if ((GPR (OP[1]) & 31) <= 16)
2612 int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2613 SET_ACC (OP[0], tmp);
2614 trace_output_40 (tmp);
2618 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2619 State.exception = SIGILL;
2630 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2631 tmp = (GPR (OP[0]) >> OP[1]);
2632 SET_GPR (OP[0], tmp);
2633 trace_output_16 (tmp);
2644 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2645 tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2646 SET_ACC (OP[0], tmp);
2647 trace_output_40 (tmp);
2655 trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
2657 tmp = ((GPR (OP[0]) >> 1) | tmp);
2658 SET_GPR (OP[0], tmp);
2659 trace_output_16 (tmp);
2666 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2667 SW (OP[1] + GPR (OP[2]), GPR (OP[0]));
2668 trace_output_void ();
2675 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2676 SW (GPR (OP[1]), GPR (OP[0]));
2677 trace_output_void ();
2684 uint16 addr = GPR (OP[1]) - 2;
2685 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2688 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2689 State.exception = SIGILL;
2692 SW (addr, GPR (OP[0]));
2693 SET_GPR (OP[1], addr);
2694 trace_output_void ();
2701 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2702 SW (GPR (OP[1]), GPR (OP[0]));
2703 INC_ADDR (OP[1], 2);
2704 trace_output_void ();
2711 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2714 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2715 State.exception = SIGILL;
2718 SW (GPR (OP[1]), GPR (OP[0]));
2719 INC_ADDR (OP[1], -2);
2720 trace_output_void ();
2727 trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2728 SW (OP[1], GPR (OP[0]));
2729 trace_output_void ();
2736 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2737 SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0));
2738 SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1));
2739 trace_output_void ();
2746 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2747 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2748 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2749 trace_output_void ();
2756 uint16 addr = GPR (OP[1]) - 4;
2757 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2760 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2761 State.exception = SIGILL;
2764 SW (addr + 0, GPR (OP[0] + 0));
2765 SW (addr + 2, GPR (OP[0] + 1));
2766 SET_GPR (OP[1], addr);
2767 trace_output_void ();
2774 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2775 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2776 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2777 INC_ADDR (OP[1], 4);
2778 trace_output_void ();
2785 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2788 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2789 State.exception = SIGILL;
2792 SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
2793 SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
2794 INC_ADDR (OP[1], -4);
2795 trace_output_void ();
2802 trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2803 SW (OP [1] + 0, GPR (OP[0] + 0));
2804 SW (OP [1] + 2, GPR (OP[0] + 1));
2805 trace_output_void ();
2812 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2813 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2814 trace_output_void ();
2821 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2822 SB (GPR (OP[1]), GPR (OP[0]));
2823 trace_output_void ();
2830 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
2831 State.exception = SIG_D10V_STOP;
2832 trace_output_void ();
2839 uint16 a = GPR (OP[0]);
2840 uint16 b = GPR (OP[1]);
2841 uint16 tmp = (a - b);
2842 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
2843 /* see ../common/sim-alu.h for a more extensive discussion on how to
2844 compute the carry/overflow bits. */
2846 SET_GPR (OP[0], tmp);
2847 trace_output_16 (tmp);
2856 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
2857 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
2860 if (tmp > SEXT40(MAX32))
2862 else if (tmp < SEXT40(MIN32))
2865 tmp = (tmp & MASK40);
2868 tmp = (tmp & MASK40);
2869 SET_ACC (OP[0], tmp);
2871 trace_output_40 (tmp);
2881 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
2882 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
2885 if (tmp > SEXT40(MAX32))
2887 else if (tmp < SEXT40(MIN32))
2890 tmp = (tmp & MASK40);
2893 tmp = (tmp & MASK40);
2894 SET_ACC (OP[0], tmp);
2896 trace_output_40 (tmp);
2905 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
2906 a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
2907 b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
2908 /* see ../common/sim-alu.h for a more extensive discussion on how to
2909 compute the carry/overflow bits */
2912 SET_GPR32 (OP[0], tmp);
2913 trace_output_32 (tmp);
2922 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2923 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
2924 SET_GPR32 (OP[0], tmp);
2925 trace_output_32 (tmp);
2934 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2935 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
2936 SET_GPR32 (OP[0], tmp);
2937 trace_output_32 (tmp);
2946 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
2947 SET_PSW_F1 (PSW_F0);
2948 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
2949 if (tmp > SEXT40(MAX32))
2954 else if (tmp < SEXT40(MIN32))
2963 SET_GPR32 (OP[0], tmp);
2964 trace_output_32 (tmp);
2973 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
2974 SET_PSW_F1 (PSW_F0);
2975 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
2976 if (tmp > SEXT40(MAX32))
2981 else if (tmp < SEXT40(MIN32))
2990 SET_GPR32 (OP[0], tmp);
2991 trace_output_32 (tmp);
3002 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
3003 /* see ../common/sim-alu.h for a more extensive discussion on how to
3004 compute the carry/overflow bits. */
3005 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3006 tmp = ((unsigned)(unsigned16) GPR (OP[0])
3007 + (unsigned)(unsigned16) ( - OP[1]));
3008 SET_PSW_C (tmp >= (1 << 16));
3009 SET_GPR (OP[0], tmp);
3010 trace_output_16 (tmp);
3017 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
3018 trace_output_void ();
3023 #if (DEBUG & DEBUG_TRAP) == 0
3025 uint16 vec = OP[0] + TRAP_VECTOR_START;
3028 SET_PSW (PSW & PSW_SM_BIT);
3032 #else /* if debugging use trap to print registers */
3035 static int first_time = 1;
3040 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
3041 for (i = 0; i < 16; i++)
3042 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
3043 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
3046 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3048 for (i = 0; i < 16; i++)
3049 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
3051 for (i = 0; i < 2; i++)
3052 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
3053 ((int)(ACC (i) >> 32) & 0xff),
3054 ((unsigned long) ACC (i)) & 0xffffffff);
3056 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
3057 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3058 (*d10v_callback->flush_stdout) (d10v_callback);
3062 case 15: /* new system call trap */
3063 /* Trap 15 is used for simulating low-level I/O */
3065 unsigned32 result = 0;
3068 /* Registers passed to trap 0 */
3070 #define FUNC GPR (4) /* function number */
3071 #define PARM1 GPR (0) /* optional parm 1 */
3072 #define PARM2 GPR (1) /* optional parm 2 */
3073 #define PARM3 GPR (2) /* optional parm 3 */
3074 #define PARM4 GPR (3) /* optional parm 3 */
3076 /* Registers set by trap 0 */
3078 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3079 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3080 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3082 /* Turn a pointer in a register into a pointer into real memory. */
3084 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3088 #if !defined(__GO32__) && !defined(_WIN32)
3089 case TARGET_SYS_fork:
3090 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3092 trace_output_16 (result);
3096 case TARGET_SYS_getpid:
3097 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3099 trace_output_16 (result);
3102 case TARGET_SYS_kill:
3103 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3104 if (PARM1 == getpid ())
3106 trace_output_void ();
3107 State.exception = PARM2;
3115 case 1: os_sig = SIGHUP; break;
3118 case 2: os_sig = SIGINT; break;
3121 case 3: os_sig = SIGQUIT; break;
3124 case 4: os_sig = SIGILL; break;
3127 case 5: os_sig = SIGTRAP; break;
3130 case 6: os_sig = SIGABRT; break;
3131 #elif defined(SIGIOT)
3132 case 6: os_sig = SIGIOT; break;
3135 case 7: os_sig = SIGEMT; break;
3138 case 8: os_sig = SIGFPE; break;
3141 case 9: os_sig = SIGKILL; break;
3144 case 10: os_sig = SIGBUS; break;
3147 case 11: os_sig = SIGSEGV; break;
3150 case 12: os_sig = SIGSYS; break;
3153 case 13: os_sig = SIGPIPE; break;
3156 case 14: os_sig = SIGALRM; break;
3159 case 15: os_sig = SIGTERM; break;
3162 case 16: os_sig = SIGURG; break;
3165 case 17: os_sig = SIGSTOP; break;
3168 case 18: os_sig = SIGTSTP; break;
3171 case 19: os_sig = SIGCONT; break;
3174 case 20: os_sig = SIGCHLD; break;
3175 #elif defined(SIGCLD)
3176 case 20: os_sig = SIGCLD; break;
3179 case 21: os_sig = SIGTTIN; break;
3182 case 22: os_sig = SIGTTOU; break;
3185 case 23: os_sig = SIGIO; break;
3186 #elif defined (SIGPOLL)
3187 case 23: os_sig = SIGPOLL; break;
3190 case 24: os_sig = SIGXCPU; break;
3193 case 25: os_sig = SIGXFSZ; break;
3196 case 26: os_sig = SIGVTALRM; break;
3199 case 27: os_sig = SIGPROF; break;
3202 case 28: os_sig = SIGWINCH; break;
3205 case 29: os_sig = SIGLOST; break;
3208 case 30: os_sig = SIGUSR1; break;
3211 case 31: os_sig = SIGUSR2; break;
3217 trace_output_void ();
3218 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3219 (*d10v_callback->flush_stdout) (d10v_callback);
3220 State.exception = SIGILL;
3224 RETVAL (kill (PARM1, PARM2));
3225 trace_output_16 (result);
3230 case TARGET_SYS_execve:
3231 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3232 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3233 (char **)MEMPTR (PARM3)));
3234 trace_output_16 (result);
3237 #ifdef TARGET_SYS_execv
3238 case TARGET_SYS_execv:
3239 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3240 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3241 trace_output_16 (result);
3245 case TARGET_SYS_pipe:
3250 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3252 RETVAL (pipe (host_fd));
3253 SW (buf, host_fd[0]);
3254 buf += sizeof(uint16);
3255 SW (buf, host_fd[1]);
3256 trace_output_16 (result);
3261 #ifdef TARGET_SYS_wait
3262 case TARGET_SYS_wait:
3265 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3266 RETVAL (wait (&status));
3269 trace_output_16 (result);
3275 case TARGET_SYS_getpid:
3276 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3278 trace_output_16 (result);
3281 case TARGET_SYS_kill:
3282 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3283 trace_output_void ();
3284 State.exception = PARM2;
3288 case TARGET_SYS_read:
3289 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3290 RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3292 trace_output_16 (result);
3295 case TARGET_SYS_write:
3296 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3298 RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3299 MEMPTR (PARM2), PARM3));
3301 RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3302 MEMPTR (PARM2), PARM3));
3303 trace_output_16 (result);
3306 case TARGET_SYS_lseek:
3307 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3308 RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3309 ((((unsigned long) PARM2) << 16)
3310 || (unsigned long) PARM3),
3312 trace_output_32 (result);
3315 case TARGET_SYS_close:
3316 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3317 RETVAL (d10v_callback->close (d10v_callback, PARM1));
3318 trace_output_16 (result);
3321 case TARGET_SYS_open:
3322 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3323 RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3324 trace_output_16 (result);
3327 case TARGET_SYS_exit:
3328 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3329 State.exception = SIG_D10V_EXIT;
3330 trace_output_void ();
3333 #ifdef TARGET_SYS_stat
3334 case TARGET_SYS_stat:
3335 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3336 /* stat system call */
3338 struct stat host_stat;
3341 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3345 /* The hard-coded offsets and sizes were determined by using
3346 * the D10V compiler on a test program that used struct stat.
3348 SW (buf, host_stat.st_dev);
3349 SW (buf+2, host_stat.st_ino);
3350 SW (buf+4, host_stat.st_mode);
3351 SW (buf+6, host_stat.st_nlink);
3352 SW (buf+8, host_stat.st_uid);
3353 SW (buf+10, host_stat.st_gid);
3354 SW (buf+12, host_stat.st_rdev);
3355 SLW (buf+16, host_stat.st_size);
3356 SLW (buf+20, host_stat.st_atime);
3357 SLW (buf+28, host_stat.st_mtime);
3358 SLW (buf+36, host_stat.st_ctime);
3360 trace_output_16 (result);
3364 case TARGET_SYS_chown:
3365 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3366 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3367 trace_output_16 (result);
3370 case TARGET_SYS_chmod:
3371 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3372 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3373 trace_output_16 (result);
3377 #ifdef TARGET_SYS_utime
3378 case TARGET_SYS_utime:
3379 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3380 /* Cast the second argument to void *, to avoid type mismatch
3381 if a prototype is present. */
3382 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3383 trace_output_16 (result);
3389 #ifdef TARGET_SYS_time
3390 case TARGET_SYS_time:
3391 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3392 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3393 trace_output_32 (result);
3399 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3401 if ((uint16) result == (uint16) -1)
3402 RETERR (d10v_callback->get_errno(d10v_callback));
3414 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3415 SET_PSW_F1 (PSW_F0);;
3416 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3417 trace_output_flag ();
3424 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3425 SET_PSW_F1 (PSW_F0);
3426 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3427 trace_output_flag ();
3434 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3436 trace_output_void ();
3444 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3445 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3446 SET_GPR (OP[0], tmp);
3447 trace_output_16 (tmp);
3455 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3456 tmp = (GPR (OP[1]) ^ OP[2]);
3457 SET_GPR (OP[0], tmp);
3458 trace_output_16 (tmp);