16 #include "targ-vals.h"
49 PSW_MASK = (PSW_SM_BIT
60 /* The following bits in the PSW _can't_ be set by instructions such
62 PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
66 move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
68 /* A MASK bit is set when the corresponding bit in the CR should
70 /* This assumes that (VAL & MASK) == 0 */
78 if ((mask & PSW_SM_BIT) == 0)
80 int new_psw_sm = (val & PSW_SM_BIT) != 0;
82 SET_HELD_SP (PSW_SM, GPR (SP_IDX));
83 if (PSW_SM != new_psw_sm)
85 SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
87 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
89 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
91 (*d10v_callback->printf_filtered)
93 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
95 State.exception = SIGILL;
98 /* keep an up-to-date psw around for tracing */
99 State.trace.psw = (State.trace.psw & mask) | val;
103 /* Just like PSW, mask things like DM out. */
116 /* only issue an update if the register is being changed */
117 if ((State.cregs[cr] & ~mask) != val)
118 SLOT_PEND_MASK (State.cregs[cr], mask, val);
123 static void trace_input_func (const char *name,
128 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
130 #ifndef SIZE_INSTRUCTION
131 #define SIZE_INSTRUCTION 8
134 #ifndef SIZE_OPERANDS
135 #define SIZE_OPERANDS 18
139 #define SIZE_VALUES 13
142 #ifndef SIZE_LOCATION
143 #define SIZE_LOCATION 20
150 #ifndef SIZE_LINE_NUMBER
151 #define SIZE_LINE_NUMBER 4
155 trace_input_func (const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
164 const char *filename;
165 const char *functionname;
166 unsigned int linenumber;
169 if ((d10v_debug & DEBUG_TRACE) == 0)
172 switch (State.ins_type)
175 case INS_UNKNOWN: type = " ?"; break;
176 case INS_LEFT: type = " L"; break;
177 case INS_RIGHT: type = " R"; break;
178 case INS_LEFT_PARALLEL: type = "*L"; break;
179 case INS_RIGHT_PARALLEL: type = "*R"; break;
180 case INS_LEFT_COND_TEST: type = "?L"; break;
181 case INS_RIGHT_COND_TEST: type = "?R"; break;
182 case INS_LEFT_COND_EXE: type = "&L"; break;
183 case INS_RIGHT_COND_EXE: type = "&R"; break;
184 case INS_LONG: type = " B"; break;
187 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
188 (*d10v_callback->printf_filtered) (d10v_callback,
190 SIZE_PC, (unsigned)PC,
192 SIZE_INSTRUCTION, name);
196 extern SIM_DESC trace_sd;
200 if (STATE_TEXT_SECTION (trace_sd)
201 && byte_pc >= STATE_TEXT_START (trace_sd)
202 && byte_pc < STATE_TEXT_END (trace_sd))
204 filename = (const char *)0;
205 functionname = (const char *)0;
207 if (bfd_find_nearest_line (STATE_PROG_BFD (trace_sd),
208 STATE_TEXT_SECTION (trace_sd),
209 (struct bfd_symbol **)0,
210 byte_pc - STATE_TEXT_START (trace_sd),
211 &filename, &functionname, &linenumber))
216 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
221 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
222 p += SIZE_LINE_NUMBER+2;
227 sprintf (p, "%s ", functionname);
232 char *q = strrchr (filename, '/');
233 sprintf (p, "%s ", (q) ? q+1 : filename);
242 (*d10v_callback->printf_filtered) (d10v_callback,
243 "0x%.*x %s: %-*.*s %-*s ",
244 SIZE_PC, (unsigned)PC,
246 SIZE_LOCATION, SIZE_LOCATION, buf,
247 SIZE_INSTRUCTION, name);
255 for (i = 0; i < 3; i++)
269 sprintf (p, "%sr%d", comma, OP[i]);
277 sprintf (p, "%scr%d", comma, OP[i]);
283 case OP_ACCUM_OUTPUT:
284 case OP_ACCUM_REVERSE:
285 sprintf (p, "%sa%d", comma, OP[i]);
291 sprintf (p, "%s%d", comma, OP[i]);
297 sprintf (p, "%s%d", comma, SEXT8(OP[i]));
303 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
309 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
315 sprintf (p, "%s@r%d", comma, OP[i]);
321 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
327 sprintf (p, "%s@%d", comma, OP[i]);
333 sprintf (p, "%s@r%d+", comma, OP[i]);
339 sprintf (p, "%s@r%d-", comma, OP[i]);
345 sprintf (p, "%s@-r%d", comma, OP[i]);
353 sprintf (p, "%sf0", comma);
356 sprintf (p, "%sf1", comma);
359 sprintf (p, "%sc", comma);
367 if ((d10v_debug & DEBUG_VALUES) == 0)
371 (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
376 (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
379 for (i = 0; i < 3; i++)
385 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
391 case OP_ACCUM_OUTPUT:
393 (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
401 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
402 (uint16) GPR (OP[i]));
406 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
410 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
411 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
416 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
417 (uint16) CREG (OP[i]));
421 case OP_ACCUM_REVERSE:
422 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
423 ((int)(ACC (OP[i]) >> 32) & 0xff),
424 ((unsigned long) ACC (OP[i])) & 0xffffffff);
428 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
433 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
434 (uint16)SEXT4(OP[i]));
438 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
439 (uint16)SEXT8(OP[i]));
443 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
444 (uint16)SEXT3(OP[i]));
449 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
453 (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
457 (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
463 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
465 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
466 (uint16)GPR (OP[i + 1]));
471 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
476 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
481 (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
489 (*d10v_callback->flush_stdout) (d10v_callback);
493 do_trace_output_flush (void)
495 (*d10v_callback->flush_stdout) (d10v_callback);
499 do_trace_output_finish (void)
501 (*d10v_callback->printf_filtered) (d10v_callback,
502 " F0=%d F1=%d C=%d\n",
503 (State.trace.psw & PSW_F0_BIT) != 0,
504 (State.trace.psw & PSW_F1_BIT) != 0,
505 (State.trace.psw & PSW_C_BIT) != 0);
506 (*d10v_callback->flush_stdout) (d10v_callback);
510 trace_output_40 (uint64 val)
512 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
514 (*d10v_callback->printf_filtered) (d10v_callback,
515 " :: %*s0x%.2x%.8lx",
518 ((int)(val >> 32) & 0xff),
519 ((unsigned long) val) & 0xffffffff);
520 do_trace_output_finish ();
525 trace_output_32 (uint32 val)
527 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
529 (*d10v_callback->printf_filtered) (d10v_callback,
534 do_trace_output_finish ();
539 trace_output_16 (uint16 val)
541 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
543 (*d10v_callback->printf_filtered) (d10v_callback,
548 do_trace_output_finish ();
553 trace_output_void (void)
555 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
557 (*d10v_callback->printf_filtered) (d10v_callback, "\n");
558 do_trace_output_flush ();
563 trace_output_flag (void)
565 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
567 (*d10v_callback->printf_filtered) (d10v_callback,
571 do_trace_output_finish ();
579 #define trace_input(NAME, IN1, IN2, IN3)
580 #define trace_output(RESULT)
588 trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
598 SET_GPR (OP[0], tmp);
599 trace_output_16 (tmp);
607 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
610 tmp = SEXT40 (ACC (OP[0]));
616 if (tmp > SEXT40(MAX32))
618 else if (tmp < SEXT40(MIN32))
621 tmp = (tmp & MASK40);
624 tmp = (tmp & MASK40);
629 tmp = (tmp & MASK40);
632 SET_ACC (OP[0], tmp);
633 trace_output_40 (tmp);
640 uint16 a = GPR (OP[0]);
641 uint16 b = GPR (OP[1]);
642 uint16 tmp = (a + b);
643 trace_input ("add", OP_REG, OP_REG, OP_VOID);
645 SET_GPR (OP[0], tmp);
646 trace_output_16 (tmp);
654 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
656 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID);
659 if (tmp > SEXT40(MAX32))
661 else if (tmp < SEXT40(MIN32))
664 tmp = (tmp & MASK40);
667 tmp = (tmp & MASK40);
668 SET_ACC (OP[0], tmp);
669 trace_output_40 (tmp);
677 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
679 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID);
682 if (tmp > SEXT40(MAX32))
684 else if (tmp < SEXT40(MIN32))
687 tmp = (tmp & MASK40);
690 tmp = (tmp & MASK40);
691 SET_ACC (OP[0], tmp);
692 trace_output_40 (tmp);
700 uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
701 uint32 b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
702 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
705 SET_GPR (OP[0] + 0, (tmp >> 16));
706 SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
707 trace_output_32 (tmp);
714 uint16 a = GPR (OP[1]);
716 uint16 tmp = (a + b);
717 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
719 SET_GPR (OP[0], tmp);
720 trace_output_16 (tmp);
728 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
730 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
731 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
732 SET_GPR (OP[0] + 1, (tmp & 0xffff));
733 trace_output_32 (tmp);
741 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
743 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
744 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
745 SET_GPR (OP[0] + 1, tmp & 0xffff);
746 trace_output_32 (tmp);
756 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
757 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
758 if (tmp > SEXT40(MAX32))
763 else if (tmp < SEXT40(MIN32))
772 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
773 SET_GPR (OP[0] + 1, (tmp & 0xffff));
774 trace_output_32 (tmp);
784 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
785 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
786 if (tmp > SEXT40(MAX32))
791 else if (tmp < SEXT40(MIN32))
800 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
801 SET_GPR (OP[0] + 1, (tmp & 0xffff));
802 trace_output_32 (tmp);
809 uint16 a = GPR (OP[0]);
816 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
818 SET_GPR (OP[0], tmp);
819 trace_output_16 (tmp);
826 uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
827 trace_input ("and", OP_REG, OP_REG, OP_VOID);
828 SET_GPR (OP[0], tmp);
829 trace_output_16 (tmp);
836 uint16 tmp = GPR (OP[1]) & OP[2];
837 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
838 SET_GPR (OP[0], tmp);
839 trace_output_16 (tmp);
847 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
848 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
849 SET_GPR (OP[0], tmp);
850 trace_output_16 (tmp);
857 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
858 SET_GPR (13, PC + 1);
859 JMP( PC + SEXT8 (OP[0]));
860 trace_output_void ();
867 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
868 SET_GPR (13, (PC + 1));
870 trace_output_void ();
878 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
879 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
880 SET_GPR (OP[0], tmp);
881 trace_output_16 (tmp);
888 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
889 JMP (PC + SEXT8 (OP[0]));
890 trace_output_void ();
897 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
899 trace_output_void ();
906 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
908 JMP (PC + SEXT8 (OP[0]));
909 trace_output_flag ();
916 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
919 trace_output_flag ();
926 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
928 JMP (PC + SEXT8 (OP[0]));
929 trace_output_flag ();
936 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
939 trace_output_flag ();
947 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
948 tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
949 SET_GPR (OP[0], tmp);
950 trace_output_16 (tmp);
957 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
959 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
960 trace_output_flag ();
967 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
976 trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
978 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
979 trace_output_flag ();
986 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
988 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
989 trace_output_flag ();
996 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
998 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
999 trace_output_flag ();
1006 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
1007 SET_PSW_F1 (PSW_F0);
1008 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
1009 trace_output_flag ();
1016 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1017 SET_PSW_F1 (PSW_F0);
1018 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
1019 trace_output_flag ();
1026 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1027 SET_PSW_F1 (PSW_F0);
1028 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
1029 trace_output_flag ();
1036 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
1037 SET_PSW_F1 (PSW_F0);
1038 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
1039 trace_output_flag ();
1046 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
1047 SET_PSW_F1 (PSW_F0);
1048 SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
1049 trace_output_flag ();
1056 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
1057 SET_PSW_F1 (PSW_F0);
1058 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
1059 trace_output_flag ();
1066 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
1067 SET_PSW_F1 (PSW_F0);
1068 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
1069 trace_output_flag ();
1078 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1082 else if (OP[1] == 1)
1091 trace_output_flag ();
1100 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
1104 else if (OP[1] == 1)
1113 trace_output_flag ();
1120 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1122 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1123 The conditional below is for either of the instruction pairs
1124 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1125 where the dbt instruction should be interpreted.
1127 The module `sim-break' provides a more effective mechanism for
1128 detecting GDB planted breakpoints. The code below may,
1129 eventually, be changed to use that mechanism. */
1131 if (State.ins_type == INS_LEFT
1132 || State.ins_type == INS_RIGHT)
1134 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
1137 SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
1138 JMP (DBT_VECTOR_START);
1139 trace_output_void ();
1143 State.exception = SIGTRAP;
1151 uint16 foo, tmp, tmpf;
1155 trace_input ("divs", OP_DREG, OP_REG, OP_VOID);
1156 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15);
1157 tmp = (int16)foo - (int16)(GPR (OP[1]));
1158 tmpf = (foo >= GPR (OP[1])) ? 1 : 0;
1159 hi = ((tmpf == 1) ? tmp : foo);
1160 lo = ((GPR (OP[0] + 1) << 1) | tmpf);
1161 SET_GPR (OP[0] + 0, hi);
1162 SET_GPR (OP[0] + 1, lo);
1163 trace_output_32 (((uint32) hi << 16) | lo);
1170 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
1171 State.exe = (PSW_F0 == 0);
1172 trace_output_flag ();
1179 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
1180 State.exe = (PSW_F0 != 0);
1181 trace_output_flag ();
1188 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
1189 State.exe = (PSW_F1 == 0);
1190 trace_output_flag ();
1197 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
1198 State.exe = (PSW_F1 != 0);
1199 trace_output_flag ();
1206 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
1207 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
1208 trace_output_flag ();
1215 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
1216 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
1217 trace_output_flag ();
1224 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
1225 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
1226 trace_output_flag ();
1233 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
1234 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
1235 trace_output_flag ();
1245 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID);
1246 if (((int16)GPR (OP[1])) >= 0)
1247 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1);
1249 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
1256 SET_GPR (OP[0], (i - 1));
1257 trace_output_16 (i - 1);
1262 SET_GPR (OP[0], 16);
1263 trace_output_16 (16);
1273 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
1274 tmp = SEXT40(ACC (OP[1]));
1276 tmp = ~tmp & MASK40;
1278 foo = 0x4000000000LL;
1283 SET_GPR (OP[0], i - 9);
1284 trace_output_16 (i - 9);
1289 SET_GPR (OP[0], 16);
1290 trace_output_16 (16);
1297 trace_input ("jl", OP_REG, OP_R0, OP_R1);
1298 SET_GPR (13, PC + 1);
1300 trace_output_void ();
1307 trace_input ("jmp", OP_REG,
1308 (OP[0] == 13) ? OP_R0 : OP_VOID,
1309 (OP[0] == 13) ? OP_R1 : OP_VOID);
1312 trace_output_void ();
1320 uint16 addr = OP[1] + GPR (OP[2]);
1321 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1324 State.exception = SIG_D10V_BUS;
1325 State.pc_changed = 1; /* Don't increment the PC. */
1326 trace_output_void ();
1330 SET_GPR (OP[0], tmp);
1331 trace_output_16 (tmp);
1339 uint16 addr = GPR (OP[1]);
1340 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1343 State.exception = SIG_D10V_BUS;
1344 State.pc_changed = 1; /* Don't increment the PC. */
1345 trace_output_void ();
1349 SET_GPR (OP[0], tmp);
1351 INC_ADDR (OP[1], -2);
1352 trace_output_16 (tmp);
1360 uint16 addr = GPR (OP[1]);
1361 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1364 State.exception = SIG_D10V_BUS;
1365 State.pc_changed = 1; /* Don't increment the PC. */
1366 trace_output_void ();
1370 SET_GPR (OP[0], tmp);
1372 INC_ADDR (OP[1], 2);
1373 trace_output_16 (tmp);
1381 uint16 addr = GPR (OP[1]);
1382 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1385 State.exception = SIG_D10V_BUS;
1386 State.pc_changed = 1; /* Don't increment the PC. */
1387 trace_output_void ();
1391 SET_GPR (OP[0], tmp);
1392 trace_output_16 (tmp);
1400 uint16 addr = OP[1];
1401 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1404 State.exception = SIG_D10V_BUS;
1405 State.pc_changed = 1; /* Don't increment the PC. */
1406 trace_output_void ();
1410 SET_GPR (OP[0], tmp);
1411 trace_output_16 (tmp);
1419 uint16 addr = OP[1] + GPR (OP[2]);
1420 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1423 State.exception = SIG_D10V_BUS;
1424 State.pc_changed = 1; /* Don't increment the PC. */
1425 trace_output_void ();
1429 SET_GPR32 (OP[0], tmp);
1430 trace_output_32 (tmp);
1437 uint16 addr = GPR (OP[1]);
1439 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
1442 State.exception = SIG_D10V_BUS;
1443 State.pc_changed = 1; /* Don't increment the PC. */
1444 trace_output_void ();
1448 SET_GPR32 (OP[0], tmp);
1449 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1450 INC_ADDR (OP[1], -4);
1451 trace_output_32 (tmp);
1459 uint16 addr = GPR (OP[1]);
1460 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
1463 State.exception = SIG_D10V_BUS;
1464 State.pc_changed = 1; /* Don't increment the PC. */
1465 trace_output_void ();
1469 SET_GPR32 (OP[0], tmp);
1470 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
1471 INC_ADDR (OP[1], 4);
1472 trace_output_32 (tmp);
1479 uint16 addr = GPR (OP[1]);
1481 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1484 State.exception = SIG_D10V_BUS;
1485 State.pc_changed = 1; /* Don't increment the PC. */
1486 trace_output_void ();
1490 SET_GPR32 (OP[0], tmp);
1491 trace_output_32 (tmp);
1499 uint16 addr = OP[1];
1500 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
1503 State.exception = SIG_D10V_BUS;
1504 State.pc_changed = 1; /* Don't increment the PC. */
1505 trace_output_void ();
1509 SET_GPR32 (OP[0], tmp);
1510 trace_output_32 (tmp);
1518 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1519 tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
1520 SET_GPR (OP[0], tmp);
1521 trace_output_16 (tmp);
1529 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1530 tmp = SEXT8 (RB (GPR (OP[1])));
1531 SET_GPR (OP[0], tmp);
1532 trace_output_16 (tmp);
1540 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
1541 tmp = SEXT4 (OP[1]);
1542 SET_GPR (OP[0], tmp);
1543 trace_output_16 (tmp);
1551 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
1553 SET_GPR (OP[0], tmp);
1554 trace_output_16 (tmp);
1562 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
1563 tmp = RB (OP[1] + GPR (OP[2]));
1564 SET_GPR (OP[0], tmp);
1565 trace_output_16 (tmp);
1573 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
1574 tmp = RB (GPR (OP[1]));
1575 SET_GPR (OP[0], tmp);
1576 trace_output_16 (tmp);
1585 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG);
1586 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1589 tmp = SEXT40( (tmp << 1) & MASK40);
1591 if (PSW_ST && tmp > SEXT40(MAX32))
1594 tmp += SEXT40 (ACC (OP[0]));
1597 if (tmp > SEXT40(MAX32))
1599 else if (tmp < SEXT40(MIN32))
1602 tmp = (tmp & MASK40);
1605 tmp = (tmp & MASK40);
1606 SET_ACC (OP[0], tmp);
1607 trace_output_40 (tmp);
1616 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG);
1617 tmp = SEXT40 ((int16) GPR (OP[1]) * GPR (OP[2]));
1619 tmp = SEXT40 ((tmp << 1) & MASK40);
1620 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
1621 SET_ACC (OP[0], tmp);
1622 trace_output_40 (tmp);
1633 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
1634 src1 = (uint16) GPR (OP[1]);
1635 src2 = (uint16) GPR (OP[2]);
1639 tmp = ((ACC (OP[0]) + tmp) & MASK40);
1640 SET_ACC (OP[0], tmp);
1641 trace_output_40 (tmp);
1649 trace_input ("max", OP_REG, OP_REG, OP_VOID);
1650 SET_PSW_F1 (PSW_F0);
1651 if ((int16) GPR (OP[1]) > (int16)GPR (OP[0]))
1661 SET_GPR (OP[0], tmp);
1662 trace_output_16 (tmp);
1671 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID);
1672 SET_PSW_F1 (PSW_F0);
1673 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1674 if (tmp > SEXT40 (ACC (OP[0])))
1676 tmp = (tmp & MASK40);
1684 SET_ACC (OP[0], tmp);
1685 trace_output_40 (tmp);
1693 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
1694 SET_PSW_F1 (PSW_F0);
1695 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0])))
1705 SET_ACC (OP[0], tmp);
1706 trace_output_40 (tmp);
1715 trace_input ("min", OP_REG, OP_REG, OP_VOID);
1716 SET_PSW_F1 (PSW_F0);
1717 if ((int16)GPR (OP[1]) < (int16)GPR (OP[0]))
1727 SET_GPR (OP[0], tmp);
1728 trace_output_16 (tmp);
1737 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID);
1738 SET_PSW_F1 (PSW_F0);
1739 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1);
1740 if (tmp < SEXT40(ACC (OP[0])))
1742 tmp = (tmp & MASK40);
1750 SET_ACC (OP[0], tmp);
1751 trace_output_40 (tmp);
1759 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
1760 SET_PSW_F1 (PSW_F0);
1761 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0])))
1771 SET_ACC (OP[0], tmp);
1772 trace_output_40 (tmp);
1781 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG);
1782 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1785 tmp = SEXT40 ((tmp << 1) & MASK40);
1787 if (PSW_ST && tmp > SEXT40(MAX32))
1790 tmp = SEXT40(ACC (OP[0])) - tmp;
1793 if (tmp > SEXT40(MAX32))
1795 else if (tmp < SEXT40(MIN32))
1798 tmp = (tmp & MASK40);
1802 tmp = (tmp & MASK40);
1804 SET_ACC (OP[0], tmp);
1805 trace_output_40 (tmp);
1814 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG);
1815 tmp = SEXT40 ((int16)GPR (OP[1]) * GPR (OP[2]));
1817 tmp = SEXT40( (tmp << 1) & MASK40);
1818 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
1819 SET_ACC (OP[0], tmp);
1820 trace_output_40 (tmp);
1831 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
1832 src1 = (uint16) GPR (OP[1]);
1833 src2 = (uint16) GPR (OP[2]);
1837 tmp = ((ACC (OP[0]) - tmp) & MASK40);
1838 SET_ACC (OP[0], tmp);
1839 trace_output_40 (tmp);
1847 trace_input ("mul", OP_REG, OP_REG, OP_VOID);
1848 tmp = GPR (OP[0]) * GPR (OP[1]);
1849 SET_GPR (OP[0], tmp);
1850 trace_output_16 (tmp);
1859 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1860 tmp = SEXT40 ((int16)(GPR (OP[1])) * (int16)(GPR (OP[2])));
1863 tmp = SEXT40 ((tmp << 1) & MASK40);
1865 if (PSW_ST && tmp > SEXT40(MAX32))
1868 tmp = (tmp & MASK40);
1869 SET_ACC (OP[0], tmp);
1870 trace_output_40 (tmp);
1879 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1880 tmp = SEXT40 ((int16)(GPR (OP[1])) * GPR (OP[2]));
1884 tmp = (tmp & MASK40);
1885 SET_ACC (OP[0], tmp);
1886 trace_output_40 (tmp);
1897 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
1898 src1 = (uint16) GPR (OP[1]);
1899 src2 = (uint16) GPR (OP[2]);
1903 tmp = (tmp & MASK40);
1904 SET_ACC (OP[0], tmp);
1905 trace_output_40 (tmp);
1913 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
1915 SET_GPR (OP[0], tmp);
1916 trace_output_16 (tmp);
1924 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
1925 tmp = GPR32 (OP[1]);
1926 SET_GPR32 (OP[0], tmp);
1927 trace_output_32 (tmp);
1935 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
1937 SET_GPR32 (OP[0], tmp);
1938 trace_output_32 (tmp);
1946 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
1947 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
1948 SET_ACC (OP[1], tmp);
1949 trace_output_40 (tmp);
1957 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
1959 SET_ACC (OP[0], tmp);
1960 trace_output_40 (tmp);
1968 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
1969 tmp = SEXT8 (GPR (OP[1]) & 0xff);
1970 SET_GPR (OP[0], tmp);
1971 trace_output_16 (tmp);
1979 trace_input ("mvf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
1983 SET_GPR (OP[0], tmp);
1987 trace_output_16 (tmp);
1995 trace_input ("mvf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
1999 SET_GPR (OP[0], tmp);
2003 trace_output_16 (tmp);
2011 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2012 tmp = ((ACC (OP[1]) >> 32) & 0xff);
2013 SET_GPR (OP[0], tmp);
2014 trace_output_16 (tmp);
2022 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2023 tmp = (ACC (OP[1]) >> 16);
2024 SET_GPR (OP[0], tmp);
2025 trace_output_16 (tmp);
2033 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2035 SET_GPR (OP[0], tmp);
2036 trace_output_16 (tmp);
2044 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
2046 SET_GPR (OP[0], tmp);
2047 trace_output_16 (tmp);
2055 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
2056 tmp = ((ACC (OP[1]) & MASK32)
2057 | ((int64)(GPR (OP[0]) & 0xff) << 32));
2058 SET_ACC (OP[1], tmp);
2059 trace_output_40 (tmp);
2067 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
2068 tmp = ACC (OP[1]) & 0xffff;
2069 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
2070 SET_ACC (OP[1], tmp);
2071 trace_output_40 (tmp);
2079 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
2080 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
2081 SET_ACC (OP[1], tmp);
2082 trace_output_40 (tmp);
2090 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
2092 tmp = SET_CREG (OP[1], tmp);
2093 trace_output_16 (tmp);
2101 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
2102 tmp = (GPR (OP[1]) & 0xff);
2103 SET_GPR (OP[0], tmp);
2104 trace_output_16 (tmp);
2112 trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
2113 tmp = - GPR (OP[0]);
2114 SET_GPR (OP[0], tmp);
2115 trace_output_16 (tmp);
2124 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID);
2125 tmp = -SEXT40(ACC (OP[0]));
2128 if (tmp > SEXT40(MAX32))
2130 else if (tmp < SEXT40(MIN32))
2133 tmp = (tmp & MASK40);
2136 tmp = (tmp & MASK40);
2137 SET_ACC (OP[0], tmp);
2138 trace_output_40 (tmp);
2146 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
2148 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
2149 switch (State.ins_type)
2152 ins_type_counters[ (int)INS_UNKNOWN ]++;
2155 case INS_LEFT_PARALLEL:
2156 /* Don't count a parallel op that includes a NOP as a true parallel op */
2157 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
2158 ins_type_counters[ (int)INS_RIGHT ]++;
2159 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2163 case INS_LEFT_COND_EXE:
2164 ins_type_counters[ (int)INS_LEFT_NOPS ]++;
2167 case INS_RIGHT_PARALLEL:
2168 /* Don't count a parallel op that includes a NOP as a true parallel op */
2169 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
2170 ins_type_counters[ (int)INS_LEFT ]++;
2171 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2175 case INS_RIGHT_COND_EXE:
2176 ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
2180 trace_output_void ();
2188 trace_input ("not", OP_REG, OP_VOID, OP_VOID);
2190 SET_GPR (OP[0], tmp);
2191 trace_output_16 (tmp);
2199 trace_input ("or", OP_REG, OP_REG, OP_VOID);
2200 tmp = (GPR (OP[0]) | GPR (OP[1]));
2201 SET_GPR (OP[0], tmp);
2202 trace_output_16 (tmp);
2210 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
2211 tmp = (GPR (OP[1]) | OP[2]);
2212 SET_GPR (OP[0], tmp);
2213 trace_output_16 (tmp);
2221 int shift = SEXT3 (OP[2]);
2223 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2226 (*d10v_callback->printf_filtered) (d10v_callback,
2227 "ERROR at PC 0x%x: instruction only valid for A0\n",
2229 State.exception = SIGILL;
2232 SET_PSW_F1 (PSW_F0);
2233 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2239 tmp >>= 16; /* look at bits 0:43 */
2240 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2245 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2254 SET_GPR32 (OP[0], tmp);
2255 trace_output_32 (tmp);
2263 int shift = SEXT3 (OP[2]);
2265 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
2266 SET_PSW_F1 (PSW_F0);
2268 tmp = SEXT40 (ACC (OP[1])) << shift;
2270 tmp = SEXT40 (ACC (OP[1])) >> -shift;
2273 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
2278 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
2288 SET_GPR (OP[0], tmp);
2289 trace_output_16 (tmp);
2296 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
2298 SET_RPT_E (PC + OP[1]);
2299 SET_RPT_C (GPR (OP[0]));
2301 if (GPR (OP[0]) == 0)
2303 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
2304 State.exception = SIGILL;
2308 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
2309 State.exception = SIGILL;
2311 trace_output_void ();
2318 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
2320 SET_RPT_E (PC + OP[1]);
2325 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
2326 State.exception = SIGILL;
2330 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
2331 State.exception = SIGILL;
2333 trace_output_void ();
2340 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
2341 SET_CREG (PSW_CR, DPSW);
2343 trace_output_void ();
2350 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
2351 SET_CREG (PSW_CR, BPSW);
2353 trace_output_void ();
2361 trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2363 tmp = SEXT40(ACC (OP[1]));
2365 SET_PSW_F1 (PSW_F0);
2367 if (tmp > SEXT40(MAX32))
2372 else if (tmp < SEXT40(MIN32))
2379 tmp = (tmp & MASK32);
2383 SET_GPR32 (OP[0], tmp);
2385 trace_output_40 (tmp);
2394 trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
2396 tmp = SEXT40(ACC (OP[1]));
2398 SET_PSW_F1 (PSW_F0);
2400 if (tmp > SEXT40(MAX32))
2405 else if (tmp < SEXT40(MIN32))
2416 SET_GPR (OP[0], tmp);
2418 trace_output_16 (OP[0]);
2427 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID);
2428 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16);
2431 if (tmp > SEXT40(MAX32))
2433 else if (tmp < SEXT40(MIN32))
2436 tmp = (tmp & MASK40);
2439 tmp = (tmp & MASK40);
2440 SET_ACC (OP[0], tmp);
2441 trace_output_40 (tmp);
2449 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2450 tmp = ((PSW_F0 == 0) ? 1 : 0);
2451 SET_GPR (OP[0], tmp);
2452 trace_output_16 (tmp);
2460 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
2461 tmp = ((PSW_F0 == 1) ? 1 : 0);
2462 SET_GPR (OP[0], tmp);
2463 trace_output_16 (tmp);
2473 trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
2475 reg = SEXT16 (GPR (OP[1]));
2477 if (reg >= 17 || reg <= -17)
2479 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", reg);
2480 State.exception = SIGILL;
2484 tmp = SEXT40 (ACC (OP[0]));
2486 if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
2488 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
2489 State.exception = SIGILL;
2493 if (reg >= 0 && reg <= 16)
2495 tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
2498 if (tmp > SEXT40(MAX32))
2500 else if (tmp < SEXT40(MIN32))
2503 tmp = (tmp & MASK40);
2506 tmp = (tmp & MASK40);
2510 tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
2513 SET_ACC(OP[0], tmp);
2515 trace_output_40(tmp);
2522 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
2524 trace_output_void ();
2532 trace_input ("sll", OP_REG, OP_REG, OP_VOID);
2533 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
2534 SET_GPR (OP[0], tmp);
2535 trace_output_16 (tmp);
2543 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
2544 if ((GPR (OP[1]) & 31) <= 16)
2545 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
2548 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2549 State.exception = SIGILL;
2555 if (tmp > SEXT40(MAX32))
2557 else if (tmp < SEXT40(MIN32))
2560 tmp = (tmp & MASK40);
2563 tmp = (tmp & MASK40);
2564 SET_ACC (OP[0], tmp);
2565 trace_output_40 (tmp);
2573 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
2574 tmp = (GPR (OP[0]) << OP[1]);
2575 SET_GPR (OP[0], tmp);
2576 trace_output_16 (tmp);
2588 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2589 tmp = SEXT40(ACC (OP[0])) << OP[1];
2593 if (tmp > SEXT40(MAX32))
2595 else if (tmp < SEXT40(MIN32))
2598 tmp = (tmp & MASK40);
2601 tmp = (tmp & MASK40);
2602 SET_ACC (OP[0], tmp);
2603 trace_output_40 (tmp);
2611 trace_input ("slx", OP_REG, OP_VOID, OP_VOID);
2612 tmp = ((GPR (OP[0]) << 1) | PSW_F0);
2613 SET_GPR (OP[0], tmp);
2614 trace_output_16 (tmp);
2622 trace_input ("sra", OP_REG, OP_REG, OP_VOID);
2623 tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
2624 SET_GPR (OP[0], tmp);
2625 trace_output_16 (tmp);
2632 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
2633 if ((GPR (OP[1]) & 31) <= 16)
2635 int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
2636 SET_ACC (OP[0], tmp);
2637 trace_output_40 (tmp);
2641 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2642 State.exception = SIGILL;
2652 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
2653 tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
2654 SET_GPR (OP[0], tmp);
2655 trace_output_16 (tmp);
2666 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2667 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
2668 SET_ACC (OP[0], tmp);
2669 trace_output_40 (tmp);
2677 trace_input ("srl", OP_REG, OP_REG, OP_VOID);
2678 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
2679 SET_GPR (OP[0], tmp);
2680 trace_output_16 (tmp);
2687 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
2688 if ((GPR (OP[1]) & 31) <= 16)
2690 int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
2691 SET_ACC (OP[0], tmp);
2692 trace_output_40 (tmp);
2696 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
2697 State.exception = SIGILL;
2708 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
2709 tmp = (GPR (OP[0]) >> OP[1]);
2710 SET_GPR (OP[0], tmp);
2711 trace_output_16 (tmp);
2722 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
2723 tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
2724 SET_ACC (OP[0], tmp);
2725 trace_output_40 (tmp);
2733 trace_input ("srx", OP_REG, OP_VOID, OP_VOID);
2735 tmp = ((GPR (OP[0]) >> 1) | tmp);
2736 SET_GPR (OP[0], tmp);
2737 trace_output_16 (tmp);
2744 uint16 addr = OP[1] + GPR (OP[2]);
2745 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
2748 State.exception = SIG_D10V_BUS;
2749 State.pc_changed = 1; /* Don't increment the PC. */
2750 trace_output_void ();
2753 SW (addr, GPR (OP[0]));
2754 trace_output_void ();
2761 uint16 addr = GPR (OP[1]);
2762 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
2765 State.exception = SIG_D10V_BUS;
2766 State.pc_changed = 1; /* Don't increment the PC. */
2767 trace_output_void ();
2770 SW (addr, GPR (OP[0]));
2771 trace_output_void ();
2779 uint16 addr = GPR (OP[1]) - 2;
2780 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
2783 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2784 State.exception = SIGILL;
2789 State.exception = SIG_D10V_BUS;
2790 State.pc_changed = 1; /* Don't increment the PC. */
2791 trace_output_void ();
2794 SW (addr, GPR (OP[0]));
2795 SET_GPR (OP[1], addr);
2796 trace_output_void ();
2803 uint16 addr = GPR (OP[1]);
2804 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
2807 State.exception = SIG_D10V_BUS;
2808 State.pc_changed = 1; /* Don't increment the PC. */
2809 trace_output_void ();
2812 SW (addr, GPR (OP[0]));
2813 INC_ADDR (OP[1], 2);
2814 trace_output_void ();
2821 uint16 addr = GPR (OP[1]);
2822 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
2825 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2826 State.exception = SIGILL;
2831 State.exception = SIG_D10V_BUS;
2832 State.pc_changed = 1; /* Don't increment the PC. */
2833 trace_output_void ();
2836 SW (addr, GPR (OP[0]));
2837 INC_ADDR (OP[1], -2);
2838 trace_output_void ();
2845 uint16 addr = OP[1];
2846 trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
2849 State.exception = SIG_D10V_BUS;
2850 State.pc_changed = 1; /* Don't increment the PC. */
2851 trace_output_void ();
2854 SW (addr, GPR (OP[0]));
2855 trace_output_void ();
2862 uint16 addr = GPR (OP[2])+ OP[1];
2863 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
2866 State.exception = SIG_D10V_BUS;
2867 State.pc_changed = 1; /* Don't increment the PC. */
2868 trace_output_void ();
2871 SW (addr + 0, GPR (OP[0] + 0));
2872 SW (addr + 2, GPR (OP[0] + 1));
2873 trace_output_void ();
2880 uint16 addr = GPR (OP[1]);
2881 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
2884 State.exception = SIG_D10V_BUS;
2885 State.pc_changed = 1; /* Don't increment the PC. */
2886 trace_output_void ();
2889 SW (addr + 0, GPR (OP[0] + 0));
2890 SW (addr + 2, GPR (OP[0] + 1));
2891 trace_output_void ();
2898 uint16 addr = GPR (OP[1]) - 4;
2899 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
2902 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2903 State.exception = SIGILL;
2908 State.exception = SIG_D10V_BUS;
2909 State.pc_changed = 1; /* Don't increment the PC. */
2910 trace_output_void ();
2913 SW (addr + 0, GPR (OP[0] + 0));
2914 SW (addr + 2, GPR (OP[0] + 1));
2915 SET_GPR (OP[1], addr);
2916 trace_output_void ();
2923 uint16 addr = GPR (OP[1]);
2924 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
2927 State.exception = SIG_D10V_BUS;
2928 State.pc_changed = 1; /* Don't increment the PC. */
2929 trace_output_void ();
2932 SW (addr + 0, GPR (OP[0] + 0));
2933 SW (addr + 2, GPR (OP[0] + 1));
2934 INC_ADDR (OP[1], 4);
2935 trace_output_void ();
2942 uint16 addr = GPR (OP[1]);
2943 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
2946 (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
2947 State.exception = SIGILL;
2952 State.exception = SIG_D10V_BUS;
2953 State.pc_changed = 1; /* Don't increment the PC. */
2954 trace_output_void ();
2957 SW (addr + 0, GPR (OP[0] + 0));
2958 SW (addr + 2, GPR (OP[0] + 1));
2959 INC_ADDR (OP[1], -4);
2960 trace_output_void ();
2967 uint16 addr = OP[1];
2968 trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
2971 State.exception = SIG_D10V_BUS;
2972 State.pc_changed = 1; /* Don't increment the PC. */
2973 trace_output_void ();
2976 SW (addr + 0, GPR (OP[0] + 0));
2977 SW (addr + 2, GPR (OP[0] + 1));
2978 trace_output_void ();
2985 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
2986 SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
2987 trace_output_void ();
2994 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
2995 SB (GPR (OP[1]), GPR (OP[0]));
2996 trace_output_void ();
3003 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
3004 State.exception = SIG_D10V_STOP;
3005 trace_output_void ();
3012 uint16 a = GPR (OP[0]);
3013 uint16 b = GPR (OP[1]);
3014 uint16 tmp = (a - b);
3015 trace_input ("sub", OP_REG, OP_REG, OP_VOID);
3016 /* see ../common/sim-alu.h for a more extensive discussion on how to
3017 compute the carry/overflow bits. */
3019 SET_GPR (OP[0], tmp);
3020 trace_output_16 (tmp);
3029 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID);
3030 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
3033 if (tmp > SEXT40(MAX32))
3035 else if (tmp < SEXT40(MIN32))
3038 tmp = (tmp & MASK40);
3041 tmp = (tmp & MASK40);
3042 SET_ACC (OP[0], tmp);
3044 trace_output_40 (tmp);
3054 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID);
3055 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1]));
3058 if (tmp > SEXT40(MAX32))
3060 else if (tmp < SEXT40(MIN32))
3063 tmp = (tmp & MASK40);
3066 tmp = (tmp & MASK40);
3067 SET_ACC (OP[0], tmp);
3069 trace_output_40 (tmp);
3078 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
3079 a = (uint32)((GPR (OP[0]) << 16) | GPR (OP[0] + 1));
3080 b = (uint32)((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
3081 /* see ../common/sim-alu.h for a more extensive discussion on how to
3082 compute the carry/overflow bits */
3085 SET_GPR32 (OP[0], tmp);
3086 trace_output_32 (tmp);
3095 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3096 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
3097 SET_GPR32 (OP[0], tmp);
3098 trace_output_32 (tmp);
3107 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3108 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
3109 SET_GPR32 (OP[0], tmp);
3110 trace_output_32 (tmp);
3119 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
3120 SET_PSW_F1 (PSW_F0);
3121 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2]));
3122 if (tmp > SEXT40(MAX32))
3127 else if (tmp < SEXT40(MIN32))
3136 SET_GPR32 (OP[0], tmp);
3137 trace_output_32 (tmp);
3146 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
3147 SET_PSW_F1 (PSW_F0);
3148 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2]));
3149 if (tmp > SEXT40(MAX32))
3154 else if (tmp < SEXT40(MIN32))
3163 SET_GPR32 (OP[0], tmp);
3164 trace_output_32 (tmp);
3175 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
3176 /* see ../common/sim-alu.h for a more extensive discussion on how to
3177 compute the carry/overflow bits. */
3178 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3179 tmp = ((unsigned)(unsigned16) GPR (OP[0])
3180 + (unsigned)(unsigned16) ( - OP[1]));
3181 SET_PSW_C (tmp >= (1 << 16));
3182 SET_GPR (OP[0], tmp);
3183 trace_output_16 (tmp);
3190 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
3191 trace_output_void ();
3196 #if (DEBUG & DEBUG_TRAP) == 0
3198 uint16 vec = OP[0] + TRAP_VECTOR_START;
3201 SET_PSW (PSW & PSW_SM_BIT);
3205 #else /* if debugging use trap to print registers */
3208 static int first_time = 1;
3213 (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
3214 for (i = 0; i < 16; i++)
3215 (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
3216 (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
3219 (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
3221 for (i = 0; i < 16; i++)
3222 (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
3224 for (i = 0; i < 2; i++)
3225 (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
3226 ((int)(ACC (i) >> 32) & 0xff),
3227 ((unsigned long) ACC (i)) & 0xffffffff);
3229 (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
3230 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
3231 (*d10v_callback->flush_stdout) (d10v_callback);
3235 case 15: /* new system call trap */
3236 /* Trap 15 is used for simulating low-level I/O */
3238 unsigned32 result = 0;
3241 /* Registers passed to trap 0 */
3243 #define FUNC GPR (4) /* function number */
3244 #define PARM1 GPR (0) /* optional parm 1 */
3245 #define PARM2 GPR (1) /* optional parm 2 */
3246 #define PARM3 GPR (2) /* optional parm 3 */
3247 #define PARM4 GPR (3) /* optional parm 3 */
3249 /* Registers set by trap 0 */
3251 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3252 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3253 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3255 /* Turn a pointer in a register into a pointer into real memory. */
3257 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3261 #if !defined(__GO32__) && !defined(_WIN32)
3262 case TARGET_SYS_fork:
3263 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
3265 trace_output_16 (result);
3269 case TARGET_SYS_getpid:
3270 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3272 trace_output_16 (result);
3275 case TARGET_SYS_kill:
3276 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
3277 if (PARM1 == getpid ())
3279 trace_output_void ();
3280 State.exception = PARM2;
3288 case 1: os_sig = SIGHUP; break;
3291 case 2: os_sig = SIGINT; break;
3294 case 3: os_sig = SIGQUIT; break;
3297 case 4: os_sig = SIGILL; break;
3300 case 5: os_sig = SIGTRAP; break;
3303 case 6: os_sig = SIGABRT; break;
3304 #elif defined(SIGIOT)
3305 case 6: os_sig = SIGIOT; break;
3308 case 7: os_sig = SIGEMT; break;
3311 case 8: os_sig = SIGFPE; break;
3314 case 9: os_sig = SIGKILL; break;
3317 case 10: os_sig = SIGBUS; break;
3320 case 11: os_sig = SIGSEGV; break;
3323 case 12: os_sig = SIGSYS; break;
3326 case 13: os_sig = SIGPIPE; break;
3329 case 14: os_sig = SIGALRM; break;
3332 case 15: os_sig = SIGTERM; break;
3335 case 16: os_sig = SIGURG; break;
3338 case 17: os_sig = SIGSTOP; break;
3341 case 18: os_sig = SIGTSTP; break;
3344 case 19: os_sig = SIGCONT; break;
3347 case 20: os_sig = SIGCHLD; break;
3348 #elif defined(SIGCLD)
3349 case 20: os_sig = SIGCLD; break;
3352 case 21: os_sig = SIGTTIN; break;
3355 case 22: os_sig = SIGTTOU; break;
3358 case 23: os_sig = SIGIO; break;
3359 #elif defined (SIGPOLL)
3360 case 23: os_sig = SIGPOLL; break;
3363 case 24: os_sig = SIGXCPU; break;
3366 case 25: os_sig = SIGXFSZ; break;
3369 case 26: os_sig = SIGVTALRM; break;
3372 case 27: os_sig = SIGPROF; break;
3375 case 28: os_sig = SIGWINCH; break;
3378 case 29: os_sig = SIGLOST; break;
3381 case 30: os_sig = SIGUSR1; break;
3384 case 31: os_sig = SIGUSR2; break;
3390 trace_output_void ();
3391 (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
3392 (*d10v_callback->flush_stdout) (d10v_callback);
3393 State.exception = SIGILL;
3397 RETVAL (kill (PARM1, PARM2));
3398 trace_output_16 (result);
3403 case TARGET_SYS_execve:
3404 trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
3405 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
3406 (char **)MEMPTR (PARM3)));
3407 trace_output_16 (result);
3410 #ifdef TARGET_SYS_execv
3411 case TARGET_SYS_execv:
3412 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
3413 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
3414 trace_output_16 (result);
3418 case TARGET_SYS_pipe:
3423 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
3425 RETVAL (pipe (host_fd));
3426 SW (buf, host_fd[0]);
3427 buf += sizeof(uint16);
3428 SW (buf, host_fd[1]);
3429 trace_output_16 (result);
3434 #ifdef TARGET_SYS_wait
3435 case TARGET_SYS_wait:
3438 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
3439 RETVAL (wait (&status));
3442 trace_output_16 (result);
3448 case TARGET_SYS_getpid:
3449 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
3451 trace_output_16 (result);
3454 case TARGET_SYS_kill:
3455 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
3456 trace_output_void ();
3457 State.exception = PARM2;
3461 case TARGET_SYS_read:
3462 trace_input ("<read>", OP_R0, OP_R1, OP_R2);
3463 RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
3465 trace_output_16 (result);
3468 case TARGET_SYS_write:
3469 trace_input ("<write>", OP_R0, OP_R1, OP_R2);
3471 RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
3472 MEMPTR (PARM2), PARM3));
3474 RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
3475 MEMPTR (PARM2), PARM3));
3476 trace_output_16 (result);
3479 case TARGET_SYS_lseek:
3480 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
3481 RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
3482 ((((unsigned long) PARM2) << 16)
3483 || (unsigned long) PARM3),
3485 trace_output_32 (result);
3488 case TARGET_SYS_close:
3489 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
3490 RETVAL (d10v_callback->close (d10v_callback, PARM1));
3491 trace_output_16 (result);
3494 case TARGET_SYS_open:
3495 trace_input ("<open>", OP_R0, OP_R1, OP_R2);
3496 RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
3497 trace_output_16 (result);
3500 case TARGET_SYS_exit:
3501 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
3502 State.exception = SIG_D10V_EXIT;
3503 trace_output_void ();
3506 #ifdef TARGET_SYS_stat
3507 case TARGET_SYS_stat:
3508 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
3509 /* stat system call */
3511 struct stat host_stat;
3514 RETVAL (stat (MEMPTR (PARM1), &host_stat));
3518 /* The hard-coded offsets and sizes were determined by using
3519 * the D10V compiler on a test program that used struct stat.
3521 SW (buf, host_stat.st_dev);
3522 SW (buf+2, host_stat.st_ino);
3523 SW (buf+4, host_stat.st_mode);
3524 SW (buf+6, host_stat.st_nlink);
3525 SW (buf+8, host_stat.st_uid);
3526 SW (buf+10, host_stat.st_gid);
3527 SW (buf+12, host_stat.st_rdev);
3528 SLW (buf+16, host_stat.st_size);
3529 SLW (buf+20, host_stat.st_atime);
3530 SLW (buf+28, host_stat.st_mtime);
3531 SLW (buf+36, host_stat.st_ctime);
3533 trace_output_16 (result);
3537 case TARGET_SYS_chown:
3538 trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
3539 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
3540 trace_output_16 (result);
3543 case TARGET_SYS_chmod:
3544 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
3545 RETVAL (chmod (MEMPTR (PARM1), PARM2));
3546 trace_output_16 (result);
3550 #ifdef TARGET_SYS_utime
3551 case TARGET_SYS_utime:
3552 trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
3553 /* Cast the second argument to void *, to avoid type mismatch
3554 if a prototype is present. */
3555 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
3556 trace_output_16 (result);
3562 #ifdef TARGET_SYS_time
3563 case TARGET_SYS_time:
3564 trace_input ("<time>", OP_R0, OP_R1, OP_R2);
3565 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
3566 trace_output_32 (result);
3572 d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
3574 if ((uint16) result == (uint16) -1)
3575 RETERR (d10v_callback->get_errno(d10v_callback));
3587 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
3588 SET_PSW_F1 (PSW_F0);;
3589 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
3590 trace_output_flag ();
3597 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
3598 SET_PSW_F1 (PSW_F0);
3599 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
3600 trace_output_flag ();
3607 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
3609 trace_output_void ();
3617 trace_input ("xor", OP_REG, OP_REG, OP_VOID);
3618 tmp = (GPR (OP[0]) ^ GPR (OP[1]));
3619 SET_GPR (OP[0], tmp);
3620 trace_output_16 (tmp);
3628 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
3629 tmp = (GPR (OP[1]) ^ OP[2]);
3630 SET_GPR (OP[0], tmp);
3631 trace_output_16 (tmp);