5 #include "gdb/callback.h"
6 #include "gdb/remote-sim.h"
9 #include "sim-options.h"
11 #include "gdb/sim-d10v.h"
12 #include "gdb/signals.h"
19 #endif /* HAVE_STRING_H */
20 #endif /* HAVE_STRINGS_H */
26 enum _leftright { LEFT_FIRST, RIGHT_FIRST };
30 /* Set this to true to get the previous segment layout. */
32 int old_segment_mapping;
34 host_callback *d10v_callback;
35 unsigned long ins_type_counters[ (int)INS_MAX ];
39 static long hash (long insn, int format);
40 static struct hash_entry *lookup_hash (uint32 ins, int size);
41 static void get_operands (struct simops *s, uint32 ins);
42 static void do_long (uint32 ins);
43 static void do_2_short (uint16 ins1, uint16 ins2, enum _leftright leftright);
44 static void do_parallel (uint16 ins1, uint16 ins2);
45 static char *add_commas (char *buf, int sizeof_buf, unsigned long value);
46 static INLINE uint8 *map_memory (unsigned phys_addr);
51 struct hash_entry *next;
58 struct hash_entry hash_table[MAX_HASH+1];
61 hash (long insn, int format)
63 if (format & LONG_OPCODE)
64 return ((insn & 0x3F000000) >> 24);
66 return((insn & 0x7E00) >> 9);
69 INLINE static struct hash_entry *
70 lookup_hash (uint32 ins, int size)
75 h = &hash_table[(ins & 0x3F000000) >> 24];
77 h = &hash_table[(ins & 0x7E00) >> 9];
79 while ((ins & h->mask) != h->opcode || h->size != size)
83 State.exception = SIGILL;
84 State.pc_changed = 1; /* Don't increment the PC. */
93 get_operands (struct simops *s, uint32 ins)
95 int i, shift, bits, flags;
97 for (i=0; i < s->numops; i++)
99 shift = s->operands[3*i];
100 bits = s->operands[3*i+1];
101 flags = s->operands[3*i+2];
102 mask = 0x7FFFFFFF >> (31 - bits);
103 OP[i] = (ins >> shift) & mask;
105 /* FIXME: for tracing, update values that need to be updated each
106 instruction decode cycle */
107 State.trace.psw = PSW;
113 struct hash_entry *h;
115 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
116 (*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins);
118 h = lookup_hash (ins, 1);
121 get_operands (h->ops, ins);
122 State.ins_type = INS_LONG;
123 ins_type_counters[ (int)State.ins_type ]++;
128 do_2_short (uint16 ins1, uint16 ins2, enum _leftright leftright)
130 struct hash_entry *h;
131 enum _ins_type first, second;
134 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
135 (*d10v_callback->printf_filtered) (d10v_callback, "do_2_short 0x%x (%s) -> 0x%x\n",
136 ins1, (leftright) ? "left" : "right", ins2);
139 if (leftright == LEFT_FIRST)
143 ins_type_counters[ (int)INS_LEFTRIGHT ]++;
149 ins_type_counters[ (int)INS_RIGHTLEFT ]++;
152 /* Issue the first instruction */
153 h = lookup_hash (ins1, 0);
156 get_operands (h->ops, ins1);
157 State.ins_type = first;
158 ins_type_counters[ (int)State.ins_type ]++;
161 /* Issue the second instruction (if the PC hasn't changed) */
162 if (!State.pc_changed && !State.exception)
164 /* finish any existing instructions */
166 h = lookup_hash (ins2, 0);
169 get_operands (h->ops, ins2);
170 State.ins_type = second;
171 ins_type_counters[ (int)State.ins_type ]++;
172 ins_type_counters[ (int)INS_CYCLES ]++;
175 else if (!State.exception)
176 ins_type_counters[ (int)INS_COND_JUMP ]++;
180 do_parallel (uint16 ins1, uint16 ins2)
182 struct hash_entry *h1, *h2;
184 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
185 (*d10v_callback->printf_filtered) (d10v_callback, "do_parallel 0x%x || 0x%x\n", ins1, ins2);
187 ins_type_counters[ (int)INS_PARALLEL ]++;
188 h1 = lookup_hash (ins1, 0);
191 h2 = lookup_hash (ins2, 0);
195 if (h1->ops->exec_type == PARONLY)
197 get_operands (h1->ops, ins1);
198 State.ins_type = INS_LEFT_COND_TEST;
199 ins_type_counters[ (int)State.ins_type ]++;
203 ins_type_counters[ (int)INS_COND_TRUE ]++;
204 get_operands (h2->ops, ins2);
205 State.ins_type = INS_RIGHT_COND_EXE;
206 ins_type_counters[ (int)State.ins_type ]++;
210 ins_type_counters[ (int)INS_COND_FALSE ]++;
212 else if (h2->ops->exec_type == PARONLY)
214 get_operands (h2->ops, ins2);
215 State.ins_type = INS_RIGHT_COND_TEST;
216 ins_type_counters[ (int)State.ins_type ]++;
220 ins_type_counters[ (int)INS_COND_TRUE ]++;
221 get_operands (h1->ops, ins1);
222 State.ins_type = INS_LEFT_COND_EXE;
223 ins_type_counters[ (int)State.ins_type ]++;
227 ins_type_counters[ (int)INS_COND_FALSE ]++;
231 get_operands (h1->ops, ins1);
232 State.ins_type = INS_LEFT_PARALLEL;
233 ins_type_counters[ (int)State.ins_type ]++;
235 if (!State.exception)
237 get_operands (h2->ops, ins2);
238 State.ins_type = INS_RIGHT_PARALLEL;
239 ins_type_counters[ (int)State.ins_type ]++;
246 add_commas (char *buf, int sizeof_buf, unsigned long value)
249 char *endbuf = buf + sizeof_buf - 1;
259 *--endbuf = (value % 10) + '0';
260 } while ((value /= 10) != 0);
269 for (i = 0; i < IMEM_SEGMENTS; i++)
271 if (State.mem.insn[i])
272 free (State.mem.insn[i]);
274 for (i = 0; i < DMEM_SEGMENTS; i++)
276 if (State.mem.data[i])
277 free (State.mem.data[i]);
279 for (i = 0; i < UMEM_SEGMENTS; i++)
281 if (State.mem.unif[i])
282 free (State.mem.unif[i]);
284 /* Always allocate dmem segment 0. This contains the IMAP and DMAP
286 State.mem.data[0] = calloc (1, SEGMENT_SIZE);
289 /* For tracing - leave info on last access around. */
290 static char *last_segname = "invalid";
291 static char *last_from = "invalid";
292 static char *last_to = "invalid";
296 IMAP0_OFFSET = 0xff00,
297 DMAP0_OFFSET = 0xff08,
298 DMAP2_SHADDOW = 0xff04,
299 DMAP2_OFFSET = 0xff0c
303 set_dmap_register (int reg_nr, unsigned long value)
305 uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
306 + DMAP0_OFFSET + 2 * reg_nr);
307 WRITE_16 (raw, value);
309 if ((d10v_debug & DEBUG_MEMORY))
311 (*d10v_callback->printf_filtered)
312 (d10v_callback, "mem: dmap%d=0x%04lx\n", reg_nr, value);
318 dmap_register (void *regcache, int reg_nr)
320 uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
321 + DMAP0_OFFSET + 2 * reg_nr);
322 return READ_16 (raw);
326 set_imap_register (int reg_nr, unsigned long value)
328 uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
329 + IMAP0_OFFSET + 2 * reg_nr);
330 WRITE_16 (raw, value);
332 if ((d10v_debug & DEBUG_MEMORY))
334 (*d10v_callback->printf_filtered)
335 (d10v_callback, "mem: imap%d=0x%04lx\n", reg_nr, value);
341 imap_register (void *regcache, int reg_nr)
343 uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
344 + IMAP0_OFFSET + 2 * reg_nr);
345 return READ_16 (raw);
360 return HELD_SP (HELD_SPU_IDX);
369 return HELD_SP (HELD_SPI_IDX);
373 set_spi_register (unsigned long value)
376 SET_GPR (SP_IDX, value);
377 SET_HELD_SP (HELD_SPI_IDX, value);
381 set_spu_register (unsigned long value)
384 SET_GPR (SP_IDX, value);
385 SET_HELD_SP (HELD_SPU_IDX, value);
388 /* Given a virtual address in the DMAP address space, translate it
389 into a physical address. */
392 sim_d10v_translate_dmap_addr (unsigned long offset,
396 unsigned long (*dmap_register) (void *regcache,
401 last_from = "logical-data";
402 if (offset >= DMAP_BLOCK_SIZE * SIM_D10V_NR_DMAP_REGS)
404 /* Logical address out side of data segments, not supported */
407 regno = (offset / DMAP_BLOCK_SIZE);
408 offset = (offset % DMAP_BLOCK_SIZE);
409 if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE)
411 /* Don't cross a BLOCK boundary */
412 nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE);
414 map = dmap_register (regcache, regno);
417 /* Always maps to data memory */
418 int iospi = (offset / 0x1000) % 4;
419 int iosp = (map >> (4 * (3 - iospi))) % 0x10;
420 last_to = "io-space";
421 *phys = (SIM_D10V_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset);
425 int sp = ((map & 0x3000) >> 12);
426 int segno = (map & 0x3ff);
429 case 0: /* 00: Unified memory */
430 *phys = SIM_D10V_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset;
433 case 1: /* 01: Instruction Memory */
434 *phys = SIM_D10V_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset;
435 last_to = "chip-insn";
437 case 2: /* 10: Internal data memory */
438 *phys = SIM_D10V_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset;
439 last_to = "chip-data";
441 case 3: /* 11: Reserved */
448 /* Given a virtual address in the IMAP address space, translate it
449 into a physical address. */
452 sim_d10v_translate_imap_addr (unsigned long offset,
456 unsigned long (*imap_register) (void *regcache,
463 last_from = "logical-insn";
464 if (offset >= (IMAP_BLOCK_SIZE * SIM_D10V_NR_IMAP_REGS))
466 /* Logical address outside of IMAP segments, not supported */
469 regno = (offset / IMAP_BLOCK_SIZE);
470 offset = (offset % IMAP_BLOCK_SIZE);
471 if (offset + nr_bytes > IMAP_BLOCK_SIZE)
473 /* Don't cross a BLOCK boundary */
474 nr_bytes = IMAP_BLOCK_SIZE - offset;
476 map = imap_register (regcache, regno);
477 sp = (map & 0x3000) >> 12;
478 segno = (map & 0x007f);
481 case 0: /* 00: unified memory */
482 *phys = SIM_D10V_MEMORY_UNIFIED + (segno << 17) + offset;
485 case 1: /* 01: instruction memory */
486 *phys = SIM_D10V_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset;
487 last_to = "chip-insn";
492 case 3: /* 11: for testing - instruction memory */
493 offset = (offset % 0x800);
494 *phys = SIM_D10V_MEMORY_INSN + offset;
495 if (offset + nr_bytes > 0x800)
496 /* don't cross VM boundary */
497 nr_bytes = 0x800 - offset;
498 last_to = "test-insn";
505 sim_d10v_translate_addr (unsigned long memaddr,
507 unsigned long *targ_addr,
509 unsigned long (*dmap_register) (void *regcache,
511 unsigned long (*imap_register) (void *regcache,
518 last_from = "unknown";
521 seg = (memaddr >> 24);
522 off = (memaddr & 0xffffffL);
524 /* However, if we've asked to use the previous generation of segment
525 mapping, rearrange the segments as follows. */
527 if (old_segment_mapping)
531 case 0x00: /* DMAP translated memory */
534 case 0x01: /* IMAP translated memory */
537 case 0x10: /* On-chip data memory */
540 case 0x11: /* On-chip insn memory */
543 case 0x12: /* Unified memory */
551 case 0x00: /* Physical unified memory */
552 last_from = "phys-unified";
554 phys = SIM_D10V_MEMORY_UNIFIED + off;
555 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
556 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
559 case 0x01: /* Physical instruction memory */
560 last_from = "phys-insn";
561 last_to = "chip-insn";
562 phys = SIM_D10V_MEMORY_INSN + off;
563 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
564 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
567 case 0x02: /* Physical data memory segment */
568 last_from = "phys-data";
569 last_to = "chip-data";
570 phys = SIM_D10V_MEMORY_DATA + off;
571 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
572 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
575 case 0x10: /* in logical data address segment */
576 nr_bytes = sim_d10v_translate_dmap_addr (off, nr_bytes, &phys, regcache,
580 case 0x11: /* in logical instruction address segment */
581 nr_bytes = sim_d10v_translate_imap_addr (off, nr_bytes, &phys, regcache,
593 /* Return a pointer into the raw buffer designated by phys_addr. It
594 is assumed that the client has already ensured that the access
595 isn't going to cross a segment boundary. */
598 map_memory (unsigned phys_addr)
603 int segment = ((phys_addr >> 24) & 0xff);
608 case 0x00: /* Unified memory */
610 memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS];
611 last_segname = "umem";
615 case 0x01: /* On-chip insn memory */
617 memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS];
618 last_segname = "imem";
622 case 0x02: /* On-chip data memory */
624 if ((phys_addr & 0xff00) == 0xff00)
626 phys_addr = (phys_addr & 0xffff);
627 if (phys_addr == DMAP2_SHADDOW)
629 phys_addr = DMAP2_OFFSET;
630 last_segname = "dmap";
633 last_segname = "reg";
636 last_segname = "dmem";
637 memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS];
643 last_segname = "scrap";
644 return State.mem.fault;
649 *memory = calloc (1, SEGMENT_SIZE);
652 (*d10v_callback->printf_filtered) (d10v_callback, "Malloc failed.\n");
653 return State.mem.fault;
657 offset = (phys_addr % SEGMENT_SIZE);
658 raw = *memory + offset;
662 /* Transfer data to/from simulated memory. Since a bug in either the
663 simulated program or in gdb or the simulator itself may cause a
664 bogus address to be passed in, we need to do some sanity checking
665 on addresses to make sure they are within bounds. When an address
666 fails the bounds check, treat it as a zero length read/write rather
667 than aborting the entire run. */
670 xfer_mem (SIM_ADDR virt,
671 unsigned char *buffer,
678 phys_size = sim_d10v_translate_addr (virt, size, &phys, NULL,
679 dmap_register, imap_register);
683 memory = map_memory (phys);
686 if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
688 (*d10v_callback->printf_filtered)
690 "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
691 (write_p ? "write" : "read"),
692 phys_size, virt, last_from,
694 (long) memory, last_segname);
700 memcpy (memory, buffer, phys_size);
704 memcpy (buffer, memory, phys_size);
712 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
714 /* FIXME: this should be performing a virtual transfer */
715 return xfer_mem( addr, buffer, size, 1);
719 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
721 /* FIXME: this should be performing a virtual transfer */
722 return xfer_mem( addr, buffer, size, 0);
726 free_state (SIM_DESC sd)
728 if (STATE_MODULES (sd) != NULL)
729 sim_module_uninstall (sd);
730 sim_cpu_free_all (sd);
734 SIM_DESC trace_sd = NULL;
737 sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
740 struct hash_entry *h;
741 static int init_p = 0;
743 SIM_DESC sd = sim_state_alloc (kind, cb);
744 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
746 /* The cpu data is kept in a separately allocated chunk of memory. */
747 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
753 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
759 /* getopt will print the error message so we just have to exit if this fails.
760 FIXME: Hmmm... in the case of gdb we need getopt to call
762 if (sim_parse_args (sd, argv) != SIM_RC_OK)
768 /* Check for/establish the a reference program image. */
769 if (sim_analyze_program (sd,
770 (STATE_PROG_ARGV (sd) != NULL
771 ? *STATE_PROG_ARGV (sd)
772 : NULL), abfd) != SIM_RC_OK)
778 /* Configure/verify the target byte order and other runtime
779 configuration options. */
780 if (sim_config (sd) != SIM_RC_OK)
782 sim_module_uninstall (sd);
786 if (sim_post_argv_init (sd) != SIM_RC_OK)
788 /* Uninstall the modules to avoid memory leaks,
789 file descriptor leaks, etc. */
790 sim_module_uninstall (sd);
796 old_segment_mapping = 0;
798 /* NOTE: This argument parsing is only effective when this function
799 is called by GDB. Standalone argument parsing is handled by
801 for (p = argv + 1; *p; ++p)
803 if (strcmp (*p, "-oldseg") == 0)
804 old_segment_mapping = 1;
806 else if (strcmp (*p, "-t") == 0)
808 else if (strncmp (*p, "-t", 2) == 0)
809 d10v_debug = atoi (*p + 2);
813 /* put all the opcodes in the hash table */
816 for (s = Simops; s->func; s++)
818 h = &hash_table[hash(s->opcode,s->format)];
820 /* go to the last entry in the chain */
826 h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
828 perror ("malloc failure");
834 h->opcode = s->opcode;
835 h->size = s->is_long;
839 /* reset the processor state */
840 if (!State.mem.data[0])
842 sim_create_inferior ((SIM_DESC) 1, NULL, NULL, NULL);
849 sim_close (SIM_DESC sd, int quitting)
855 dmem_addr (uint16 offset)
861 /* Note: DMEM address range is 0..0x10000. Calling code can compute
862 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
863 is uint16 this is modulo'ed onto 0x0e5d. */
865 phys_size = sim_d10v_translate_dmap_addr (offset, 1, &phys, NULL,
869 mem = State.mem.fault;
872 mem = map_memory (phys);
874 if ((d10v_debug & DEBUG_MEMORY))
876 (*d10v_callback->printf_filtered)
878 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
880 phys, phys_size, last_to,
881 (long) mem, last_segname);
888 imem_addr (uint32 offset)
892 int phys_size = sim_d10v_translate_imap_addr (offset, 1, &phys, NULL,
896 return State.mem.fault;
898 mem = map_memory (phys);
900 if ((d10v_debug & DEBUG_MEMORY))
902 (*d10v_callback->printf_filtered)
904 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
906 phys, phys_size, last_to,
907 (long) mem, last_segname);
913 static int stop_simulator = 0;
916 sim_stop (SIM_DESC sd)
923 /* Run (or resume) the program. */
925 sim_resume (SIM_DESC sd, int step, int siggnal)
930 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
945 SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
946 JMP (AE_VECTOR_START);
952 SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
953 JMP (RIE_VECTOR_START);
963 iaddr = imem_addr ((uint32)PC << 2);
964 if (iaddr == State.mem.fault)
966 State.exception = SIGBUS;
970 inst = get_longword( iaddr );
972 State.pc_changed = 0;
973 ins_type_counters[ (int)INS_CYCLES ]++;
975 switch (inst & 0xC0000000)
978 /* long instruction */
979 do_long (inst & 0x3FFFFFFF);
983 do_2_short ( inst & 0x7FFF, (inst & 0x3FFF8000) >> 15, RIGHT_FIRST);
987 do_2_short ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF, LEFT_FIRST);
990 do_parallel ((inst & 0x3FFF8000) >> 15, inst & 0x7FFF);
994 /* If the PC of the current instruction matches RPT_E then
995 schedule a branch to the loop start. If one of those
996 instructions happens to be a branch, than that instruction
998 if (!State.pc_changed)
1000 if (PSW_RP && PC == RPT_E)
1002 /* Note: The behavour of a branch instruction at RPT_E
1003 is implementation dependant, this simulator takes the
1004 branch. Branching to RPT_E is valid, the instruction
1005 must be executed before the loop is taken. */
1014 SET_RPT_C (RPT_C - 1);
1022 /* Check for a breakpoint trap on this instruction. This
1023 overrides any pending branches or loops */
1024 if (PSW_DB && PC == IBA)
1028 SET_PSW (PSW & PSW_SM_BIT);
1029 SET_PC (SDBT_VECTOR_START);
1032 /* Writeback all the DATA / PC changes */
1035 while ( !State.exception && !stop_simulator);
1037 if (step && !State.exception)
1038 State.exception = SIGTRAP;
1042 sim_info (SIM_DESC sd, int verbose)
1049 unsigned long left = ins_type_counters[ (int)INS_LEFT ] + ins_type_counters[ (int)INS_LEFT_COND_EXE ];
1050 unsigned long left_nops = ins_type_counters[ (int)INS_LEFT_NOPS ];
1051 unsigned long left_parallel = ins_type_counters[ (int)INS_LEFT_PARALLEL ];
1052 unsigned long left_cond = ins_type_counters[ (int)INS_LEFT_COND_TEST ];
1053 unsigned long left_total = left + left_parallel + left_cond + left_nops;
1055 unsigned long right = ins_type_counters[ (int)INS_RIGHT ] + ins_type_counters[ (int)INS_RIGHT_COND_EXE ];
1056 unsigned long right_nops = ins_type_counters[ (int)INS_RIGHT_NOPS ];
1057 unsigned long right_parallel = ins_type_counters[ (int)INS_RIGHT_PARALLEL ];
1058 unsigned long right_cond = ins_type_counters[ (int)INS_RIGHT_COND_TEST ];
1059 unsigned long right_total = right + right_parallel + right_cond + right_nops;
1061 unsigned long unknown = ins_type_counters[ (int)INS_UNKNOWN ];
1062 unsigned long ins_long = ins_type_counters[ (int)INS_LONG ];
1063 unsigned long parallel = ins_type_counters[ (int)INS_PARALLEL ];
1064 unsigned long leftright = ins_type_counters[ (int)INS_LEFTRIGHT ];
1065 unsigned long rightleft = ins_type_counters[ (int)INS_RIGHTLEFT ];
1066 unsigned long cond_true = ins_type_counters[ (int)INS_COND_TRUE ];
1067 unsigned long cond_false = ins_type_counters[ (int)INS_COND_FALSE ];
1068 unsigned long cond_jump = ins_type_counters[ (int)INS_COND_JUMP ];
1069 unsigned long cycles = ins_type_counters[ (int)INS_CYCLES ];
1070 unsigned long total = (unknown + left_total + right_total + ins_long);
1072 int size = strlen (add_commas (buf1, sizeof (buf1), total));
1073 int parallel_size = strlen (add_commas (buf1, sizeof (buf1),
1074 (left_parallel > right_parallel) ? left_parallel : right_parallel));
1075 int cond_size = strlen (add_commas (buf1, sizeof (buf1), (left_cond > right_cond) ? left_cond : right_cond));
1076 int nop_size = strlen (add_commas (buf1, sizeof (buf1), (left_nops > right_nops) ? left_nops : right_nops));
1077 int normal_size = strlen (add_commas (buf1, sizeof (buf1), (left > right) ? left : right));
1079 (*d10v_callback->printf_filtered) (d10v_callback,
1080 "executed %*s left instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1081 size, add_commas (buf1, sizeof (buf1), left_total),
1082 normal_size, add_commas (buf2, sizeof (buf2), left),
1083 parallel_size, add_commas (buf3, sizeof (buf3), left_parallel),
1084 cond_size, add_commas (buf4, sizeof (buf4), left_cond),
1085 nop_size, add_commas (buf5, sizeof (buf5), left_nops));
1087 (*d10v_callback->printf_filtered) (d10v_callback,
1088 "executed %*s right instruction(s), %*s normal, %*s parallel, %*s EXExxx, %*s nops\n",
1089 size, add_commas (buf1, sizeof (buf1), right_total),
1090 normal_size, add_commas (buf2, sizeof (buf2), right),
1091 parallel_size, add_commas (buf3, sizeof (buf3), right_parallel),
1092 cond_size, add_commas (buf4, sizeof (buf4), right_cond),
1093 nop_size, add_commas (buf5, sizeof (buf5), right_nops));
1096 (*d10v_callback->printf_filtered) (d10v_callback,
1097 "executed %*s long instruction(s)\n",
1098 size, add_commas (buf1, sizeof (buf1), ins_long));
1101 (*d10v_callback->printf_filtered) (d10v_callback,
1102 "executed %*s parallel instruction(s)\n",
1103 size, add_commas (buf1, sizeof (buf1), parallel));
1106 (*d10v_callback->printf_filtered) (d10v_callback,
1107 "executed %*s instruction(s) encoded L->R\n",
1108 size, add_commas (buf1, sizeof (buf1), leftright));
1111 (*d10v_callback->printf_filtered) (d10v_callback,
1112 "executed %*s instruction(s) encoded R->L\n",
1113 size, add_commas (buf1, sizeof (buf1), rightleft));
1116 (*d10v_callback->printf_filtered) (d10v_callback,
1117 "executed %*s unknown instruction(s)\n",
1118 size, add_commas (buf1, sizeof (buf1), unknown));
1121 (*d10v_callback->printf_filtered) (d10v_callback,
1122 "executed %*s instruction(s) due to EXExxx condition being true\n",
1123 size, add_commas (buf1, sizeof (buf1), cond_true));
1126 (*d10v_callback->printf_filtered) (d10v_callback,
1127 "skipped %*s instruction(s) due to EXExxx condition being false\n",
1128 size, add_commas (buf1, sizeof (buf1), cond_false));
1131 (*d10v_callback->printf_filtered) (d10v_callback,
1132 "skipped %*s instruction(s) due to conditional branch succeeding\n",
1133 size, add_commas (buf1, sizeof (buf1), cond_jump));
1135 (*d10v_callback->printf_filtered) (d10v_callback,
1136 "executed %*s cycle(s)\n",
1137 size, add_commas (buf1, sizeof (buf1), cycles));
1139 (*d10v_callback->printf_filtered) (d10v_callback,
1140 "executed %*s total instructions\n",
1141 size, add_commas (buf1, sizeof (buf1), total));
1145 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
1147 bfd_vma start_address;
1149 /* reset all state information */
1150 memset (&State.regs, 0, (uintptr_t)&State.mem - (uintptr_t)&State.regs);
1152 /* There was a hack here to copy the values of argc and argv into r0
1153 and r1. The values were also saved into some high memory that
1154 won't be overwritten by the stack (0x7C00). The reason for doing
1155 this was to allow the 'run' program to accept arguments. Without
1156 the hack, this is not possible anymore. If the simulator is run
1157 from the debugger, arguments cannot be passed in, so this makes
1162 start_address = bfd_get_start_address (abfd);
1164 start_address = 0xffc0 << 2;
1167 (*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%lx\n", (long) start_address);
1169 SET_CREG (PC_CR, start_address >> 2);
1171 /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
1172 initializes imap0 and imap1 to 0x1000 as part of its ROM
1174 if (old_segment_mapping)
1176 /* External memory startup. This is the HARD reset state. */
1177 set_imap_register (0, 0x0000);
1178 set_imap_register (1, 0x007f);
1179 set_dmap_register (0, 0x2000);
1180 set_dmap_register (1, 0x2000);
1181 set_dmap_register (2, 0x0000); /* Old DMAP */
1182 set_dmap_register (3, 0x0000);
1186 /* Internal memory startup. This is the ROM intialized state. */
1187 set_imap_register (0, 0x1000);
1188 set_imap_register (1, 0x1000);
1189 set_dmap_register (0, 0x2000);
1190 set_dmap_register (1, 0x2000);
1191 set_dmap_register (2, 0x2000); /* DMAP2 initial internal value is
1192 0x2000 on the new board. */
1193 set_dmap_register (3, 0x0000);
1201 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
1203 /* (*d10v_callback->printf_filtered) (d10v_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
1205 switch (State.exception)
1207 case SIG_D10V_STOP: /* stop instruction */
1208 *reason = sim_exited;
1212 case SIG_D10V_EXIT: /* exit trap */
1213 *reason = sim_exited;
1218 *reason = sim_stopped;
1219 *sigrc = GDB_SIGNAL_BUS;
1222 default: /* some signal */
1223 *reason = sim_stopped;
1224 if (stop_simulator && !State.exception)
1225 *sigrc = GDB_SIGNAL_INT;
1227 *sigrc = State.exception;
1235 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1238 switch ((enum sim_d10v_regs) rn)
1240 case SIM_D10V_R0_REGNUM:
1241 case SIM_D10V_R1_REGNUM:
1242 case SIM_D10V_R2_REGNUM:
1243 case SIM_D10V_R3_REGNUM:
1244 case SIM_D10V_R4_REGNUM:
1245 case SIM_D10V_R5_REGNUM:
1246 case SIM_D10V_R6_REGNUM:
1247 case SIM_D10V_R7_REGNUM:
1248 case SIM_D10V_R8_REGNUM:
1249 case SIM_D10V_R9_REGNUM:
1250 case SIM_D10V_R10_REGNUM:
1251 case SIM_D10V_R11_REGNUM:
1252 case SIM_D10V_R12_REGNUM:
1253 case SIM_D10V_R13_REGNUM:
1254 case SIM_D10V_R14_REGNUM:
1255 case SIM_D10V_R15_REGNUM:
1256 WRITE_16 (memory, GPR (rn - SIM_D10V_R0_REGNUM));
1259 case SIM_D10V_CR0_REGNUM:
1260 case SIM_D10V_CR1_REGNUM:
1261 case SIM_D10V_CR2_REGNUM:
1262 case SIM_D10V_CR3_REGNUM:
1263 case SIM_D10V_CR4_REGNUM:
1264 case SIM_D10V_CR5_REGNUM:
1265 case SIM_D10V_CR6_REGNUM:
1266 case SIM_D10V_CR7_REGNUM:
1267 case SIM_D10V_CR8_REGNUM:
1268 case SIM_D10V_CR9_REGNUM:
1269 case SIM_D10V_CR10_REGNUM:
1270 case SIM_D10V_CR11_REGNUM:
1271 case SIM_D10V_CR12_REGNUM:
1272 case SIM_D10V_CR13_REGNUM:
1273 case SIM_D10V_CR14_REGNUM:
1274 case SIM_D10V_CR15_REGNUM:
1275 WRITE_16 (memory, CREG (rn - SIM_D10V_CR0_REGNUM));
1278 case SIM_D10V_A0_REGNUM:
1279 case SIM_D10V_A1_REGNUM:
1280 WRITE_64 (memory, ACC (rn - SIM_D10V_A0_REGNUM));
1283 case SIM_D10V_SPI_REGNUM:
1284 /* PSW_SM indicates that the current SP is the USER
1286 WRITE_16 (memory, spi_register ());
1289 case SIM_D10V_SPU_REGNUM:
1290 /* PSW_SM indicates that the current SP is the USER
1292 WRITE_16 (memory, spu_register ());
1295 case SIM_D10V_IMAP0_REGNUM:
1296 case SIM_D10V_IMAP1_REGNUM:
1297 WRITE_16 (memory, imap_register (NULL, rn - SIM_D10V_IMAP0_REGNUM));
1300 case SIM_D10V_DMAP0_REGNUM:
1301 case SIM_D10V_DMAP1_REGNUM:
1302 case SIM_D10V_DMAP2_REGNUM:
1303 case SIM_D10V_DMAP3_REGNUM:
1304 WRITE_16 (memory, dmap_register (NULL, rn - SIM_D10V_DMAP0_REGNUM));
1307 case SIM_D10V_TS2_DMAP_REGNUM:
1318 sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1321 switch ((enum sim_d10v_regs) rn)
1323 case SIM_D10V_R0_REGNUM:
1324 case SIM_D10V_R1_REGNUM:
1325 case SIM_D10V_R2_REGNUM:
1326 case SIM_D10V_R3_REGNUM:
1327 case SIM_D10V_R4_REGNUM:
1328 case SIM_D10V_R5_REGNUM:
1329 case SIM_D10V_R6_REGNUM:
1330 case SIM_D10V_R7_REGNUM:
1331 case SIM_D10V_R8_REGNUM:
1332 case SIM_D10V_R9_REGNUM:
1333 case SIM_D10V_R10_REGNUM:
1334 case SIM_D10V_R11_REGNUM:
1335 case SIM_D10V_R12_REGNUM:
1336 case SIM_D10V_R13_REGNUM:
1337 case SIM_D10V_R14_REGNUM:
1338 case SIM_D10V_R15_REGNUM:
1339 SET_GPR (rn - SIM_D10V_R0_REGNUM, READ_16 (memory));
1342 case SIM_D10V_CR0_REGNUM:
1343 case SIM_D10V_CR1_REGNUM:
1344 case SIM_D10V_CR2_REGNUM:
1345 case SIM_D10V_CR3_REGNUM:
1346 case SIM_D10V_CR4_REGNUM:
1347 case SIM_D10V_CR5_REGNUM:
1348 case SIM_D10V_CR6_REGNUM:
1349 case SIM_D10V_CR7_REGNUM:
1350 case SIM_D10V_CR8_REGNUM:
1351 case SIM_D10V_CR9_REGNUM:
1352 case SIM_D10V_CR10_REGNUM:
1353 case SIM_D10V_CR11_REGNUM:
1354 case SIM_D10V_CR12_REGNUM:
1355 case SIM_D10V_CR13_REGNUM:
1356 case SIM_D10V_CR14_REGNUM:
1357 case SIM_D10V_CR15_REGNUM:
1358 SET_CREG (rn - SIM_D10V_CR0_REGNUM, READ_16 (memory));
1361 case SIM_D10V_A0_REGNUM:
1362 case SIM_D10V_A1_REGNUM:
1363 SET_ACC (rn - SIM_D10V_A0_REGNUM, READ_64 (memory) & MASK40);
1366 case SIM_D10V_SPI_REGNUM:
1367 /* PSW_SM indicates that the current SP is the USER
1369 set_spi_register (READ_16 (memory));
1372 case SIM_D10V_SPU_REGNUM:
1373 set_spu_register (READ_16 (memory));
1376 case SIM_D10V_IMAP0_REGNUM:
1377 case SIM_D10V_IMAP1_REGNUM:
1378 set_imap_register (rn - SIM_D10V_IMAP0_REGNUM, READ_16(memory));
1381 case SIM_D10V_DMAP0_REGNUM:
1382 case SIM_D10V_DMAP1_REGNUM:
1383 case SIM_D10V_DMAP2_REGNUM:
1384 case SIM_D10V_DMAP3_REGNUM:
1385 set_dmap_register (rn - SIM_D10V_DMAP0_REGNUM, READ_16(memory));
1388 case SIM_D10V_TS2_DMAP_REGNUM: