6 #include "opcode/d10v.h"
8 #define DEBUG_TRACE 0x00000001
9 #define DEBUG_VALUES 0x00000002
10 #define DEBUG_LINE_NUMBER 0x00000004
11 #define DEBUG_MEMSIZE 0x00000008
12 #define DEBUG_INSTRUCTION 0x00000010
15 #define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
18 extern int d10v_debug;
21 typedef unsigned char uint8;
22 typedef signed char int8;
24 #error "Char is not an 8-bit type"
28 typedef unsigned short uint16;
29 typedef signed short int16;
31 #error "Short is not a 16-bit type"
34 #if INT_MAX == 2147483647
35 typedef unsigned int uint32;
36 typedef signed int int32;
38 #elif LONG_MAX == 2147483647
39 typedef unsigned long uint32;
40 typedef signed long int32;
43 #error "Neither int nor long is a 32-bit type"
46 #if LONG_MAX > 2147483647
47 typedef unsigned long uint64;
48 typedef signed long int64;
51 typedef unsigned long long uint64;
52 typedef signed long long int64;
55 #error "Can't find an appropriate 64-bit type"
58 /* FIXME: D10V defines */
76 INS_UNKNOWN, /* unknown instruction */
77 INS_COND_TRUE, /* # times EXExxx executed other instruction */
78 INS_COND_FALSE, /* # times EXExxx did not execute other instruction */
79 INS_COND_JUMP, /* # times JUMP skipped other instruction */
80 INS_CYCLES, /* # cycles */
81 INS_LONG, /* long instruction (both containers, ie FM == 11) */
82 INS_LEFTRIGHT, /* # times instruction encoded as L -> R (ie, FM == 01) */
83 INS_RIGHTLEFT, /* # times instruction encoded as L <- R (ie, FM == 10) */
84 INS_PARALLEL, /* # times instruction encoded as L || R (ie, RM == 00) */
86 INS_LEFT, /* normal left instructions */
87 INS_LEFT_PARALLEL, /* left side of || */
88 INS_LEFT_COND_TEST, /* EXExx test on left side */
89 INS_LEFT_COND_EXE, /* execution after EXExxx test on right side succeeded */
90 INS_LEFT_NOPS, /* NOP on left side */
92 INS_RIGHT, /* normal right instructions */
93 INS_RIGHT_PARALLEL, /* right side of || */
94 INS_RIGHT_COND_TEST, /* EXExx test on right side */
95 INS_RIGHT_COND_EXE, /* execution after EXExxx test on left side succeeded */
96 INS_RIGHT_NOPS, /* NOP on right side */
101 extern unsigned long ins_type_counters[ (int)INS_MAX ];
105 reg_t regs[16]; /* general-purpose registers */
106 reg_t cregs[16]; /* control registers */
107 int64 a[2]; /* accumulators */
121 /* everything below this line is not reset by sim_create_inferior() */
125 enum _ins_type ins_type;
128 extern host_callback *d10v_callback;
130 extern struct simops Simops[];
132 #define PC (State.cregs[2])
133 #define PSW (State.cregs[0])
134 #define BPSW (State.cregs[1])
135 #define BPC (State.cregs[3])
136 #define RPT_C (State.cregs[7])
137 #define RPT_S (State.cregs[8])
138 #define RPT_E (State.cregs[9])
139 #define MOD_S (State.cregs[10])
140 #define MOD_E (State.cregs[11])
141 #define IBA (State.cregs[14])
143 #define SIG_D10V_STOP -1
144 #define SIG_D10V_EXIT -2
146 #define SEXT3(x) ((((x)&0x7)^(~3))+4)
148 /* sign-extend a 4-bit number */
149 #define SEXT4(x) ((((x)&0xf)^(~7))+8)
151 /* sign-extend an 8-bit number */
152 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
154 /* sign-extend a 16-bit number */
155 #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
157 /* sign-extend a 32-bit number */
158 #define SEXT32(x) ((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL)
160 /* sign extend a 40 bit number */
161 #define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL)
163 /* sign extend a 44 bit number */
164 #define SEXT44(x) ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL)
166 /* sign extend a 60 bit number */
167 #define SEXT60(x) ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL)
169 #define MAX32 0x7fffffffLL
170 #define MIN32 0xff80000000LL
171 #define MASK32 0xffffffffLL
172 #define MASK40 0xffffffffffLL
174 #define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
176 extern uint8 *dmem_addr PARAMS ((uint32));
178 #define RB(x) (*(dmem_addr(x)))
179 #define SB(addr,data) ( RB(addr) = (data & 0xff))
181 #if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
182 #define ENDIAN_INLINE static __inline__
187 extern uint32 get_longword PARAMS ((uint8 *));
188 extern uint16 get_word PARAMS ((uint8 *));
189 extern int64 get_longlong PARAMS ((uint8 *));
190 extern void write_word PARAMS ((uint8 *addr, uint16 data));
191 extern void write_longword PARAMS ((uint8 *addr, uint32 data));
192 extern void write_longlong PARAMS ((uint8 *addr, int64 data));
195 #define SW(addr,data) write_word(dmem_addr(addr),data)
196 #define RW(x) get_word(dmem_addr(x))
197 #define SLW(addr,data) write_longword(dmem_addr(addr),data)
198 #define RLW(x) get_longword(dmem_addr(x))
199 #define READ_16(x) get_word(x)
200 #define WRITE_16(addr,data) write_word(addr,data)
201 #define READ_64(x) get_longlong(x)
202 #define WRITE_64(addr,data) write_longlong(addr,data)
204 #define IMAP0 RW(0xff00)
205 #define IMAP1 RW(0xff02)
206 #define DMAP RW(0xff04)
207 #define SET_IMAP0(x) SW(0xff00,x)
208 #define SET_IMAP1(x) SW(0xff02,x)
209 #define SET_DMAP(x) SW(0xff04,x)