1 /* CPU family header for crisv10f.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996-2005 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>.
24 #ifndef CPU_CRISV10F_H
25 #define CPU_CRISV10F_H
27 /* Maximum number of instructions that are fetched at a time.
28 This is for LIW type instructions sets (e.g. m32r). */
29 #define MAX_LIW_INSNS 1
31 /* Maximum number of instructions that can be executed in parallel. */
32 #define MAX_PARALLEL_INSNS 1
34 /* CPU state information. */
36 /* Hardware elements. */
40 #define GET_H_PC() CPU (h_pc)
43 CPU (h_pc) = ANDSI ((x), (~ (1)));\
45 /* General purpose registers */
47 #define GET_H_GR_REAL_PC(a1) CPU (h_gr_real_pc)[a1]
48 #define SET_H_GR_REAL_PC(a1, x) (CPU (h_gr_real_pc)[a1] = (x))
49 /* Special registers for v10 */
51 #define GET_H_SR_V10(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (10) : (ORIF (((index) == (((UINT) 5))), ((index) == (((UINT) 13))))) ? (ORSI (ANDSI (CPU (h_sr_v10[((UINT) 5)]), 0xffffff00), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), 0)))))))))) : (CPU (h_sr_v10[index]))
52 #define SET_H_SR_V10(index, x) \
54 if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\
57 else if (ORIF ((((index)) == (((UINT) 5))), (((index)) == (((UINT) 13))))) {\
59 CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\
60 CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\
61 CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\
62 CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\
63 CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\
64 SET_H_IBIT (((NESI (ANDSI ((x), ((1) << (5))), 0)) ? (1) : (0)));\
65 SET_H_UBIT (((NESI (ANDSI ((x), ((1) << (6))), 0)) ? (1) : (0)));\
66 CPU (h_pbit) = ((NESI (ANDSI ((x), ((1) << (7))), 0)) ? (1) : (0));\
67 CPU (h_sr_v10[((UINT) 5)]) = (x);\
68 CPU (h_sr_v10[((UINT) 13)]) = (x);\
72 CPU (h_sr_v10[(index)]) = (x);\
77 #define GET_H_CBIT() CPU (h_cbit)
78 #define SET_H_CBIT(x) (CPU (h_cbit) = (x))
81 #define GET_H_VBIT() CPU (h_vbit)
82 #define SET_H_VBIT(x) (CPU (h_vbit) = (x))
85 #define GET_H_ZBIT() CPU (h_zbit)
86 #define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
89 #define GET_H_NBIT() CPU (h_nbit)
90 #define SET_H_NBIT(x) (CPU (h_nbit) = (x))
91 /* extended-arithmetic bit */
93 #define GET_H_XBIT() CPU (h_xbit)
94 #define SET_H_XBIT(x) (CPU (h_xbit) = (x))
95 /* interrupt-enable bit */
97 #define GET_H_IBIT_PRE_V32() CPU (h_ibit_pre_v32)
98 #define SET_H_IBIT_PRE_V32(x) (CPU (h_ibit_pre_v32) = (x))
99 /* sequence-broken bit */
101 #define GET_H_PBIT() CPU (h_pbit)
102 #define SET_H_PBIT(x) (CPU (h_pbit) = (x))
105 #define GET_H_UBIT_PRE_V32() CPU (h_ubit_pre_v32)
106 #define SET_H_UBIT_PRE_V32(x) (CPU (h_ubit_pre_v32) = (x))
107 /* instruction-is-prefixed bit */
108 BI h_insn_prefixed_p_pre_v32;
109 #define GET_H_INSN_PREFIXED_P_PRE_V32() CPU (h_insn_prefixed_p_pre_v32)
110 #define SET_H_INSN_PREFIXED_P_PRE_V32(x) (CPU (h_insn_prefixed_p_pre_v32) = (x))
111 /* Prefix-address register */
112 SI h_prefixreg_pre_v32;
113 #define GET_H_PREFIXREG_PRE_V32() CPU (h_prefixreg_pre_v32)
114 #define SET_H_PREFIXREG_PRE_V32(x) (CPU (h_prefixreg_pre_v32) = (x))
116 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
121 #define GET_H_V32_NON_V32() 0
122 #define SET_H_V32_NON_V32(x) \
124 cgen_rtx_error (current_cpu, "Can't set h-v32");\
126 #define GET_H_GR(index) GET_H_GR_PC (index)
127 #define SET_H_GR(index, x) \
129 SET_H_GR_PC ((index), (x));\
131 #define GET_H_GR_PC(index) ((((index) == (15))) ? ((cgen_rtx_error (current_cpu, "General register read of PC is not implemented."), 0)) : (CPU (h_gr_real_pc[index])))
132 #define SET_H_GR_PC(index, x) \
135 if ((((index)) == (15))) {\
136 cgen_rtx_error (current_cpu, "General register write to PC is not implemented.");\
138 CPU (h_gr_real_pc[(index)]) = (x);\
141 #define GET_H_RAW_GR_PC(index) CPU (h_gr_real_pc[index])
142 #define SET_H_RAW_GR_PC(index, x) \
144 CPU (h_gr_real_pc[(index)]) = (x);\
146 #define GET_H_SR(index) GET_H_SR_V10 (index)
147 #define SET_H_SR(index, x) \
149 SET_H_SR_V10 ((index), (x));\
151 #define GET_H_CBIT_MOVE() GET_H_CBIT_MOVE_PRE_V32 ()
152 #define SET_H_CBIT_MOVE(x) \
154 SET_H_CBIT_MOVE_PRE_V32 ((x));\
156 #define GET_H_CBIT_MOVE_PRE_V32() CPU (h_cbit)
157 #define SET_H_CBIT_MOVE_PRE_V32(x) \
161 #define GET_H_VBIT_MOVE() GET_H_VBIT_MOVE_PRE_V32 ()
162 #define SET_H_VBIT_MOVE(x) \
164 SET_H_VBIT_MOVE_PRE_V32 ((x));\
166 #define GET_H_VBIT_MOVE_PRE_V32() CPU (h_vbit)
167 #define SET_H_VBIT_MOVE_PRE_V32(x) \
171 #define GET_H_ZBIT_MOVE() GET_H_ZBIT_MOVE_PRE_V32 ()
172 #define SET_H_ZBIT_MOVE(x) \
174 SET_H_ZBIT_MOVE_PRE_V32 ((x));\
176 #define GET_H_ZBIT_MOVE_PRE_V32() CPU (h_zbit)
177 #define SET_H_ZBIT_MOVE_PRE_V32(x) \
181 #define GET_H_NBIT_MOVE() GET_H_NBIT_MOVE_PRE_V32 ()
182 #define SET_H_NBIT_MOVE(x) \
184 SET_H_NBIT_MOVE_PRE_V32 ((x));\
186 #define GET_H_NBIT_MOVE_PRE_V32() CPU (h_nbit)
187 #define SET_H_NBIT_MOVE_PRE_V32(x) \
191 #define GET_H_IBIT() CPU (h_ibit_pre_v32)
192 #define SET_H_IBIT(x) \
194 CPU (h_ibit_pre_v32) = (x);\
196 #define GET_H_UBIT() CPU (h_ubit_pre_v32)
197 #define SET_H_UBIT(x) \
199 CPU (h_ubit_pre_v32) = (x);\
201 #define GET_H_INSN_PREFIXED_P() CPU (h_insn_prefixed_p_pre_v32)
202 #define SET_H_INSN_PREFIXED_P(x) \
204 CPU (h_insn_prefixed_p_pre_v32) = (x);\
207 /* Cover fns for register access. */
208 BI crisv10f_h_v32_non_v32_get (SIM_CPU *);
209 void crisv10f_h_v32_non_v32_set (SIM_CPU *, BI);
210 USI crisv10f_h_pc_get (SIM_CPU *);
211 void crisv10f_h_pc_set (SIM_CPU *, USI);
212 SI crisv10f_h_gr_get (SIM_CPU *, UINT);
213 void crisv10f_h_gr_set (SIM_CPU *, UINT, SI);
214 SI crisv10f_h_gr_pc_get (SIM_CPU *, UINT);
215 void crisv10f_h_gr_pc_set (SIM_CPU *, UINT, SI);
216 SI crisv10f_h_gr_real_pc_get (SIM_CPU *, UINT);
217 void crisv10f_h_gr_real_pc_set (SIM_CPU *, UINT, SI);
218 SI crisv10f_h_raw_gr_pc_get (SIM_CPU *, UINT);
219 void crisv10f_h_raw_gr_pc_set (SIM_CPU *, UINT, SI);
220 SI crisv10f_h_sr_get (SIM_CPU *, UINT);
221 void crisv10f_h_sr_set (SIM_CPU *, UINT, SI);
222 SI crisv10f_h_sr_v10_get (SIM_CPU *, UINT);
223 void crisv10f_h_sr_v10_set (SIM_CPU *, UINT, SI);
224 BI crisv10f_h_cbit_get (SIM_CPU *);
225 void crisv10f_h_cbit_set (SIM_CPU *, BI);
226 BI crisv10f_h_cbit_move_get (SIM_CPU *);
227 void crisv10f_h_cbit_move_set (SIM_CPU *, BI);
228 BI crisv10f_h_cbit_move_pre_v32_get (SIM_CPU *);
229 void crisv10f_h_cbit_move_pre_v32_set (SIM_CPU *, BI);
230 BI crisv10f_h_vbit_get (SIM_CPU *);
231 void crisv10f_h_vbit_set (SIM_CPU *, BI);
232 BI crisv10f_h_vbit_move_get (SIM_CPU *);
233 void crisv10f_h_vbit_move_set (SIM_CPU *, BI);
234 BI crisv10f_h_vbit_move_pre_v32_get (SIM_CPU *);
235 void crisv10f_h_vbit_move_pre_v32_set (SIM_CPU *, BI);
236 BI crisv10f_h_zbit_get (SIM_CPU *);
237 void crisv10f_h_zbit_set (SIM_CPU *, BI);
238 BI crisv10f_h_zbit_move_get (SIM_CPU *);
239 void crisv10f_h_zbit_move_set (SIM_CPU *, BI);
240 BI crisv10f_h_zbit_move_pre_v32_get (SIM_CPU *);
241 void crisv10f_h_zbit_move_pre_v32_set (SIM_CPU *, BI);
242 BI crisv10f_h_nbit_get (SIM_CPU *);
243 void crisv10f_h_nbit_set (SIM_CPU *, BI);
244 BI crisv10f_h_nbit_move_get (SIM_CPU *);
245 void crisv10f_h_nbit_move_set (SIM_CPU *, BI);
246 BI crisv10f_h_nbit_move_pre_v32_get (SIM_CPU *);
247 void crisv10f_h_nbit_move_pre_v32_set (SIM_CPU *, BI);
248 BI crisv10f_h_xbit_get (SIM_CPU *);
249 void crisv10f_h_xbit_set (SIM_CPU *, BI);
250 BI crisv10f_h_ibit_get (SIM_CPU *);
251 void crisv10f_h_ibit_set (SIM_CPU *, BI);
252 BI crisv10f_h_ibit_pre_v32_get (SIM_CPU *);
253 void crisv10f_h_ibit_pre_v32_set (SIM_CPU *, BI);
254 BI crisv10f_h_pbit_get (SIM_CPU *);
255 void crisv10f_h_pbit_set (SIM_CPU *, BI);
256 BI crisv10f_h_ubit_get (SIM_CPU *);
257 void crisv10f_h_ubit_set (SIM_CPU *, BI);
258 BI crisv10f_h_ubit_pre_v32_get (SIM_CPU *);
259 void crisv10f_h_ubit_pre_v32_set (SIM_CPU *, BI);
260 BI crisv10f_h_insn_prefixed_p_get (SIM_CPU *);
261 void crisv10f_h_insn_prefixed_p_set (SIM_CPU *, BI);
262 BI crisv10f_h_insn_prefixed_p_pre_v32_get (SIM_CPU *);
263 void crisv10f_h_insn_prefixed_p_pre_v32_set (SIM_CPU *, BI);
264 SI crisv10f_h_prefixreg_pre_v32_get (SIM_CPU *);
265 void crisv10f_h_prefixreg_pre_v32_set (SIM_CPU *, SI);
267 /* These must be hand-written. */
268 extern CPUREG_FETCH_FN crisv10f_fetch_register;
269 extern CPUREG_STORE_FN crisv10f_store_register;
273 } MODEL_CRISV10_DATA;
275 /* Instruction argument buffer. */
278 struct { /* no operands */
288 IADDR i_o_word_pcrel;
297 unsigned char in_h_gr_SI_14;
298 unsigned char out_h_gr_SI_14;
299 } sfmt_move_m_spplus_p8;
306 INT f_indir_pc__dword;
308 unsigned char out_Pd;
309 } sfmt_move_c_sprv10_p9;
311 INT f_indir_pc__word;
313 unsigned char out_Pd;
314 } sfmt_move_c_sprv10_p5;
318 unsigned char out_Rd;
321 INT f_indir_pc__dword;
324 unsigned char out_Rd;
327 INT f_indir_pc__word;
330 unsigned char out_Rd;
333 INT f_indir_pc__byte;
336 unsigned char out_Rd;
342 unsigned char out_Rd;
348 unsigned char out_h_gr_SI_index_of__DFLT_Rd;
351 INT f_indir_pc__dword;
354 unsigned char out_h_gr_SI_index_of__DFLT_Rd;
357 INT f_indir_pc__word;
360 unsigned char out_h_gr_SI_index_of__DFLT_Rd;
363 INT f_indir_pc__byte;
366 unsigned char out_h_gr_SI_index_of__DFLT_Rd;
372 unsigned char out_h_gr_SI_index_of__DFLT_Rs;
373 } sfmt_move_spr_rv10;
378 unsigned char out_h_gr_SI_index_of__DFLT_Rd;
385 unsigned char out_h_gr_SI_index_of__DFLT_Rd;
392 unsigned char out_Rd;
393 unsigned char out_h_sr_SI_7;
401 unsigned char out_Rs;
402 } sfmt_move_spr_mv10;
408 unsigned char out_Pd;
409 unsigned char out_Rs;
410 } sfmt_move_m_sprv10;
417 unsigned char out_Rd;
418 unsigned char out_Rs;
426 unsigned char out_Rs;
427 unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd;
435 unsigned char out_Rs;
436 unsigned char out_h_gr_SI_0;
437 unsigned char out_h_gr_SI_1;
438 unsigned char out_h_gr_SI_10;
439 unsigned char out_h_gr_SI_11;
440 unsigned char out_h_gr_SI_12;
441 unsigned char out_h_gr_SI_13;
442 unsigned char out_h_gr_SI_14;
443 unsigned char out_h_gr_SI_2;
444 unsigned char out_h_gr_SI_3;
445 unsigned char out_h_gr_SI_4;
446 unsigned char out_h_gr_SI_5;
447 unsigned char out_h_gr_SI_6;
448 unsigned char out_h_gr_SI_7;
449 unsigned char out_h_gr_SI_8;
450 unsigned char out_h_gr_SI_9;
458 unsigned char in_h_gr_SI_0;
459 unsigned char in_h_gr_SI_1;
460 unsigned char in_h_gr_SI_10;
461 unsigned char in_h_gr_SI_11;
462 unsigned char in_h_gr_SI_12;
463 unsigned char in_h_gr_SI_13;
464 unsigned char in_h_gr_SI_14;
465 unsigned char in_h_gr_SI_15;
466 unsigned char in_h_gr_SI_2;
467 unsigned char in_h_gr_SI_3;
468 unsigned char in_h_gr_SI_4;
469 unsigned char in_h_gr_SI_5;
470 unsigned char in_h_gr_SI_6;
471 unsigned char in_h_gr_SI_7;
472 unsigned char in_h_gr_SI_8;
473 unsigned char in_h_gr_SI_9;
474 unsigned char out_Rs;
477 /* Writeback handler. */
479 /* Pointer to argbuf entry for insn whose results need writing back. */
480 const struct argbuf *abuf;
482 /* x-before handler */
484 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
487 /* x-after handler */
491 /* This entry is used to terminate each pbb. */
493 /* Number of insns in pbb. */
495 /* Next pbb to execute. */
497 SCACHE *branch_target;
502 /* The ARGBUF struct. */
504 /* These are the baseclass definitions. */
509 /* ??? Temporary hack for skip insns. */
512 /* cpu specific data follows */
515 union sem_fields fields;
520 ??? SCACHE used to contain more than just argbuf. We could delete the
521 type entirely and always just use ARGBUF, but for future concerns and as
522 a level of abstraction it is left in. */
525 struct argbuf argbuf;
528 /* Macros to simplify extraction, reading and semantic code.
529 These define and assign the local vars that contain the insn's fields. */
531 #define EXTRACT_IFMT_EMPTY_VARS \
533 #define EXTRACT_IFMT_EMPTY_CODE \
536 #define EXTRACT_IFMT_NOP_VARS \
543 #define EXTRACT_IFMT_NOP_CODE \
545 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
546 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
547 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
548 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
549 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
551 #define EXTRACT_IFMT_MOVE_B_R_VARS \
558 #define EXTRACT_IFMT_MOVE_B_R_CODE \
560 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
561 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
562 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
563 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
564 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
566 #define EXTRACT_IFMT_MOVEPCR_VARS \
573 #define EXTRACT_IFMT_MOVEPCR_CODE \
575 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
576 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
577 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
578 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
579 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
581 #define EXTRACT_IFMT_MOVEQ_VARS \
587 #define EXTRACT_IFMT_MOVEQ_CODE \
589 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
590 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
591 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
592 f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6); \
594 #define EXTRACT_IFMT_MOVECBR_VARS \
596 INT f_indir_pc__byte; \
601 /* Contents of trailing part of insn. */ \
604 #define EXTRACT_IFMT_MOVECBR_CODE \
606 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
607 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
608 f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
609 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
610 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
611 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
612 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
614 #define EXTRACT_IFMT_MOVECWR_VARS \
616 INT f_indir_pc__word; \
621 /* Contents of trailing part of insn. */ \
624 #define EXTRACT_IFMT_MOVECWR_CODE \
626 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
627 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
628 f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
629 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
630 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
631 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
632 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
634 #define EXTRACT_IFMT_MOVECDR_VARS \
635 INT f_indir_pc__dword; \
641 /* Contents of trailing part of insn. */ \
644 #define EXTRACT_IFMT_MOVECDR_CODE \
646 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
647 f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
648 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
649 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
650 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
651 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
652 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
654 #define EXTRACT_IFMT_MOVUCBR_VARS \
656 INT f_indir_pc__byte; \
661 /* Contents of trailing part of insn. */ \
664 #define EXTRACT_IFMT_MOVUCBR_CODE \
666 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
667 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
668 f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
669 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
670 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
671 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
672 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
674 #define EXTRACT_IFMT_MOVUCWR_VARS \
676 INT f_indir_pc__word; \
681 /* Contents of trailing part of insn. */ \
684 #define EXTRACT_IFMT_MOVUCWR_CODE \
686 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
687 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
688 f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
689 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
690 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
691 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
692 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
694 #define EXTRACT_IFMT_ADDQ_VARS \
700 #define EXTRACT_IFMT_ADDQ_CODE \
702 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
703 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
704 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
705 f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6); \
707 #define EXTRACT_IFMT_CMP_M_B_M_VARS \
715 #define EXTRACT_IFMT_CMP_M_B_M_CODE \
717 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
718 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
719 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
720 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
721 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
722 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
724 #define EXTRACT_IFMT_MOVE_R_SPRV10_VARS \
731 #define EXTRACT_IFMT_MOVE_R_SPRV10_CODE \
733 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
734 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
735 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
736 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
737 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
739 #define EXTRACT_IFMT_MOVE_SPR_RV10_VARS \
746 #define EXTRACT_IFMT_MOVE_SPR_RV10_CODE \
748 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
749 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
750 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
751 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
752 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
754 #define EXTRACT_IFMT_RET_TYPE_VARS \
761 #define EXTRACT_IFMT_RET_TYPE_CODE \
763 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
764 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
765 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
766 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
767 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
769 #define EXTRACT_IFMT_MOVE_M_SPRV10_VARS \
777 #define EXTRACT_IFMT_MOVE_M_SPRV10_CODE \
779 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
780 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
781 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
782 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
783 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
784 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
786 #define EXTRACT_IFMT_MOVE_C_SPRV10_P5_VARS \
788 INT f_indir_pc__word; \
793 /* Contents of trailing part of insn. */ \
796 #define EXTRACT_IFMT_MOVE_C_SPRV10_P5_CODE \
798 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
799 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
800 f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
801 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
802 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
803 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
804 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
806 #define EXTRACT_IFMT_MOVE_C_SPRV10_P9_VARS \
807 INT f_indir_pc__dword; \
813 /* Contents of trailing part of insn. */ \
816 #define EXTRACT_IFMT_MOVE_C_SPRV10_P9_CODE \
818 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
819 f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
820 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
821 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
822 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
823 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
824 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
826 #define EXTRACT_IFMT_MOVE_SPR_MV10_VARS \
834 #define EXTRACT_IFMT_MOVE_SPR_MV10_CODE \
836 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
837 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
838 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
839 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
840 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
841 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
843 #define EXTRACT_IFMT_SBFS_VARS \
851 #define EXTRACT_IFMT_SBFS_CODE \
853 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
854 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
855 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
856 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
857 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
858 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
860 #define EXTRACT_IFMT_SWAP_VARS \
867 #define EXTRACT_IFMT_SWAP_CODE \
869 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
870 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
871 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
872 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
873 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
875 #define EXTRACT_IFMT_ASRQ_VARS \
882 #define EXTRACT_IFMT_ASRQ_CODE \
884 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
885 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
886 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
887 f_b5 = EXTRACT_LSB0_UINT (insn, 16, 5, 1); \
888 f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5); \
890 #define EXTRACT_IFMT_SETF_VARS \
898 #define EXTRACT_IFMT_SETF_CODE \
900 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
901 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
902 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
903 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
904 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
905 f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));\
907 #define EXTRACT_IFMT_BCC_B_VARS \
915 #define EXTRACT_IFMT_BCC_B_CODE \
917 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
918 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
919 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
920 f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
921 f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
925 tmp_abslo = ((f_disp9_lo) << (1));\
926 tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
927 f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\
930 #define EXTRACT_IFMT_BA_B_VARS \
938 #define EXTRACT_IFMT_BA_B_CODE \
940 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
941 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
942 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
943 f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
944 f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
948 tmp_abslo = ((f_disp9_lo) << (1));\
949 tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
950 f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\
953 #define EXTRACT_IFMT_BCC_W_VARS \
955 SI f_indir_pc__word_pcrel; \
960 /* Contents of trailing part of insn. */ \
963 #define EXTRACT_IFMT_BCC_W_CODE \
965 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
966 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
967 f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \
968 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
969 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
970 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
971 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
973 #define EXTRACT_IFMT_BA_W_VARS \
975 SI f_indir_pc__word_pcrel; \
980 /* Contents of trailing part of insn. */ \
983 #define EXTRACT_IFMT_BA_W_CODE \
985 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
986 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
987 f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \
988 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
989 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
990 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
991 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
993 #define EXTRACT_IFMT_JUMP_C_VARS \
994 INT f_indir_pc__dword; \
1000 /* Contents of trailing part of insn. */ \
1002 unsigned int length;
1003 #define EXTRACT_IFMT_JUMP_C_CODE \
1005 word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1006 f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
1007 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1008 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1009 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1010 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1011 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1013 #define EXTRACT_IFMT_BREAK_VARS \
1019 unsigned int length;
1020 #define EXTRACT_IFMT_BREAK_CODE \
1022 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1023 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1024 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1025 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1026 f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1028 #define EXTRACT_IFMT_SCC_VARS \
1034 unsigned int length;
1035 #define EXTRACT_IFMT_SCC_CODE \
1037 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1038 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1039 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1040 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1041 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1043 #define EXTRACT_IFMT_ADDOQ_VARS \
1048 unsigned int length;
1049 #define EXTRACT_IFMT_ADDOQ_CODE \
1051 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1052 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1053 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1054 f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
1056 #define EXTRACT_IFMT_BDAPQPC_VARS \
1061 unsigned int length;
1062 #define EXTRACT_IFMT_BDAPQPC_CODE \
1064 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1065 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1066 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1067 f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
1069 /* Collection of various things for the trace handler to use. */
1071 typedef struct trace_record {
1076 #endif /* CPU_CRISV10F_H */