1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2014 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include <sys/types.h>
36 #include "targ-vals.h"
38 extern char *strrchr ();
109 /* The following bits in the PSR _can't_ be set by instructions such
111 PSR_HW_MASK = (PSR_MASK)
114 /* cond Code Condition True State
115 * EQ Equal Z flag is 1
116 * NE Not Equal Z flag is 0
117 * CS Carry Set C flag is 1
118 * CC Carry Clear C flag is 0
119 * HI Higher L flag is 1
120 * LS Lower or Same L flag is 0
121 * GT Greater Than N flag is 1
122 * LE Less Than or Equal To N flag is 0
123 * FS Flag Set F flag is 1
124 * FC Flag Clear F flag is 0
125 * LO Lower Z and L flags are 0
126 * HS Higher or Same Z or L flag is 1
127 * LT Less Than Z and N flags are 0
128 * GE Greater Than or Equal To Z or N flag is 1. */
130 int cond_stat(int cc)
134 case 0: return PSR_Z; break;
135 case 1: return !PSR_Z; break;
136 case 2: return PSR_C; break;
137 case 3: return !PSR_C; break;
138 case 4: return PSR_L; break;
139 case 5: return !PSR_L; break;
140 case 6: return PSR_N; break;
141 case 7: return !PSR_N; break;
142 case 8: return PSR_F; break;
143 case 9: return !PSR_F; break;
144 case 10: return !PSR_Z && !PSR_L; break;
145 case 11: return PSR_Z || PSR_L; break;
146 case 12: return !PSR_Z && !PSR_N; break;
147 case 13: return PSR_Z || PSR_N; break;
148 case 14: return 1; break; /*ALWAYS. */
150 // case NEVER: return false; break;
152 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
160 move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p)
162 /* A MASK bit is set when the corresponding bit in the CR should
164 /* This assumes that (VAL & MASK) == 0. */
173 (*cr16_callback->printf_filtered)
175 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC);
176 State.exception = SIGILL;
178 /* keep an up-to-date psw around for tracing. */
179 State.trace.psw = (State.trace.psw & mask) | val;
184 /* only issue an update if the register is being changed. */
185 if ((State.cregs[cr] & ~mask) != val)
186 SLOT_PEND_MASK (State.cregs[cr], mask, val);
192 static void trace_input_func (char *name,
197 #define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (name, in1, in2, in3); } while (0)
199 #ifndef SIZE_INSTRUCTION
200 #define SIZE_INSTRUCTION 8
203 #ifndef SIZE_OPERANDS
204 #define SIZE_OPERANDS 18
208 #define SIZE_VALUES 13
211 #ifndef SIZE_LOCATION
212 #define SIZE_LOCATION 20
219 #ifndef SIZE_LINE_NUMBER
220 #define SIZE_LINE_NUMBER 2
224 trace_input_func (name, in1, in2, in3)
237 const char *filename;
238 const char *functionname;
239 unsigned int linenumber;
242 if ((cr16_debug & DEBUG_TRACE) == 0)
245 switch (State.ins_type)
248 case INS_UNKNOWN: type = " ?"; break;
251 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0)
252 (*cr16_callback->printf_filtered) (cr16_callback,
254 SIZE_PC, (unsigned)PC,
256 SIZE_INSTRUCTION, name);
261 byte_pc = decode_pc ();
262 if (text && byte_pc >= text_start && byte_pc < text_end)
264 filename = (const char *)0;
265 functionname = (const char *)0;
267 if (bfd_find_nearest_line (prog_bfd, text, (struct bfd_symbol **)0, byte_pc - text_start,
268 &filename, &functionname, &linenumber))
273 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
278 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
279 p += SIZE_LINE_NUMBER+2;
284 sprintf (p, "%s ", functionname);
289 char *q = strrchr (filename, '/');
290 sprintf (p, "%s ", (q) ? q+1 : filename);
299 (*cr16_callback->printf_filtered) (cr16_callback,
300 "0x%.*x %s: %-*.*s %-*s ",
301 SIZE_PC, (unsigned)PC,
303 SIZE_LOCATION, SIZE_LOCATION, buf,
304 SIZE_INSTRUCTION, name);
312 for (i = 0; i < 3; i++)
321 sprintf (p, "%sr%d", comma, OP[i]);
327 sprintf (p, "%scr%d", comma, OP[i]);
333 sprintf (p, "%s%d", comma, OP[i]);
339 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
345 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
351 sprintf (p, "%s@r%d", comma, OP[i]);
357 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
363 sprintf (p, "%s@%d", comma, OP[i]);
370 if ((cr16_debug & DEBUG_VALUES) == 0)
374 (*cr16_callback->printf_filtered) (cr16_callback, "%s", buf);
379 (*cr16_callback->printf_filtered) (cr16_callback, "%-*s", SIZE_OPERANDS, buf);
382 for (i = 0; i < 3; i++)
388 (*cr16_callback->printf_filtered) (cr16_callback, "%*s", SIZE_VALUES, "");
392 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
393 (uint16) GPR (OP[i]));
397 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
398 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
402 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
403 (uint16) CREG (OP[i]));
407 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
412 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
413 (uint16)SEXT4(OP[i]));
417 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
418 (uint16)SEXT3(OP[i]));
422 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
424 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
425 (uint16)GPR (OP[i + 1]));
432 (*cr16_callback->flush_stdout) (cr16_callback);
436 do_trace_output_flush (void)
438 (*cr16_callback->flush_stdout) (cr16_callback);
442 do_trace_output_finish (void)
444 (*cr16_callback->printf_filtered) (cr16_callback,
445 " F0=%d F1=%d C=%d\n",
446 (State.trace.psw & PSR_F_BIT) != 0,
447 (State.trace.psw & PSR_F_BIT) != 0,
448 (State.trace.psw & PSR_C_BIT) != 0);
449 (*cr16_callback->flush_stdout) (cr16_callback);
453 trace_output_40 (uint64 val)
455 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
457 (*cr16_callback->printf_filtered) (cr16_callback,
458 " :: %*s0x%.2x%.8lx",
461 ((int)(val >> 32) & 0xff),
462 ((unsigned long) val) & 0xffffffff);
463 do_trace_output_finish ();
468 trace_output_32 (uint32 val)
470 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
472 (*cr16_callback->printf_filtered) (cr16_callback,
477 do_trace_output_finish ();
482 trace_output_16 (uint16 val)
484 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
486 (*cr16_callback->printf_filtered) (cr16_callback,
491 do_trace_output_finish ();
498 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
500 (*cr16_callback->printf_filtered) (cr16_callback, "\n");
501 do_trace_output_flush ();
508 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
510 (*cr16_callback->printf_filtered) (cr16_callback,
514 do_trace_output_finish ();
522 #define trace_input(NAME, IN1, IN2, IN3)
523 #define trace_output(RESULT)
531 uint8 a = OP[0] & 0xff;
532 uint16 b = (GPR (OP[1])) & 0xff;
533 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
534 tmp = (a + b) & 0xff;
535 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
536 trace_output_16 (tmp);
544 uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
545 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
546 tmp = (a + b) & 0xff;
547 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
548 trace_output_16 (tmp);
555 uint8 a = (GPR (OP[0])) & 0xff;
556 uint8 b = (GPR (OP[1])) & 0xff;
557 uint16 tmp = (a + b) & 0xff;
558 trace_input ("addub", OP_REG, OP_REG, OP_VOID);
559 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
560 trace_output_16 (tmp);
568 uint16 b = GPR (OP[1]);
569 uint16 tmp = (a + b);
570 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
571 SET_GPR (OP[1], tmp);
572 trace_output_16 (tmp);
580 uint16 b = GPR (OP[1]);
581 uint16 tmp = (a + b);
582 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
583 SET_GPR (OP[1], tmp);
584 trace_output_16 (tmp);
591 uint16 a = GPR (OP[0]);
592 uint16 b = GPR (OP[1]);
593 uint16 tmp = (a + b);
594 trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
595 SET_GPR (OP[1], tmp);
596 trace_output_16 (tmp);
604 uint8 b = (GPR (OP[1]) & 0xff);
605 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
606 uint16 tmp = (a + b) & 0xff;
607 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
608 SET_PSR_C (tmp > 0xFF);
609 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
610 trace_output_16 (tmp);
617 uint8 a = (OP[0]) & 0xff;
618 uint8 b = (GPR (OP[1]) & 0xff);
619 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
620 uint16 tmp = (a + b) & 0xff;
621 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
622 SET_PSR_C (tmp > 0xFF);
623 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
624 trace_output_16 (tmp);
631 uint8 a = (GPR (OP[0]) & 0xff);
632 uint8 b = (GPR (OP[1]) & 0xff);
633 trace_input ("addb", OP_REG, OP_REG, OP_VOID);
634 uint16 tmp = (a + b) & 0xff;
635 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
636 SET_PSR_C (tmp > 0xFF);
637 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
638 trace_output_16 (tmp);
646 uint16 tmp, b = GPR (OP[1]);
647 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
649 SET_GPR (OP[1], tmp);
650 SET_PSR_C (tmp > 0xFFFF);
651 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
652 trace_output_16 (tmp);
660 uint16 tmp, b = GPR (OP[1]);
662 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
663 SET_GPR (OP[1], tmp);
664 SET_PSR_C (tmp > 0xFFFF);
665 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
666 trace_output_16 (tmp);
673 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
674 trace_input ("addw", OP_REG, OP_REG, OP_VOID);
676 SET_GPR (OP[1], tmp);
677 SET_PSR_C (tmp > 0xFFFF);
678 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
679 trace_output_16 (tmp);
686 uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
687 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
688 tmp = (a + b + PSR_C) & 0xff;
689 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
690 SET_PSR_C (tmp > 0xFF);
691 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
692 trace_output_16 (tmp);
699 int8 a = OP[0] & 0xff;
700 uint8 b = (GPR (OP[1])) & 0xff;
701 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
702 uint8 tmp = (a + b + PSR_C) & 0xff;
703 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
704 SET_PSR_C (tmp > 0xFF);
705 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
706 trace_output_16 (tmp);
713 uint8 a = (GPR (OP[0])) & 0xff;
714 uint8 b = (GPR (OP[1])) & 0xff;
715 trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
716 uint8 tmp = (a + b + PSR_C) & 0xff;
717 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
718 SET_PSR_C (tmp > 0xFF);
719 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
720 trace_output_16 (tmp);
728 uint16 b = GPR (OP[1]);
729 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
730 uint16 tmp = (a + b + PSR_C);
731 SET_GPR (OP[1], tmp);
732 SET_PSR_C (tmp > 0xFFFF);
733 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
734 trace_output_16 (tmp);
742 uint16 b = GPR (OP[1]);
743 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
744 uint16 tmp = (a + b + PSR_C);
745 SET_GPR (OP[1], tmp);
746 SET_PSR_C (tmp > 0xFFFF);
747 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
748 trace_output_16 (tmp);
755 uint16 a = GPR (OP[1]);
756 uint16 b = GPR (OP[1]);
757 trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
758 uint16 tmp = (a + b + PSR_C);
759 SET_GPR (OP[1], tmp);
760 SET_PSR_C (tmp > 0xFFFF);
761 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
762 trace_output_16 (tmp);
770 uint32 b = GPR32 (OP[1]);
771 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
772 uint32 tmp = (a + b);
773 SET_GPR32 (OP[1], tmp);
774 SET_PSR_C (tmp > 0xFFFFFFFF);
775 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
776 trace_output_32 (tmp);
783 int32 a = (SEXT16(OP[0]));
784 uint32 b = GPR32 (OP[1]);
785 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
786 uint32 tmp = (a + b);
787 SET_GPR32 (OP[1], tmp);
788 SET_PSR_C (tmp > 0xFFFFFFFF);
789 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
790 trace_output_32 (tmp);
797 uint32 a = GPR32 (OP[0]);
798 uint32 b = GPR32 (OP[1]);
799 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
800 uint32 tmp = (a + b);
801 SET_GPR32 (OP[1], tmp);
802 trace_output_32 (tmp);
803 SET_PSR_C (tmp > 0xFFFFFFFF);
804 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
812 uint32 b = GPR32 (OP[1]);
814 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
816 SET_GPR32 (OP[1], tmp);
817 SET_PSR_C (tmp > 0xFFFFFFFF);
818 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
819 trace_output_32 (tmp);
827 uint32 b = GPR32 (OP[1]);
829 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
831 SET_GPR32 (OP[1], tmp);
832 SET_PSR_C (tmp > 0xFFFFFFFF);
833 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
834 trace_output_32 (tmp);
841 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
842 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
844 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
845 trace_output_16 (tmp);
852 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
853 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
855 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
856 trace_output_16 (tmp);
863 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
864 trace_input ("andb", OP_REG, OP_REG, OP_VOID);
866 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
867 trace_output_16 (tmp);
874 uint16 tmp, a = OP[0], b = GPR (OP[1]);
875 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
877 SET_GPR (OP[1], tmp);
878 trace_output_16 (tmp);
885 uint16 tmp, a = OP[0], b = GPR (OP[1]);
886 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
888 SET_GPR (OP[1], tmp);
889 trace_output_16 (tmp);
896 uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]);
897 trace_input ("andw", OP_REG, OP_REG, OP_VOID);
899 SET_GPR (OP[1], tmp);
900 trace_output_16 (tmp);
907 uint32 tmp, a = OP[0], b = GPR32 (OP[1]);
908 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
910 SET_GPR32 (OP[1], tmp);
911 trace_output_32 (tmp);
918 uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
919 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
921 SET_GPR32 (OP[1], tmp);
922 trace_output_32 (tmp);
929 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
930 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
932 SET_GPR32 (OP[1], tmp);
933 trace_output_32 (tmp);
940 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
941 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
943 SET_GPR32 (OP[1], tmp);
944 trace_output_32 (tmp);
951 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
952 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
954 SET_GPR32 (OP[1], tmp);
955 trace_output_32 (tmp);
962 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
963 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
965 SET_GPR32 (OP[1], tmp);
966 trace_output_32 (tmp);
974 uint32 tmp, cc = cond_stat (OP[0]);
975 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
979 tmp = (PC - (OP[1]));
981 tmp = (PC + (OP[1]));
982 /* If the resulting PC value is less than 0x00_0000 or greater
983 than 0xFF_FFFF, this instruction causes an IAD trap.*/
985 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
987 State.exception = SIG_CR16_BUS;
988 State.pc_changed = 1; /* Don't increment the PC. */
989 trace_output_void ();
995 sign_flag = 0; /* Reset sign_flag. */
996 trace_output_32 (tmp);
1003 uint32 tmp, cc = cond_stat (OP[0]);
1004 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
1011 /* If the resulting PC value is less than 0x00_0000 or greater
1012 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1014 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1016 State.exception = SIG_CR16_BUS;
1017 State.pc_changed = 1; /* Don't increment the PC. */
1018 trace_output_void ();
1024 sign_flag = 0; /* Reset sign_flag. */
1025 trace_output_32 (tmp);
1032 uint32 tmp, cc = cond_stat (OP[0]);
1033 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
1037 tmp = (PC - (OP[1]));
1039 tmp = (PC + (OP[1]));
1040 /* If the resulting PC value is less than 0x00_0000 or greater
1041 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1043 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1045 State.exception = SIG_CR16_BUS;
1046 State.pc_changed = 1; /* Don't increment the PC. */
1047 trace_output_void ();
1053 sign_flag = 0; /* Reset sign_flag. */
1054 trace_output_32 (tmp);
1062 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
1063 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
1064 SET_GPR32 (14, tmp);
1066 tmp = (PC - (OP[1]));
1068 tmp = (PC + (OP[1]));
1070 /* If the resulting PC value is less than 0x00_0000 or greater
1071 than 0xFF_FFFF, this instruction causes an IAD trap. */
1073 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1075 State.exception = SIG_CR16_BUS;
1076 State.pc_changed = 1; /* Don't increment the PC. */
1077 trace_output_void ();
1082 sign_flag = 0; /* Reset sign_flag. */
1083 trace_output_32 (tmp);
1092 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
1093 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
1094 SET_GPR32 (OP[0], tmp);
1096 tmp = ((PC) - (OP[1]));
1098 tmp = ((PC) + (OP[1]));
1099 /* If the resulting PC value is less than 0x00_0000 or greater
1100 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1102 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1104 State.exception = SIG_CR16_BUS;
1105 State.pc_changed = 1; /* Don't increment the PC. */
1106 trace_output_void ();
1111 sign_flag = 0; /* Reset sign_flag. */
1112 trace_output_32 (tmp);
1120 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
1121 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
1122 tmp = GPR32 (OP[1]);
1123 tmp = SEXT24(tmp << 1);
1124 /* If the resulting PC value is less than 0x00_0000 or greater
1125 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1127 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1129 State.exception = SIG_CR16_BUS;
1130 State.pc_changed = 1; /* Don't increment the PC. */
1131 trace_output_void ();
1137 trace_output_32 (tmp);
1146 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
1147 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
1148 tmp = GPR32 (OP[0]);
1149 tmp = SEXT24(tmp << 1);
1150 /* If the resulting PC value is less than 0x00_0000 or greater
1151 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1153 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1155 State.exception = SIG_CR16_BUS;
1156 State.pc_changed = 1; /* Don't increment the PC. */
1157 trace_output_void ();
1163 trace_output_32 (tmp);
1172 uint8 a = (GPR (OP[0]) & 0xFF);
1173 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
1178 addr = (PC - OP[1]);
1180 addr = (PC + OP[1]);
1184 sign_flag = 0; /* Reset sign_flag. */
1185 trace_output_void ();
1193 uint8 a = (GPR (OP[0]) & 0xFF);
1194 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
1199 addr = (PC - OP[1]);
1201 addr = (PC + OP[1]);
1205 sign_flag = 0; /* Reset sign_flag. */
1206 trace_output_void ();
1214 uint16 a = GPR (OP[0]);
1215 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
1220 addr = (PC - OP[1]);
1222 addr = (PC + OP[1]);
1226 sign_flag = 0; /* Reset sign_flag. */
1227 trace_output_void ();
1235 uint16 a = GPR (OP[0]);
1236 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
1241 addr = (PC - OP[1]);
1243 addr = (PC + OP[1]);
1247 sign_flag = 0; /* Reset sign_flag. */
1248 trace_output_void ();
1257 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
1260 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1261 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1263 trace_output_32 (tmp);
1271 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
1274 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1275 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1277 trace_output_32 (tmp);
1285 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
1288 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1289 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1291 trace_output_32 (tmp);
1299 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
1302 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1303 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1305 trace_output_32 (tmp);
1313 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
1316 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1317 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1319 trace_output_32 (tmp);
1327 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
1330 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1331 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1333 trace_output_32 (tmp);
1341 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
1344 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1345 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1347 trace_output_32 (tmp);
1355 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
1358 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1359 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1361 trace_output_32 (tmp);
1370 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
1373 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1374 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1376 trace_output_32 (tmp);
1384 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
1387 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1388 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1390 trace_output_32 (tmp);
1398 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
1399 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1401 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1402 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1404 trace_output_32 (tmp);
1412 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
1413 if (((PSR_Z) == 1) | ((PSR_L) == 1))
1415 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1416 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1418 trace_output_32 (tmp);
1426 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
1427 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1429 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1430 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1432 trace_output_32 (tmp);
1440 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
1441 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1443 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1444 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1446 trace_output_32 (tmp);
1454 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
1455 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1456 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1457 trace_output_32 (tmp);
1465 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
1466 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1467 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1469 trace_output_32 (tmp);
1476 trace_input ("seq", OP_REG, OP_VOID, OP_VOID);
1481 trace_output_void ();
1487 trace_input ("sne", OP_REG, OP_VOID, OP_VOID);
1492 trace_output_void ();
1499 trace_input ("scs", OP_REG, OP_VOID, OP_VOID);
1504 trace_output_void ();
1511 trace_input ("scc", OP_REG, OP_VOID, OP_VOID);
1516 trace_output_void ();
1523 trace_input ("shi", OP_REG, OP_VOID, OP_VOID);
1528 trace_output_void ();
1535 trace_input ("sls", OP_REG, OP_VOID, OP_VOID);
1540 trace_output_void ();
1547 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID);
1552 trace_output_void ();
1559 trace_input ("sle", OP_REG, OP_VOID, OP_VOID);
1564 trace_output_void ();
1571 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID);
1576 trace_output_void ();
1583 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID);
1588 trace_output_void ();
1596 trace_input ("slo", OP_REG, OP_VOID, OP_VOID);
1597 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1601 trace_output_void ();
1608 trace_input ("shs", OP_REG, OP_VOID, OP_VOID);
1609 if ( ((PSR_Z) == 1) | ((PSR_L) == 1))
1613 trace_output_void ();
1620 trace_input ("slt", OP_REG, OP_VOID, OP_VOID);
1621 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1625 trace_output_void ();
1632 trace_input ("sge", OP_REG, OP_VOID, OP_VOID);
1633 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1637 trace_output_void ();
1644 uint8 a = OP[0] & 0xff;
1645 uint32 addr = OP[1], tmp;
1646 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1648 SET_PSR_F (tmp & (1 << a));
1649 tmp = tmp & ~(1 << a);
1651 trace_output_32 (tmp);
1658 uint8 a = OP[0] & 0xff;
1659 uint32 addr = OP[1], tmp;
1660 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1662 SET_PSR_F (tmp & (1 << a));
1663 tmp = tmp & ~(1 << a);
1665 trace_output_32 (tmp);
1672 uint8 a = (OP[0]) & 0xff;
1673 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1674 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1676 SET_PSR_F (tmp & (1 << a));
1677 tmp = tmp & ~(1 << a);
1679 trace_output_32 (addr);
1686 uint8 a = (OP[0]) & 0xff;
1687 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1688 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1690 SET_PSR_F (tmp & (1 << a));
1691 tmp = tmp & ~(1 << a);
1693 trace_output_32 (addr);
1700 uint8 a = (OP[0]) & 0xff;
1701 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1702 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1704 SET_PSR_F (tmp & (1 << a));
1705 tmp = tmp & ~(1 << a);
1707 trace_output_32 (addr);
1714 uint8 a = (OP[0]) & 0xff;
1715 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1716 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1718 SET_PSR_F (tmp & (1 << a));
1719 tmp = tmp & ~(1 << a);
1721 trace_output_32 (addr);
1728 uint8 a = (OP[0]) & 0xff;
1729 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1730 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1732 SET_PSR_F (tmp & (1 << a));
1733 tmp = tmp & ~(1 << a);
1735 trace_output_32 (addr);
1743 uint8 a = (OP[0]) & 0xff;
1744 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1745 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1747 SET_PSR_F (tmp & (1 << a));
1748 tmp = tmp & ~(1 << a);
1750 trace_output_32 (addr);
1757 uint8 a = (OP[0]) & 0xff;
1758 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1759 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1761 SET_PSR_F (tmp & (1 << a));
1762 tmp = tmp & ~(1 << a);
1764 trace_output_32 (addr);
1773 uint32 addr = OP[1], tmp;
1774 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1776 SET_PSR_F (tmp & (1 << a));
1777 tmp = tmp & ~(1 << a);
1779 trace_output_32 (tmp);
1787 uint32 addr = OP[1], tmp;
1788 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1790 SET_PSR_F (tmp & (1 << a));
1791 tmp = tmp & ~(1 << a);
1793 trace_output_32 (tmp);
1801 uint16 a = (OP[0]), tmp;
1802 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
1805 addr = (GPR32 (12)) + OP[2];
1807 addr = (GPR32 (13)) + OP[2];
1810 SET_PSR_F (tmp & (1 << a));
1811 tmp = tmp & ~(1 << a);
1813 trace_output_32 (addr);
1822 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1823 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1825 SET_PSR_F (tmp & (1 << a));
1826 tmp = tmp & ~(1 << a);
1828 trace_output_32 (addr);
1836 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1837 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1839 SET_PSR_F (tmp & (1 << a));
1840 tmp = tmp & ~(1 << a);
1842 trace_output_32 (addr);
1851 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1852 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1854 SET_PSR_F (tmp & (1 << a));
1855 tmp = tmp & ~(1 << a);
1857 trace_output_32 (addr);
1865 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1866 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1868 SET_PSR_F (tmp & (1 << a));
1869 tmp = tmp & ~(1 << a);
1871 trace_output_32 (addr);
1880 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1881 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1883 SET_PSR_F (tmp & (1 << a));
1884 tmp = tmp & ~(1 << a);
1886 trace_output_32 (addr);
1894 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1895 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1897 SET_PSR_F (tmp & (1 << a));
1898 tmp = tmp & ~(1 << a);
1900 trace_output_32 (addr);
1907 uint8 a = OP[0] & 0xff;
1908 uint32 addr = OP[1], tmp;
1909 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1911 SET_PSR_F (tmp & (1 << a));
1912 tmp = tmp | (1 << a);
1914 trace_output_32 (tmp);
1921 uint8 a = OP[0] & 0xff;
1922 uint32 addr = OP[1], tmp;
1923 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1925 SET_PSR_F (tmp & (1 << a));
1926 tmp = tmp | (1 << a);
1928 trace_output_32 (tmp);
1935 uint8 a = OP[0] & 0xff;
1936 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1937 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1939 SET_PSR_F (tmp & (1 << a));
1940 tmp = tmp | (1 << a);
1942 trace_output_32 (tmp);
1949 uint8 a = OP[0] & 0xff;
1950 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1951 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1953 SET_PSR_F (tmp & (1 << a));
1954 tmp = tmp | (1 << a);
1956 trace_output_32 (tmp);
1963 uint8 a = OP[0] & 0xff;
1964 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1965 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1967 SET_PSR_F (tmp & (1 << a));
1968 tmp = tmp | (1 << a);
1970 trace_output_32 (tmp);
1978 uint8 a = OP[0] & 0xff;
1979 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1980 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1982 SET_PSR_F (tmp & (1 << a));
1983 tmp = tmp | (1 << a);
1985 trace_output_32 (tmp);
1992 uint8 a = OP[0] & 0xff;
1993 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1994 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1996 SET_PSR_F (tmp & (1 << a));
1997 tmp = tmp | (1 << a);
1999 trace_output_32 (tmp);
2007 uint8 a = OP[0] & 0xff;
2008 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2009 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2011 SET_PSR_F (tmp & (1 << a));
2012 tmp = tmp | (1 << a);
2014 trace_output_32 (tmp);
2022 uint8 a = OP[0] & 0xff;
2023 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2024 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2026 SET_PSR_F (tmp & (1 << a));
2027 tmp = tmp | (1 << a);
2029 trace_output_32 (tmp);
2038 uint32 addr = OP[1], tmp;
2039 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2041 SET_PSR_F (tmp & (1 << a));
2042 tmp = tmp | (1 << a);
2044 trace_output_32 (tmp);
2052 uint32 addr = OP[1], tmp;
2053 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2055 SET_PSR_F (tmp & (1 << a));
2056 tmp = tmp | (1 << a);
2058 trace_output_32 (tmp);
2066 uint16 a = (OP[0]), tmp;
2067 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2070 addr = (GPR32 (12)) + OP[2];
2072 addr = (GPR32 (13)) + OP[2];
2075 SET_PSR_F (tmp & (1 << a));
2076 tmp = tmp | (1 << a);
2078 trace_output_32 (addr);
2086 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2087 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2089 SET_PSR_F (tmp & (1 << a));
2090 tmp = tmp | (1 << a);
2092 trace_output_32 (addr);
2100 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2101 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2103 SET_PSR_F (tmp & (1 << a));
2104 tmp = tmp | (1 << a);
2106 trace_output_32 (addr);
2114 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2115 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2117 SET_PSR_F (tmp & (1 << a));
2118 tmp = tmp | (1 << a);
2120 trace_output_32 (addr);
2128 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2129 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2131 SET_PSR_F (tmp & (1 << a));
2132 tmp = tmp | (1 << a);
2134 trace_output_32 (addr);
2142 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2143 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2145 SET_PSR_F (tmp & (1 << a));
2146 tmp = tmp | (1 << a);
2148 trace_output_32 (addr);
2156 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2157 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2159 SET_PSR_F (tmp & (1 << a));
2160 tmp = tmp | (1 << a);
2162 trace_output_32 (addr);
2170 uint8 a = OP[0] & 0xff;
2171 uint32 addr = OP[1], tmp;
2172 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2174 SET_PSR_F (tmp & (1 << a));
2175 trace_output_32 (tmp);
2182 uint8 a = OP[0] & 0xff;
2183 uint32 addr = OP[1], tmp;
2184 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2186 SET_PSR_F (tmp & (1 << a));
2187 trace_output_32 (tmp);
2194 uint8 a = (OP[0]) & 0xff;
2195 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2196 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
2198 SET_PSR_F (tmp & (1 << a));
2199 trace_output_32 (addr);
2206 uint8 a = (OP[0]) & 0xff;
2207 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2208 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2210 SET_PSR_F (tmp & (1 << a));
2211 trace_output_32 (addr);
2218 uint8 a = (OP[0]) & 0xff;
2219 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2220 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2222 SET_PSR_F (tmp & (1 << a));
2223 trace_output_32 (addr);
2230 uint8 a = (OP[0]) & 0xff;
2231 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2232 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2234 SET_PSR_F (tmp & (1 << a));
2235 trace_output_32 (addr);
2242 uint8 a = (OP[0]) & 0xff;
2243 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2244 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2246 SET_PSR_F (tmp & (1 << a));
2247 trace_output_32 (addr);
2254 uint8 a = (OP[0]) & 0xff;
2255 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2256 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2258 SET_PSR_F (tmp & (1 << a));
2259 trace_output_32 (addr);
2266 uint8 a = (OP[0]) & 0xff;
2267 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2268 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2270 SET_PSR_F (tmp & (1 << a));
2271 trace_output_32 (addr);
2280 uint32 addr = OP[1], tmp;
2281 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2283 SET_PSR_F (tmp & (1 << a));
2284 trace_output_32 (tmp);
2292 uint32 addr = OP[1], tmp;
2293 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2295 SET_PSR_F (tmp & (1 << a));
2296 trace_output_32 (tmp);
2305 uint16 a = (OP[0]), tmp;
2306 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2309 addr = (GPR32 (12)) + OP[2];
2311 addr = (GPR32 (13)) + OP[2];
2314 SET_PSR_F (tmp & (1 << a));
2315 trace_output_32 (addr);
2323 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2324 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2326 SET_PSR_F (tmp & (1 << a));
2327 trace_output_32 (addr);
2335 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2336 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2338 SET_PSR_F (tmp & (1 << a));
2339 trace_output_32 (addr);
2347 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2348 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2350 SET_PSR_F (tmp & (1 << a));
2351 trace_output_32 (addr);
2359 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2360 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2362 SET_PSR_F (tmp & (1 << a));
2363 trace_output_32 (addr);
2371 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2372 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2374 SET_PSR_F (tmp & (1 << a));
2375 trace_output_32 (addr);
2384 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2385 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2387 SET_PSR_F (tmp & (1 << a));
2388 trace_output_32 (addr);
2397 uint16 b = (GPR (OP[1]));
2398 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
2399 SET_PSR_F (b & (1 << a));
2400 trace_output_16 (b);
2407 uint16 a = GPR (OP[0]);
2408 uint16 b = (GPR (OP[1]));
2409 trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
2410 SET_PSR_F (b & (1 << a));
2411 trace_output_16 (b);
2419 uint8 a = (OP[0]) & 0xFF;
2420 uint8 b = (GPR (OP[1])) & 0xFF;
2421 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
2423 SET_PSR_N ((int8)a > (int8)b);
2425 trace_output_flag ();
2432 uint8 a = (OP[0]) & 0xFF;
2433 uint8 b = (GPR (OP[1])) & 0xFF;
2434 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
2436 SET_PSR_N ((int8)a > (int8)b);
2438 trace_output_flag ();
2445 uint8 a = (GPR (OP[0])) & 0xFF;
2446 uint8 b = (GPR (OP[1])) & 0xFF;
2447 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
2449 SET_PSR_N ((int8)a > (int8)b);
2451 trace_output_flag ();
2459 uint16 b = GPR (OP[1]);
2460 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
2462 SET_PSR_N ((int16)a > (int16)b);
2464 trace_output_flag ();
2472 uint16 b = GPR (OP[1]);
2473 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
2475 SET_PSR_N ((int16)a > (int16)b);
2477 trace_output_flag ();
2484 uint16 a = GPR (OP[0]) ;
2485 uint16 b = GPR (OP[1]) ;
2486 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
2488 SET_PSR_N ((int16)a > (int16)b);
2490 trace_output_flag ();
2498 uint32 b = GPR32 (OP[1]);
2499 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
2501 SET_PSR_N ((int32)a > (int32)b);
2503 trace_output_flag ();
2510 uint32 a = (SEXT16(OP[0]));
2511 uint32 b = GPR32 (OP[1]);
2512 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
2514 SET_PSR_N ((int32)a > (int32)b);
2516 trace_output_flag ();
2523 uint32 a = GPR32 (OP[0]) ;
2524 uint32 b = GPR32 (OP[1]) ;
2525 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
2527 SET_PSR_N ((int32)a > (int32)b);
2529 trace_output_flag ();
2537 uint32 b = GPR32 (OP[1]);
2538 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
2540 SET_PSR_N ((int32)a > (int32)b);
2542 trace_output_flag ();
2550 uint8 tmp = OP[0] & 0xFF;
2551 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
2552 uint16 a = (GPR (OP[1])) & 0xFF00;
2553 SET_GPR (OP[1], (a | tmp));
2554 trace_output_16 (tmp);
2561 uint8 tmp = OP[0] & 0xFF;
2562 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
2563 uint16 a = (GPR (OP[1])) & 0xFF00;
2564 SET_GPR (OP[1], (a | tmp));
2565 trace_output_16 (tmp);
2572 uint8 tmp = (GPR (OP[0])) & 0xFF;
2573 trace_input ("movb", OP_REG, OP_REG, OP_VOID);
2574 uint16 a = (GPR (OP[1])) & 0xFF00;
2575 SET_GPR (OP[1], (a | tmp));
2576 trace_output_16 (tmp);
2584 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
2585 SET_GPR (OP[1], (tmp & 0xffff));
2586 trace_output_16 (tmp);
2594 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
2595 SET_GPR (OP[1], (tmp & 0xffff));
2596 trace_output_16 (tmp);
2603 uint16 tmp = GPR (OP[0]);
2604 trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
2605 uint32 a = GPR32 (OP[1]);
2606 a = (a & 0xffff0000) | tmp;
2607 SET_GPR32 (OP[1], a);
2608 trace_output_16 (tmp);
2615 uint8 tmp = (GPR (OP[0])) & 0xFF;
2616 trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
2617 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
2618 trace_output_16 (tmp);
2625 uint8 tmp = (GPR (OP[0])) & 0xFF;
2626 trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
2627 SET_GPR (OP[1], tmp);
2628 trace_output_16 (tmp);
2635 uint16 tmp = GPR (OP[0]);
2636 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
2637 SET_GPR32 (OP[1], SEXT16(tmp));
2638 trace_output_16 (tmp);
2645 uint16 tmp = GPR (OP[0]);
2646 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
2647 SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
2648 trace_output_16 (tmp);
2656 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
2657 SET_GPR32 (OP[1], tmp);
2658 trace_output_32 (tmp);
2665 int32 tmp = SEXT16(OP[0]);
2666 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
2667 SET_GPR32 (OP[1], tmp);
2668 trace_output_32 (tmp);
2675 uint32 tmp = GPR32 (OP[0]);
2676 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
2677 SET_GPR32 (OP[1], tmp);
2678 trace_output_32 (tmp);
2686 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
2687 SET_GPR32 (OP[1], tmp);
2688 trace_output_32 (tmp);
2696 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
2697 SET_GPR32 (OP[1], tmp);
2698 trace_output_32 (tmp);
2705 uint32 addr = GPR (0);
2706 uint16 count = OP[0], reg = 2, tmp;
2707 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2710 State.exception = SIG_CR16_BUS;
2711 State.pc_changed = 1; /* Don't increment the PC. */
2712 trace_output_void ();
2723 if (reg == 6) reg = 8;
2727 trace_output_void ();
2735 uint32 addr = GPR32 (0);
2736 uint16 count = OP[0], reg = 2, tmp;
2737 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2740 State.exception = SIG_CR16_BUS;
2741 State.pc_changed = 1; /* Don't increment the PC. */
2742 trace_output_void ();
2753 if (reg == 6) reg = 8;
2756 SET_GPR32 (0, addr);
2757 trace_output_void ();
2766 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2769 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2770 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2771 * by the core to 16M-64k to 16M. */
2773 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2774 uint32 addr = OP[0];
2775 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
2776 if (addr > 0xEFFFF) addr |= 0xF00000;
2778 SET_GPR (OP[1], (a | tmp));
2779 trace_output_16 (tmp);
2790 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2791 uint32 addr = OP[0];
2792 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
2794 SET_GPR (OP[1], (a | tmp));
2795 trace_output_16 (tmp);
2802 /* loadb [Rindex]ABS20 REG
2803 * ADDR = Rindex + zext24(disp20)
2807 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2808 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
2811 addr = (GPR32 (12)) + OP[1];
2813 addr = (GPR32 (13)) + OP[1];
2816 SET_GPR (OP[2], (a | tmp));
2817 trace_output_16 (tmp);
2825 /* loadb DIPS4(REGP) REG
2826 * ADDR = RPBASE + zext24(DISP4)
2828 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2829 uint32 addr = (GPR32 (OP[1])) + OP[0];
2830 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
2832 SET_GPR (OP[2], (a | tmp));
2833 trace_output_16 (tmp);
2840 /* loadb [Rindex]disp0(RPbasex) REG
2841 * ADDR = Rpbasex + Rindex
2845 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2846 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
2848 addr = (GPR32 (OP[2])) + OP[1];
2851 addr = (GPR32 (12)) + addr;
2853 addr = (GPR32 (13)) + addr;
2856 SET_GPR (OP[3], (a | tmp));
2857 trace_output_16 (tmp);
2864 /* loadb [Rindex]disp14(RPbasex) REG
2865 * ADDR = Rpbasex + Rindex + zext24(disp14)
2869 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2871 addr = (GPR32 (OP[2])) + OP[1];
2874 addr = (GPR32 (12)) + addr;
2876 addr = (GPR32 (13)) + addr;
2878 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
2880 SET_GPR (OP[3], (a | tmp));
2881 trace_output_16 (tmp);
2889 /* loadb DISPE20(REG) REG
2890 * zext24(Rbase) + zext24(dispe20)
2893 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2894 uint32 addr = OP[0] + (GPR (OP[1]));
2895 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
2897 SET_GPR (OP[2], (a | tmp));
2898 trace_output_16 (tmp);
2905 /* loadb DISP20(REG) REG
2906 * ADDR = zext24(Rbase) + zext24(disp20)
2909 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2910 uint32 addr = OP[0] + (GPR (OP[1]));
2911 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
2913 SET_GPR (OP[2], (a | tmp));
2914 trace_output_16 (tmp);
2921 /* loadb disp16(REGP) REG
2922 * ADDR = RPbase + zext24(disp16)
2925 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2926 uint32 addr = (GPR32 (OP[1])) + OP[0];
2927 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
2929 SET_GPR (OP[2], (a | tmp));
2930 trace_output_16 (tmp);
2937 /* loadb disp20(REGP) REG
2938 * ADDR = RPbase + zext24(disp20)
2940 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2941 uint32 addr = (GPR32 (OP[1])) + OP[0];
2942 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
2944 SET_GPR (OP[2], (a | tmp));
2945 trace_output_16 (tmp);
2953 /* loadb -disp20(REGP) REG
2954 * ADDR = RPbase + zext24(-disp20)
2956 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2957 uint32 addr = (GPR32 (OP[1])) + OP[1];
2958 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
2960 SET_GPR (OP[2], (a | tmp));
2961 trace_output_16 (tmp);
2968 /* loadb [Rindex]disp20(RPbasexb) REG
2969 * ADDR = RPbasex + Rindex + zext24(disp20)
2973 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2974 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
2976 addr = (GPR32 (OP[2])) + OP[1];
2979 addr = (GPR32 (12)) + addr;
2981 addr = (GPR32 (13)) + addr;
2984 SET_GPR (OP[3], (a | tmp));
2985 trace_output_16 (tmp);
2994 * ADDR = zext24(abs20) | remap
2997 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2998 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2999 * by the core to 16M-64k to 16M. */
3002 uint32 addr = OP[0];
3003 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
3004 if (addr > 0xEFFFF) addr |= 0xF00000;
3006 SET_GPR (OP[1], tmp);
3007 trace_output_16 (tmp);
3019 uint32 addr = OP[0];
3020 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
3022 SET_GPR (OP[1], tmp);
3023 trace_output_16 (tmp);
3030 /* loadw [Rindex]ABS20 REG
3031 * ADDR = Rindex + zext24(disp20)
3036 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
3039 addr = (GPR32 (12)) + OP[1];
3041 addr = (GPR32 (13)) + OP[1];
3044 SET_GPR (OP[2], tmp);
3045 trace_output_16 (tmp);
3053 /* loadw DIPS4(REGP) REGP
3054 * ADDR = RPBASE + zext24(DISP4)
3058 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
3059 addr = (GPR32 (OP[1])) + OP[0];
3063 a = (GPR32 (OP[2])) & 0xffff0000;
3064 SET_GPR32 (OP[2], (a | tmp));
3067 SET_GPR (OP[2], tmp);
3069 trace_output_16 (tmp);
3077 /* loadw [Rindex]disp0(RPbasex) REG
3078 * ADDR = Rpbasex + Rindex
3083 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
3085 addr = (GPR32 (OP[2])) + OP[1];
3088 addr = (GPR32 (12)) + addr;
3090 addr = (GPR32 (13)) + addr;
3093 SET_GPR (OP[3], tmp);
3094 trace_output_16 (tmp);
3102 /* loadw [Rindex]disp14(RPbasex) REG
3103 * ADDR = Rpbasex + Rindex + zext24(disp14)
3108 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
3109 addr = (GPR32 (OP[2])) + OP[1];
3112 addr = (GPR32 (12)) + addr;
3114 addr = (GPR32 (13)) + addr;
3117 SET_GPR (OP[3], tmp);
3118 trace_output_16 (tmp);
3125 /* loadw dispe20(REG) REGP
3126 * REGP = [DISPE20+[REG]] */
3130 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3131 addr = OP[0] + (GPR (OP[1]));
3135 a = (GPR32 (OP[2])) & 0xffff0000;
3136 SET_GPR32 (OP[2], (a | tmp));
3139 SET_GPR (OP[2], tmp);
3141 trace_output_16 (tmp);
3149 /* loadw DISP20(REG) REGP
3150 * ADDR = zext24(Rbase) + zext24(disp20)
3155 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3156 addr = OP[0] + (GPR (OP[1]));
3160 a = (GPR32 (OP[2])) & 0xffff0000;
3161 SET_GPR32 (OP[2], (a | tmp));
3164 SET_GPR (OP[2], tmp);
3166 trace_output_16 (tmp);
3173 /* loadw disp16(REGP) REGP
3174 * ADDR = RPbase + zext24(disp16)
3178 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3179 addr = (GPR32 (OP[1])) + OP[0];
3183 a = (GPR32 (OP[2])) & 0xffff0000;
3184 SET_GPR32 (OP[2], (a | tmp));
3187 SET_GPR (OP[2], tmp);
3189 trace_output_16 (tmp);
3196 /* loadw disp20(REGP) REGP
3197 * ADDR = RPbase + zext24(disp20)
3201 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
3202 addr = (GPR32 (OP[1])) + OP[0];
3206 a = (GPR32 (OP[2])) & 0xffff0000;
3207 SET_GPR32 (OP[2], (a | tmp));
3210 SET_GPR (OP[2], tmp);
3212 trace_output_16 (tmp);
3219 /* loadw -disp20(REGP) REG
3220 * ADDR = RPbase + zext24(-disp20)
3225 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
3226 addr = (GPR32 (OP[1])) + OP[0];
3230 a = (GPR32 (OP[2])) & 0xffff0000;
3231 SET_GPR32 (OP[2], (a | tmp));
3234 SET_GPR (OP[2], tmp);
3236 trace_output_16 (tmp);
3244 /* loadw [Rindex]disp20(RPbasexb) REG
3245 * ADDR = RPbasex + Rindex + zext24(disp20)
3250 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
3253 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3255 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3258 SET_GPR (OP[3], tmp);
3259 trace_output_16 (tmp);
3267 /* loadd ABS20, REGP
3268 * ADDR = zext24(abs20) | remap
3271 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3272 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3273 * by the core to 16M-64k to 16M. */
3277 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
3278 if (addr > 0xEFFFF) addr |= 0xF00000;
3280 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3281 SET_GPR32 (OP[1], tmp);
3282 trace_output_32 (tmp);
3289 /* loadd ABS24, REGP
3293 uint32 addr = OP[0];
3295 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
3297 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3298 SET_GPR32 (OP[1],tmp);
3299 trace_output_32 (tmp);
3307 /* loadd [Rindex]ABS20 REGP
3308 * ADDR = Rindex + zext24(disp20)
3312 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
3315 addr = (GPR32 (12)) + OP[1];
3317 addr = (GPR32 (13)) + OP[1];
3320 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3321 SET_GPR32 (OP[2], tmp);
3322 trace_output_32 (tmp);
3330 /* loadd dips4(regp) REGP
3331 * ADDR = Rpbase + zext24(disp4)
3334 uint32 tmp, addr = (GPR32 (OP[1])) + OP[0];
3335 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
3337 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3338 SET_GPR32 (OP[2], tmp);
3339 trace_output_32 (tmp);
3347 /* loadd [Rindex]disp0(RPbasex) REGP
3348 * ADDR = Rpbasex + Rindex
3352 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
3355 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1];
3357 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1];
3360 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3361 SET_GPR32 (OP[3], tmp);
3362 trace_output_32 (tmp);
3370 /* loadd [Rindex]disp14(RPbasex) REGP
3371 * ADDR = Rpbasex + Rindex + zext24(disp14)
3375 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
3378 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3380 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3383 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3384 SET_GPR (OP[3],tmp);
3385 trace_output_32 (tmp);
3393 /* loadd dispe20(REG) REG
3394 * zext24(Rbase) + zext24(dispe20)
3397 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3398 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3400 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3401 SET_GPR32 (OP[2], tmp);
3402 trace_output_32 (tmp);
3410 /* loadd DISP20(REG) REG
3411 * ADDR = zext24(Rbase) + zext24(disp20)
3414 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3415 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3417 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3418 SET_GPR32 (OP[2], tmp);
3419 trace_output_32 (tmp);
3426 /* loadd disp16(REGP) REGP
3427 * ADDR = RPbase + zext24(disp16)
3429 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3430 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3432 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3433 SET_GPR32 (OP[2], tmp);
3434 trace_output_32 (tmp);
3442 /* loadd disp20(REGP) REGP
3443 * ADDR = RPbase + zext24(disp20)
3445 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3446 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
3448 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3449 SET_GPR32 (OP[2], tmp);
3450 trace_output_32 (tmp);
3457 /* loadd -disp20(REGP) REGP
3458 * ADDR = RPbase + zext24(-disp20)
3461 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3462 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
3464 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3465 SET_GPR32 (OP[2], tmp);
3466 trace_output_32 (tmp);
3473 /* loadd [Rindex]disp20(RPbasexb) REGP
3474 * ADDR = RPbasex + Rindex + zext24(disp20)
3478 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
3481 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3483 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3486 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3487 SET_GPR32 (OP[3], tmp);
3488 trace_output_32 (tmp);
3497 * ADDR = zext24(abs20) | remap
3500 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3501 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3502 * by the core to 16M-64k to 16M. */
3504 uint8 a = ((GPR (OP[0])) & 0xff);
3505 uint32 addr = OP[1];
3506 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3508 trace_output_32 (addr);
3519 uint8 a = ((GPR (OP[0])) & 0xff);
3520 uint32 addr = OP[1];
3521 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3523 trace_output_32 (addr);
3530 /* storb REG, [Rindex]ABS20
3531 * ADDR = Rindex + zext24(disp20)
3535 uint8 a = ((GPR (OP[0])) & 0xff);
3536 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3539 addr = (GPR32 (12)) + OP[2];
3541 addr = (GPR32 (13)) + OP[2];
3544 trace_output_32 (addr);
3551 /* storb REG, DIPS4(REGP)
3552 * ADDR = RPBASE + zext24(DISP4)
3555 uint16 a = ((GPR (OP[0])) & 0xff);
3556 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
3557 uint32 addr = (GPR32 (OP[2])) + OP[1];
3559 trace_output_32 (addr);
3566 /* storb [Rindex]disp0(RPbasex) REG
3567 * ADDR = Rpbasex + Rindex
3571 uint8 a = ((GPR (OP[0])) & 0xff);
3572 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3575 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2];
3577 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2];
3580 trace_output_32 (addr);
3587 /* storb REG, [Rindex]disp14(RPbasex)
3588 * ADDR = Rpbasex + Rindex + zext24(disp14)
3591 uint8 a = ((GPR (OP[0])) & 0xff);
3592 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3593 uint32 addr = (GPR32 (OP[2])) + OP[1];
3595 trace_output_32 (addr);
3602 /* storb REG, DISPE20(REG)
3603 * zext24(Rbase) + zext24(dispe20)
3606 uint8 a = ((GPR (OP[0])) & 0xff);
3607 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
3608 uint32 addr = OP[1] + (GPR (OP[2]));
3610 trace_output_32 (addr);
3617 /* storb REG, DISP20(REG)
3618 * ADDR = zext24(Rbase) + zext24(disp20)
3621 uint8 a = (GPR (OP[0]) & 0xff);
3622 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3623 uint32 addr = OP[1] + (GPR (OP[2]));
3625 trace_output_32 (addr);
3632 /* storb REG, disp16(REGP)
3633 * ADDR = RPbase + zext24(disp16)
3636 uint8 a = ((GPR (OP[0])) & 0xff);
3637 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3638 uint32 addr = (GPR32 (OP[2])) + OP[1];
3640 trace_output_32 (addr);
3647 /* storb REG, disp20(REGP)
3648 * ADDR = RPbase + zext24(disp20)
3651 uint8 a = ((GPR (OP[0])) & 0xff);
3652 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3653 uint32 addr = (GPR32 (OP[2])) + OP[1];
3655 trace_output_32 (addr);
3662 /* storb REG, -disp20(REGP)
3663 * ADDR = RPbase + zext24(-disp20)
3666 uint8 a = (GPR (OP[0]) & 0xff);
3667 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3668 uint32 addr = (GPR32 (OP[2])) + OP[1];
3670 trace_output_32 (addr);
3677 /* storb REG, [Rindex]disp20(RPbase)
3678 * ADDR = RPbasex + Rindex + zext24(disp20)
3681 uint8 a = (GPR (OP[0])) & 0xff;
3682 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3683 uint32 addr = (GPR32 (OP[2])) + OP[1];
3685 trace_output_32 (addr);
3688 /* STR_IMM instructions. */
3693 uint8 a = (OP[0]) & 0xff;
3694 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3695 uint32 addr = OP[1];
3697 trace_output_32 (addr);
3704 uint8 a = (OP[0]) & 0xff;
3705 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3706 uint32 addr = OP[1];
3708 trace_output_32 (addr);
3716 uint8 a = (OP[0]) & 0xff;
3717 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3720 addr = (GPR32 (12)) + OP[2];
3722 addr = (GPR32 (13)) + OP[2];
3725 trace_output_32 (addr);
3732 uint8 a = (OP[0]) & 0xff;
3733 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3734 uint32 addr = (GPR32 (OP[2])) + OP[1];
3736 trace_output_32 (addr);
3743 uint8 a = (OP[0]) & 0xff;
3744 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3745 uint32 addr = (GPR32 (OP[2])) + OP[1];
3747 trace_output_32 (addr);
3754 uint8 a = (OP[0]) & 0xff;
3755 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
3756 uint32 addr = (GPR (OP[2])) + OP[1];
3758 trace_output_32 (addr);
3765 uint8 a = (OP[0]) & 0xff;
3766 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
3767 uint32 addr = (GPR32 (OP[2])) + OP[1];
3769 trace_output_32 (addr);
3776 uint8 a = (OP[0]) & 0xff;
3777 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
3778 uint32 addr = (GPR32 (OP[2])) + OP[1];
3780 trace_output_32 (addr);
3787 uint8 a = (OP[0]) & 0xff;
3788 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
3789 uint32 addr = (GPR32 (OP[2])) + OP[1];
3791 trace_output_32 (addr);
3793 /* endif for STR_IMM. */
3799 uint16 a = GPR (OP[0]);
3800 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3801 uint32 addr = OP[1];
3803 trace_output_32 (addr);
3810 uint16 a = GPR (OP[0]);
3811 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3812 uint32 addr = OP[1];
3814 trace_output_32 (addr);
3822 uint16 a = GPR (OP[0]);
3823 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3826 addr = (GPR32 (12)) + OP[2];
3828 addr = (GPR32 (13)) + OP[2];
3831 trace_output_32 (addr);
3839 uint16 a = (GPR (OP[0]));
3840 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
3841 uint32 addr = (GPR32 (OP[2])) + OP[1];
3843 trace_output_32 (addr);
3850 uint16 a = GPR (OP[0]);
3851 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3852 uint32 addr = (GPR32 (OP[2])) + OP[1];
3854 trace_output_32 (addr);
3861 uint16 a = GPR (OP[0]);
3862 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3863 uint32 addr = (GPR32 (OP[2])) + OP[1];
3865 trace_output_32 (addr);
3872 uint16 a = (GPR (OP[0]));
3873 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
3874 uint32 addr = (GPR32 (OP[2])) + OP[1];
3876 trace_output_32 (addr);
3883 uint16 a = (GPR (OP[0]));
3884 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3885 uint32 addr = (GPR (OP[2])) + OP[1];
3887 trace_output_32 (addr);
3894 uint16 a = (GPR (OP[0]));
3895 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3896 uint32 addr = (GPR32 (OP[2])) + OP[1];
3898 trace_output_32 (addr);
3905 uint16 a = (GPR (OP[0]));
3906 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3907 uint32 addr = (GPR32 (OP[2])) + OP[1];
3909 trace_output_32 (addr);
3916 uint16 a = (GPR (OP[0]));
3917 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3918 uint32 addr = (GPR32 (OP[2])) + OP[1];
3920 trace_output_32 (addr);
3927 uint16 a = (GPR (OP[0]));
3928 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3929 uint32 addr = (GPR32 (OP[2])) + OP[1];
3931 trace_output_32 (addr);
3934 /* STORE-w IMM instruction *****/
3940 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3941 uint32 addr = OP[1];
3943 trace_output_32 (addr);
3951 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3952 uint32 addr = OP[1];
3954 trace_output_32 (addr);
3963 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3966 addr = (GPR32 (12)) + OP[2];
3968 addr = (GPR32 (13)) + OP[2];
3971 trace_output_32 (addr);
3979 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3980 uint32 addr = (GPR32 (OP[2])) + OP[1];
3982 trace_output_32 (addr);
3990 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3991 uint32 addr = (GPR32 (OP[2])) + OP[1];
3993 trace_output_32 (addr);
4001 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
4002 uint32 addr = (GPR32 (OP[2])) + OP[1];
4004 trace_output_32 (addr);
4012 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
4013 uint32 addr = (GPR32 (OP[2])) + OP[1];
4015 trace_output_32 (addr);
4024 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
4025 uint32 addr = (GPR32 (OP[2])) + OP[1];
4027 trace_output_32 (addr);
4035 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
4036 uint32 addr = (GPR32 (OP[2])) + OP[1];
4038 trace_output_32 (addr);
4046 uint32 a = GPR32 (OP[0]);
4047 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
4048 uint32 addr = OP[1];
4050 trace_output_32 (addr);
4057 uint32 a = GPR32 (OP[0]);
4058 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
4059 uint32 addr = OP[1];
4061 trace_output_32 (addr);
4068 uint32 addr, a = GPR32 (OP[0]);
4069 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
4072 addr = (GPR32 (12)) + OP[2];
4074 addr = (GPR32 (13)) + OP[2];
4077 trace_output_32 (addr);
4084 uint32 a = GPR32 (OP[0]);
4085 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
4086 uint32 addr = (GPR32 (OP[2])) + OP[1];
4088 trace_output_32 (addr);
4095 uint32 a = GPR32 (OP[0]);
4096 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
4097 uint32 addr = (GPR32 (OP[2])) + OP[1];
4099 trace_output_32 (addr);
4106 uint32 a = GPR32 (OP[0]);
4107 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
4108 uint32 addr = (GPR32 (OP[2])) + OP[1];
4110 trace_output_32 (addr);
4117 uint32 a = GPR32 (OP[0]);
4118 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
4119 uint32 addr = (GPR32 (OP[2])) + OP[1];
4121 trace_output_32 (addr);
4128 uint32 a = GPR32 (OP[0]);
4129 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
4130 uint32 addr = (GPR32 (OP[2])) + OP[1];
4132 trace_output_32 (addr);
4139 uint32 a = GPR32 (OP[0]);
4140 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
4141 uint32 addr = (GPR32 (OP[2])) + OP[1];
4143 trace_output_32 (addr);
4150 uint32 a = GPR32 (OP[0]);
4151 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
4152 uint32 addr = (GPR32 (OP[2])) + OP[1];
4154 trace_output_32 (addr);
4161 uint32 a = GPR32 (OP[0]);
4162 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
4163 uint32 addr = (GPR32 (OP[2])) + OP[1];
4165 trace_output_32 (addr);
4172 uint32 a = GPR32 (OP[0]);
4173 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
4174 uint32 addr = (GPR32 (OP[2])) + OP[1];
4176 trace_output_32 (addr);
4185 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4189 /*REVISIT FOR SATURATION and Q FORMAT. */
4190 SET_GPR32 (OP[2], tmp);
4191 trace_output_32 (tmp);
4200 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4204 /*REVISIT FOR SATURATION. */
4205 SET_GPR32 (OP[2], tmp);
4206 trace_output_32 (tmp);
4215 trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
4219 /*REVISIT FOR SATURATION. */
4220 SET_GPR32 (OP[2], tmp);
4221 trace_output_32 (tmp);
4230 int8 a = (OP[0]) & 0xff;
4231 int8 b = (GPR (OP[1])) & 0xff;
4232 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
4233 tmp = (a * b) & 0xff;
4234 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4235 trace_output_16 (tmp);
4243 int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4244 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
4245 tmp = (a * b) & 0xff;
4246 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4247 trace_output_16 (tmp);
4256 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4257 trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
4258 tmp = (a * b) & 0xff;
4259 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4260 trace_output_16 (tmp);
4270 int16 b = (GPR (OP[1]));
4271 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
4272 tmp = (a * b) & 0xffff;
4273 SET_GPR (OP[1], tmp);
4274 trace_output_32 (tmp);
4282 int16 a = OP[0], b = (GPR (OP[1]));
4283 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
4284 tmp = (a * b) & 0xffff;
4285 SET_GPR (OP[1], tmp);
4286 trace_output_32 (tmp);
4295 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4296 trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
4297 tmp = (a * b) & 0xffff;
4298 SET_GPR (OP[1], tmp);
4299 trace_output_32 (tmp);
4308 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4309 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
4311 SET_GPR (OP[1], tmp);
4312 trace_output_32 (tmp);
4320 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4321 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
4323 SET_GPR32 (OP[1], tmp);
4324 trace_output_32 (tmp);
4332 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4333 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
4335 SET_GPR32 (OP[1], tmp);
4336 trace_output_32 (tmp);
4344 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
4347 State.exception = SIGTRAP;
4348 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
4349 switch (State.ins_type)
4352 ins_type_counters[ (int)INS_UNKNOWN ]++;
4358 trace_output_void ();
4366 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4367 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
4369 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4370 trace_output_16 (tmp);
4377 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4378 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
4380 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4381 trace_output_16 (tmp);
4388 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4389 trace_input ("orb", OP_REG, OP_REG, OP_VOID);
4391 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4392 trace_output_16 (tmp);
4399 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4400 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
4402 SET_GPR (OP[1], tmp);
4403 trace_output_16 (tmp);
4411 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4412 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
4414 SET_GPR (OP[1], tmp);
4415 trace_output_16 (tmp);
4422 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
4423 trace_input ("orw", OP_REG, OP_REG, OP_VOID);
4425 SET_GPR (OP[1], tmp);
4426 trace_output_16 (tmp);
4435 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4436 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
4437 /* A positive count specifies a shift to the left;
4438 * A negative count specifies a shift to the right. */
4444 sign_flag = 0; /* Reset sign_flag. */
4446 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4447 trace_output_16 (tmp);
4454 uint16 a = (GPR (OP[0])) & 0xff;
4455 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4456 trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
4457 if (a & ((long)1 << 3))
4462 a = (unsigned int) (a & 0x7);
4464 /* A positive count specifies a shift to the left;
4465 * A negative count specifies a shift to the right. */
4471 sign_flag = 0; /* Reset sign_flag. */
4472 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4473 trace_output_16 (tmp);
4480 uint16 tmp, b = GPR (OP[1]);
4481 int16 a = GPR (OP[0]);
4482 trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
4483 if (a & ((long)1 << 4))
4488 a = (unsigned int) (a & 0xf);
4490 /* A positive count specifies a shift to the left;
4491 * A negative count specifies a shift to the right. */
4497 sign_flag = 0; /* Reset sign_flag. */
4498 SET_GPR (OP[1], (tmp & 0xffff));
4499 trace_output_16 (tmp);
4506 uint16 tmp, b = GPR (OP[1]);
4508 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
4509 /* A positive count specifies a shift to the left;
4510 * A negative count specifies a shift to the right. */
4516 sign_flag = 0; /* Reset sign_flag. */
4517 SET_GPR (OP[1], (tmp & 0xffff));
4518 trace_output_16 (tmp);
4525 uint32 tmp, b = GPR32 (OP[1]);
4527 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
4528 /* A positive count specifies a shift to the left;
4529 * A negative count specifies a shift to the right. */
4535 sign_flag = 0; /* Reset sign flag. */
4537 SET_GPR32 (OP[1], tmp);
4538 trace_output_32 (tmp);
4545 uint32 tmp, b = GPR32 (OP[1]);
4546 uint16 a = GPR (OP[0]);
4547 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
4548 if (a & ((long)1 << 5))
4553 a = (unsigned int) (a & 0x1f);
4554 /* A positive count specifies a shift to the left;
4555 * A negative count specifies a shift to the right. */
4561 sign_flag = 0; /* Reset sign flag. */
4563 SET_GPR32 (OP[1], tmp);
4564 trace_output_32 (tmp);
4572 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4573 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4574 /* A positive count specifies a shift to the left;
4575 * A negative count specifies a shift to the right. */
4581 sign_flag = 0; /* Reset sign flag. */
4583 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00)));
4584 trace_output_16 (tmp);
4592 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4593 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4594 /* A positive count specifies a shift to the left;
4595 * A negative count specifies a shift to the right. */
4601 sign_flag = 0; /* Reset sign flag. */
4603 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4604 trace_output_16 (tmp);
4612 int16 a = (GPR (OP[0]));
4613 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4614 trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
4616 if (a & ((long)1 << 3))
4621 a = (unsigned int) (a & 0x7);
4623 /* A positive count specifies a shift to the left;
4624 * A negative count specifies a shift to the right. */
4630 sign_flag = 0; /* Reset sign flag. */
4632 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4633 trace_output_16 (tmp);
4641 int16 tmp, b = GPR (OP[1]);
4643 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4644 /* A positive count specifies a shift to the left;
4645 * A negative count specifies a shift to the right. */
4651 sign_flag = 0; /* Reset sign flag. */
4653 SET_GPR (OP[1], (tmp & 0xffff));
4654 trace_output_16 (tmp);
4661 int16 tmp, b = GPR (OP[1]);
4663 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4664 /* A positive count specifies a shift to the left;
4665 * A negative count specifies a shift to the right. */
4671 sign_flag = 0; /* Reset sign flag. */
4672 SET_GPR (OP[1], (tmp & 0xffff));
4673 trace_output_16 (tmp);
4681 int16 a = GPR (OP[0]), b = GPR (OP[1]);
4682 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
4684 if (a & ((long)1 << 4))
4689 a = (unsigned int) (a & 0xf);
4690 /* A positive count specifies a shift to the left;
4691 * A negative count specifies a shift to the right. */
4698 sign_flag = 0; /* Reset sign flag. */
4699 SET_GPR (OP[1], (tmp & 0xffff));
4700 trace_output_16 (tmp);
4707 int32 tmp,b = GPR32 (OP[1]);
4709 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4710 /* A positive count specifies a shift to the left;
4711 * A negative count specifies a shift to the right. */
4717 sign_flag = 0; /* Reset sign flag. */
4718 SET_GPR32 (OP[1], tmp);
4719 trace_output_32 (tmp);
4727 int32 a = OP[0], b = GPR32 (OP[1]);
4728 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4729 /* A positive count specifies a shift to the left;
4730 * A negative count specifies a shift to the right. */
4736 sign_flag = 0; /* Reset sign flag. */
4737 SET_GPR32 (OP[1], tmp);
4738 trace_output_32 (tmp);
4746 int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]);
4747 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
4749 if (a & ((long)1 << 5))
4754 a = (unsigned int) (a & 0x1f);
4755 /* A positive count specifies a shift to the left;
4756 * A negative count specifies a shift to the right. */
4762 sign_flag = 0; /* Reset sign flag. */
4763 SET_GPR32 (OP[1], tmp);
4764 trace_output_32 (tmp);
4772 uint32 addr = GPR (1);
4773 uint16 count = OP[0], reg = 2;
4774 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
4777 State.exception = SIG_CR16_BUS;
4778 State.pc_changed = 1; /* Don't increment the PC. */
4779 trace_output_void ();
4785 SW (addr, (GPR (reg)));
4789 if (reg == 6) reg = 8;
4794 trace_output_void ();
4802 uint32 addr = GPR32 (6);
4803 uint16 count = OP[0], reg = 2;
4804 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
4807 State.exception = SIG_CR16_BUS;
4808 State.pc_changed = 1; /* Don't increment the PC. */
4809 trace_output_void ();
4815 SW (addr, (GPR (reg)));
4819 if (reg == 6) reg = 8;
4822 SET_GPR32 (6, addr);
4823 trace_output_void ();
4831 uint8 b = (GPR (OP[1])) & 0xff;
4832 uint16 tmp = (~a + 1 + b) & 0xff;
4833 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
4834 /* see ../common/sim-alu.h for a more extensive discussion on how to
4835 compute the carry/overflow bits. */
4836 SET_PSR_C (tmp > 0xff);
4837 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4838 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4839 trace_output_16 (tmp);
4846 uint8 a = OP[0] & 0xFF;
4847 uint8 b = (GPR (OP[1])) & 0xFF;
4848 uint16 tmp = (~a + 1 + b) & 0xFF;
4849 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
4850 /* see ../common/sim-alu.h for a more extensive discussion on how to
4851 compute the carry/overflow bits. */
4852 SET_PSR_C (tmp > 0xff);
4853 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4854 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4855 trace_output_16 (tmp);
4862 uint8 a = (GPR (OP[0])) & 0xFF;
4863 uint8 b = (GPR (OP[1])) & 0xFF;
4864 uint16 tmp = (~a + 1 + b) & 0xff;
4865 trace_input ("subb", OP_REG, OP_REG, OP_VOID);
4866 /* see ../common/sim-alu.h for a more extensive discussion on how to
4867 compute the carry/overflow bits. */
4868 SET_PSR_C (tmp > 0xff);
4869 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4870 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4871 trace_output_16 (tmp);
4879 uint16 b = GPR (OP[1]);
4880 uint16 tmp = (~a + 1 + b);
4881 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
4882 /* see ../common/sim-alu.h for a more extensive discussion on how to
4883 compute the carry/overflow bits. */
4884 SET_PSR_C (tmp > 0xffff);
4885 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4886 SET_GPR (OP[1], tmp);
4887 trace_output_16 (tmp);
4895 uint16 b = GPR (OP[1]);
4896 uint32 tmp = (~a + 1 + b);
4897 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
4898 /* see ../common/sim-alu.h for a more extensive discussion on how to
4899 compute the carry/overflow bits. */
4900 SET_PSR_C (tmp > 0xffff);
4901 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4902 SET_GPR (OP[1], tmp & 0xffff);
4903 trace_output_16 (tmp);
4910 uint16 a = GPR (OP[0]);
4911 uint16 b = GPR (OP[1]);
4912 uint32 tmp = (~a + 1 + b);
4913 trace_input ("subw", OP_REG, OP_REG, OP_VOID);
4914 /* see ../common/sim-alu.h for a more extensive discussion on how to
4915 compute the carry/overflow bits. */
4916 SET_PSR_C (tmp > 0xffff);
4917 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4918 SET_GPR (OP[1], tmp & 0xffff);
4919 trace_output_16 (tmp);
4927 uint8 b = (GPR (OP[1])) & 0xff;
4928 //uint16 tmp1 = a + 1;
4929 uint16 tmp1 = a + (PSR_C);
4930 uint16 tmp = (~tmp1 + 1 + b);
4931 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
4932 /* see ../common/sim-alu.h for a more extensive discussion on how to
4933 compute the carry/overflow bits. */
4934 SET_PSR_C (tmp > 0xff);
4935 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4936 SET_GPR (OP[1], tmp);
4937 trace_output_16 (tmp);
4945 uint16 b = (GPR (OP[1])) & 0xff;
4946 //uint16 tmp1 = a + 1;
4947 uint16 tmp1 = a + (PSR_C);
4948 uint16 tmp = (~tmp1 + 1 + b);
4949 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
4950 /* see ../common/sim-alu.h for a more extensive discussion on how to
4951 compute the carry/overflow bits. */
4952 SET_PSR_C (tmp > 0xff);
4953 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4954 SET_GPR (OP[1], tmp);
4955 trace_output_16 (tmp);
4962 uint16 a = (GPR (OP[0])) & 0xff;
4963 uint16 b = (GPR (OP[1])) & 0xff;
4964 uint16 tmp1 = a + (PSR_C);
4965 uint16 tmp = (~tmp1 + 1 + b);
4966 trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
4967 /* see ../common/sim-alu.h for a more extensive discussion on how to
4968 compute the carry/overflow bits. */
4969 SET_PSR_C (tmp > 0xff);
4970 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4971 SET_GPR (OP[1], tmp);
4972 trace_output_16 (tmp);
4979 uint16 a = OP[0], b = (GPR (OP[1]));
4980 uint16 tmp1 = a + (PSR_C);
4981 uint16 tmp = (~tmp1 + 1 + b);
4982 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
4983 /* see ../common/sim-alu.h for a more extensive discussion on how to
4984 compute the carry/overflow bits. */
4985 SET_PSR_C (tmp > 0xffff);
4986 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4987 SET_GPR (OP[1], tmp);
4988 trace_output_16 (tmp);
4996 uint16 b = GPR (OP[1]);
4997 uint16 tmp1 = a + (PSR_C);
4998 uint16 tmp = (~tmp1 + 1 + b);
4999 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
5000 /* see ../common/sim-alu.h for a more extensive discussion on how to
5001 compute the carry/overflow bits. */
5002 SET_PSR_C (tmp > 0xffff);
5003 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5004 SET_GPR (OP[1], tmp);
5005 trace_output_16 (tmp);
5012 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
5013 uint16 tmp1 = a + (PSR_C);
5014 uint16 tmp = (~tmp1 + 1 + b);
5015 trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
5016 /* see ../common/sim-alu.h for a more extensive discussion on how to
5017 compute the carry/overflow bits. */
5018 SET_PSR_C (tmp > 0xffff);
5019 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5020 SET_GPR (OP[1], tmp);
5021 trace_output_16 (tmp);
5029 uint32 b = GPR32 (OP[1]);
5030 uint32 tmp = (~a + 1 + b);
5031 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
5032 /* see ../common/sim-alu.h for a more extensive discussion on how to
5033 compute the carry/overflow bits. */
5034 SET_PSR_C (tmp > 0xffffffff);
5035 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5036 ((b & 0x80000000) != (tmp & 0x80000000)));
5037 SET_GPR32 (OP[1], tmp);
5038 trace_output_32 (tmp);
5045 uint32 a = GPR32 (OP[0]);
5046 uint32 b = GPR32 (OP[1]);
5047 uint32 tmp = (~a + 1 + b);
5048 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
5049 /* see ../common/sim-alu.h for a more extensive discussion on how to
5050 compute the carry/overflow bits. */
5051 SET_PSR_C (tmp > 0xffffffff);
5052 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5053 ((b & 0x80000000) != (tmp & 0x80000000)));
5054 SET_GPR32 (OP[1], tmp);
5055 trace_output_32 (tmp);
5064 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
5068 #if (DEBUG & DEBUG_TRAP) == 0
5071 uint16 vec = OP[0] + TRAP_VECTOR_START;
5074 SET_PSR (PSR & PSR_SM_BIT);
5079 #else /* if debugging use trap to print registers */
5082 static int first_time = 1;
5087 (*cr16_callback->printf_filtered) (cr16_callback, "Trap # PC ");
5088 for (i = 0; i < 16; i++)
5089 (*cr16_callback->printf_filtered) (cr16_callback, " %sr%d", (i > 9) ? "" : " ", i);
5090 (*cr16_callback->printf_filtered) (cr16_callback, " a0 a1 f0 f1 c\n");
5093 (*cr16_callback->printf_filtered) (cr16_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
5095 for (i = 0; i < 16; i++)
5096 (*cr16_callback->printf_filtered) (cr16_callback, " %.4x", (int) GPR (i));
5098 for (i = 0; i < 2; i++)
5099 (*cr16_callback->printf_filtered) (cr16_callback, " %.2x%.8lx",
5100 ((int)(ACC (i) >> 32) & 0xff),
5101 ((unsigned long) ACC (i)) & 0xffffffff);
5103 (*cr16_callback->printf_filtered) (cr16_callback, " %d %d %d\n",
5104 PSR_F != 0, PSR_F != 0, PSR_C != 0);
5105 (*cr16_callback->flush_stdout) (cr16_callback);
5109 case 8: /* new system call trap */
5110 /* Trap 8 is used for simulating low-level I/O */
5112 unsigned32 result = 0;
5115 /* Registers passed to trap 0. */
5117 #define FUNC GPR (0) /* function number. */
5118 #define PARM1 GPR (2) /* optional parm 1. */
5119 #define PARM2 GPR (3) /* optional parm 2. */
5120 #define PARM3 GPR (4) /* optional parm 3. */
5121 #define PARM4 GPR (5) /* optional parm 4. */
5123 /* Registers set by trap 0 */
5125 #define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5126 #define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5127 #define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5129 /* Turn a pointer in a register into a pointer into real memory. */
5131 #define MEMPTR(x) ((char *)(dmem_addr(x)))
5135 #if !defined(__GO32__) && !defined(_WIN32)
5136 #ifdef TARGET_SYS_fork
5137 case TARGET_SYS_fork:
5138 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
5140 trace_output_16 (result);
5145 case TARGET_SYS_getpid:
5146 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5148 trace_output_16 (result);
5151 case TARGET_SYS_kill:
5152 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5153 if (PARM1 == getpid ())
5155 trace_output_void ();
5156 State.exception = PARM2;
5164 case 1: os_sig = SIGHUP; break;
5167 case 2: os_sig = SIGINT; break;
5170 case 3: os_sig = SIGQUIT; break;
5173 case 4: os_sig = SIGILL; break;
5176 case 5: os_sig = SIGTRAP; break;
5179 case 6: os_sig = SIGABRT; break;
5180 #elif defined(SIGIOT)
5181 case 6: os_sig = SIGIOT; break;
5184 case 7: os_sig = SIGEMT; break;
5187 case 8: os_sig = SIGFPE; break;
5190 case 9: os_sig = SIGKILL; break;
5193 case 10: os_sig = SIGBUS; break;
5196 case 11: os_sig = SIGSEGV; break;
5199 case 12: os_sig = SIGSYS; break;
5202 case 13: os_sig = SIGPIPE; break;
5205 case 14: os_sig = SIGALRM; break;
5208 case 15: os_sig = SIGTERM; break;
5211 case 16: os_sig = SIGURG; break;
5214 case 17: os_sig = SIGSTOP; break;
5217 case 18: os_sig = SIGTSTP; break;
5220 case 19: os_sig = SIGCONT; break;
5223 case 20: os_sig = SIGCHLD; break;
5224 #elif defined(SIGCLD)
5225 case 20: os_sig = SIGCLD; break;
5228 case 21: os_sig = SIGTTIN; break;
5231 case 22: os_sig = SIGTTOU; break;
5234 case 23: os_sig = SIGIO; break;
5235 #elif defined (SIGPOLL)
5236 case 23: os_sig = SIGPOLL; break;
5239 case 24: os_sig = SIGXCPU; break;
5242 case 25: os_sig = SIGXFSZ; break;
5245 case 26: os_sig = SIGVTALRM; break;
5248 case 27: os_sig = SIGPROF; break;
5251 case 28: os_sig = SIGWINCH; break;
5254 case 29: os_sig = SIGLOST; break;
5257 case 30: os_sig = SIGUSR1; break;
5260 case 31: os_sig = SIGUSR2; break;
5266 trace_output_void ();
5267 (*cr16_callback->printf_filtered) (cr16_callback, "Unknown signal %d\n", PARM2);
5268 (*cr16_callback->flush_stdout) (cr16_callback);
5269 State.exception = SIGILL;
5273 RETVAL (kill (PARM1, PARM2));
5274 trace_output_16 (result);
5279 #ifdef TARGET_SYS_execve
5280 case TARGET_SYS_execve:
5281 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID);
5282 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3),
5283 (char **)MEMPTR (PARM4)));
5284 trace_output_16 (result);
5288 #ifdef TARGET_SYS_execv
5289 case TARGET_SYS_execv:
5290 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID);
5291 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
5292 trace_output_16 (result);
5296 #ifdef TARGET_SYS_pipe
5297 case TARGET_SYS_pipe:
5302 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID);
5304 RETVAL (pipe (host_fd));
5305 SW (buf, host_fd[0]);
5306 buf += sizeof(uint16);
5307 SW (buf, host_fd[1]);
5308 trace_output_16 (result);
5313 #ifdef TARGET_SYS_wait
5314 case TARGET_SYS_wait:
5317 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID);
5318 RETVAL (wait (&status));
5321 trace_output_16 (result);
5326 case TARGET_SYS_getpid:
5327 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5329 trace_output_16 (result);
5332 case TARGET_SYS_kill:
5333 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5334 trace_output_void ();
5335 State.exception = PARM2;
5339 case TARGET_SYS_read:
5340 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG);
5341 RETVAL (cr16_callback->read (cr16_callback, PARM1,
5342 MEMPTR (((unsigned long)PARM3 << 16)
5343 |((unsigned long)PARM2)), PARM4));
5344 trace_output_16 (result);
5347 case TARGET_SYS_write:
5348 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG);
5349 RETVAL ((int)cr16_callback->write (cr16_callback, PARM1,
5350 MEMPTR (((unsigned long)PARM3 << 16) | PARM2), PARM4));
5351 trace_output_16 (result);
5354 case TARGET_SYS_lseek:
5355 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG);
5356 RETVAL32 (cr16_callback->lseek (cr16_callback, PARM1,
5357 ((((long) PARM3) << 16) | PARM2),
5359 trace_output_32 (result);
5362 case TARGET_SYS_close:
5363 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID);
5364 RETVAL (cr16_callback->close (cr16_callback, PARM1));
5365 trace_output_16 (result);
5368 case TARGET_SYS_open:
5369 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID);
5370 RETVAL32 (cr16_callback->open (cr16_callback,
5371 MEMPTR ((((unsigned long)PARM2)<<16)|PARM1),
5373 trace_output_32 (result);
5376 #ifdef TARGET_SYS_rename
5377 case TARGET_SYS_rename:
5378 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID);
5379 RETVAL (cr16_callback->rename (cr16_callback,
5380 MEMPTR ((((unsigned long)PARM2)<<16) |PARM1),
5381 MEMPTR ((((unsigned long)PARM4)<<16) |PARM3)));
5382 trace_output_16 (result);
5386 case 0x408: /* REVISIT: Added a dummy getenv call. */
5387 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID);
5389 trace_output_32 (result);
5392 case TARGET_SYS_exit:
5393 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID);
5394 State.exception = SIG_CR16_EXIT;
5395 trace_output_void ();
5398 case TARGET_SYS_unlink:
5399 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID);
5400 RETVAL (cr16_callback->unlink (cr16_callback,
5401 MEMPTR (((unsigned long)PARM2<<16)|PARM1)));
5402 trace_output_16 (result);
5406 #ifdef TARGET_SYS_stat
5407 case TARGET_SYS_stat:
5408 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID);
5409 /* stat system call. */
5411 struct stat host_stat;
5414 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat));
5418 /* The hard-coded offsets and sizes were determined by using
5419 * the CR16 compiler on a test program that used struct stat.
5421 SW (buf, host_stat.st_dev);
5422 SW (buf+2, host_stat.st_ino);
5423 SW (buf+4, host_stat.st_mode);
5424 SW (buf+6, host_stat.st_nlink);
5425 SW (buf+8, host_stat.st_uid);
5426 SW (buf+10, host_stat.st_gid);
5427 SW (buf+12, host_stat.st_rdev);
5428 SLW (buf+16, host_stat.st_size);
5429 SLW (buf+20, host_stat.st_atime);
5430 SLW (buf+28, host_stat.st_mtime);
5431 SLW (buf+36, host_stat.st_ctime);
5433 trace_output_16 (result);
5437 #ifdef TARGET_SYS_chown
5438 case TARGET_SYS_chown:
5439 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID);
5440 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
5441 trace_output_16 (result);
5445 case TARGET_SYS_chmod:
5446 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID);
5447 RETVAL (chmod (MEMPTR (PARM1), PARM2));
5448 trace_output_16 (result);
5451 #ifdef TARGET_SYS_utime
5452 case TARGET_SYS_utime:
5453 trace_input ("<utime>", OP_REG, OP_REG, OP_REG);
5454 /* Cast the second argument to void *, to avoid type mismatch
5455 if a prototype is present. */
5456 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
5457 trace_output_16 (result);
5461 #ifdef TARGET_SYS_time
5462 case TARGET_SYS_time:
5463 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG);
5464 RETVAL32 (time (NULL));
5465 trace_output_32 (result);
5473 case TRAP_BREAKPOINT:
5474 State.exception = SIGTRAP;
5477 trace_output_void ();
5479 case SIGTRAP: /* supervisor call ? */
5480 State.exception = SIG_CR16_EXIT;
5481 trace_output_void ();
5484 cr16_callback->error (cr16_callback, "Unknown syscall %d", FUNC);
5488 if ((uint16) result == (uint16) -1)
5489 RETERR (cr16_callback->get_errno(cr16_callback));
5502 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5503 uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
5504 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
5510 SW (sp_addr, (GPR (b+i)));
5516 tmp = (GPR32 (b+i));
5518 tmp = (GPR32 (b+i-1));
5537 /* Store RA address. */
5541 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5542 SET_GPR32 (15, sp_addr); /* Update SP address. */
5544 trace_output_void ();
5551 uint32 sp_addr, tmp, is_regp = 0;
5552 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5553 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
5556 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5558 sp_addr = (GPR32 (15)) - (a * 2);
5564 SW (sp_addr, (GPR (b+i)));
5570 tmp = (GPR32 (b+i));
5572 tmp = (GPR32 (b+i-1));
5591 /* Store RA address. */
5594 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5597 sp_addr = (GPR32 (15)) - (a * 2);
5599 SET_GPR32 (15, sp_addr); /* Update SP address. */
5601 trace_output_void ();
5609 uint32 sp_addr = (GPR32 (15)), tmp;
5610 trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
5612 SLW(sp_addr-4,tmp); /* Store RA address. */
5613 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */
5614 trace_output_void ();
5622 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5623 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
5624 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
5630 SET_GPR ((b+i), RW(sp_addr));
5646 tmp = (tmp << 16) | (GPR32 (b+i));
5648 tmp = (tmp << 16) | (GPR32 (b+i-1));
5652 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)
5653 | ((tmp >> 16) & 0xffff)));
5655 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)
5656 | ((tmp >> 16) & 0xffff)));
5663 tmp = RLW(sp_addr); /* store RA also. */
5664 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5666 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */
5668 trace_output_void ();
5675 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5676 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;
5677 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
5683 SET_GPR ((b+i), RW(sp_addr));
5699 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i));
5701 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1));
5705 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5707 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5715 tmp = RLW(sp_addr); /* Store RA Reg. */
5716 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5720 SET_GPR32 (15, sp_addr); /* Update SP address. */
5722 trace_output_void ();
5729 uint32 sp_addr = GPR32 (15);
5731 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
5734 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5735 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */
5737 trace_output_void ();
5744 uint16 a = OP[0], b = OP[1];
5745 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
5747 JMP(((GPR32(14)) << 1) & 0xffffff);
5749 trace_output_void ();
5756 uint16 a = OP[0], b = OP[1];
5757 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
5759 JMP(((GPR32(14)) << 1) & 0xffffff);
5761 trace_output_void ();
5769 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
5771 tmp = (((GPR32(14)) << 1) & 0xffffff);
5772 /* If the resulting PC value is less than 0x00_0000 or greater
5773 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5775 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
5777 State.exception = SIG_CR16_BUS;
5778 State.pc_changed = 1; /* Don't increment the PC. */
5779 trace_output_void ();
5785 trace_output_32 (tmp);
5793 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID);
5795 trace_output_void ();
5802 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5804 trace_output_void ();
5811 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID);
5813 trace_output_void ();
5820 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5822 trace_output_void ();
5829 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID);
5831 trace_output_void ();
5838 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID);
5840 trace_output_void ();
5847 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID);
5849 trace_output_void ();
5856 trace_input ("di", OP_VOID, OP_VOID, OP_VOID);
5858 trace_output_void ();
5865 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID);
5867 trace_output_void ();
5874 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
5875 State.exception = SIGTRAP;
5876 trace_output_void ();
5883 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID);
5885 trace_output_void ();
5892 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5893 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
5895 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5896 trace_output_16 (tmp);
5903 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5904 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
5906 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5907 trace_output_16 (tmp);
5914 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
5915 trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
5917 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5918 trace_output_16 (tmp);
5925 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5926 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
5928 SET_GPR (OP[1], tmp);
5929 trace_output_16 (tmp);
5936 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5937 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
5939 SET_GPR (OP[1], tmp);
5940 trace_output_16 (tmp);
5947 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
5948 trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
5950 SET_GPR (OP[1], tmp);
5951 trace_output_16 (tmp);
5954 /*REVISIT FOR LPR/SPR . */
5960 uint16 a = GPR (OP[0]);
5961 trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
5962 SET_CREG (OP[1], a);
5963 trace_output_16 (a);
5970 uint32 a = GPR32 (OP[0]);
5971 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
5972 SET_CREG (OP[1], a);
5973 trace_output_flag ();
5980 uint16 a = CREG (OP[0]);
5981 trace_input ("spr", OP_REG, OP_REG, OP_VOID);
5983 trace_output_16 (a);
5990 uint32 a = CREG (OP[0]);
5991 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
5992 SET_GPR32 (OP[1], a);
5993 trace_output_32 (a);
6000 trace_input ("null", OP_VOID, OP_VOID, OP_VOID);
6001 State.exception = SIG_CR16_STOP;