1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2015 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb/callback.h"
27 #include "gdb/remote-sim.h"
30 #include "sim-options.h"
32 #include "gdb/sim-cr16.h"
33 #include "gdb/signals.h"
34 #include "opcode/cr16.h"
38 host_callback *cr16_callback;
43 static struct hash_entry *lookup_hash (uint64 ins, int size);
44 static void get_operands (operand_desc *s, uint64 mcode, int isize, int nops);
45 static INLINE uint8 *map_memory (unsigned phys_addr);
51 struct hash_entry *next;
59 struct hash_entry hash_table[MAX_HASH+1];
62 hash(unsigned long long insn, int format)
64 unsigned int i = 4, tmp;
67 while ((insn >> i) != 0) i +=4;
69 return ((insn >> (i-4)) & 0xf); /* Use last 4 bits as hask key. */
71 return ((insn & 0xF)); /* Use last 4 bits as hask key. */
75 INLINE static struct hash_entry *
76 lookup_hash (uint64 ins, int size)
81 h = &hash_table[hash(ins,1)];
84 mask = (((1 << (32 - h->mask)) -1) << h->mask);
86 /* Adjuest mask for branch with 2 word instructions. */
87 if ((h->ops->mnimonic != NULL) &&
88 ((streq(h->ops->mnimonic,"b") && h->size == 2)))
92 while ((ins & mask) != (BIN(h->opcode, h->mask)))
96 State.exception = SIGILL;
97 State.pc_changed = 1; /* Don't increment the PC. */
102 mask = (((1 << (32 - h->mask)) -1) << h->mask);
103 /* Adjuest mask for branch with 2 word instructions. */
104 if ((streq(h->ops->mnimonic,"b")) && h->size == 2)
112 get_operands (operand_desc *s, uint64 ins, int isize, int nops)
114 uint32 i, opn = 0, start_bit = 0, op_type = 0;
115 int32 op_size = 0, mask = 0;
117 if (isize == 1) /* Trunkcate the extra 16 bits of INS. */
120 for (i=0; i < 4; ++i,++opn)
122 if (s[opn].op_type == dummy) break;
124 op_type = s[opn].op_type;
125 start_bit = s[opn].shift;
126 op_size = cr16_optab[op_type].bit_size;
130 case imm3: case imm4: case imm5: case imm6:
133 OP[i] = ((ins >> 4) & ((1 << op_size) -1));
135 OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));
137 if (OP[i] & ((long)1 << (op_size -1)))
140 OP[i] = ~(OP[i]) + 1;
142 OP[i] = (unsigned long int)(OP[i] & (((long)1 << op_size) -1));
146 case uimm3: case uimm3_1: case uimm4_1:
150 OP[i] = ((ins >> 4) & ((1 << op_size) -1)); break;
152 OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));break;
153 default: /* for case 3. */
154 OP[i] = ((ins >> (16 + start_bit)) & ((1 << op_size) -1)); break;
164 OP[i] = ((ins >> 4) & ((1 << op_size) -1));
166 OP[i] = (ins & ((1 << op_size) -1));
169 OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
172 OP[i] = ((ins >> (start_bit + 16)) & ((1 << op_size) -1));
175 OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
180 case imm16: case uimm16:
181 OP[i] = ins & 0xFFFF;
184 case uimm20: case imm20:
185 OP[i] = ins & (((long)1 << op_size) - 1);
188 case imm32: case uimm32:
189 OP[i] = ins & 0xFFFFFFFF;
192 case uimm5: break; /*NOT USED. */
193 OP[i] = ins & ((1 << op_size) - 1); break;
196 OP[i] = (ins >> 4) & ((1 << 4) - 1);
197 OP[i] = (OP[i] * 2) + 2;
198 if (OP[i] & ((long)1 << 5))
201 OP[i] = ~(OP[i]) + 1;
202 OP[i] = (unsigned long int)(OP[i] & 0x1F);
207 OP[i] = ((((ins >> 8) & 0xf) << 4) | (ins & 0xf));
209 if (OP[i] & ((long)1 << 8))
212 OP[i] = ~(OP[i]) + 1;
213 OP[i] = (unsigned long int)(OP[i] & 0xFF);
218 OP[i] = (ins & 0xFFFF);
221 OP[i] = (OP[i] & 0xFFFE);
223 OP[i] = ~(OP[i]) + 1;
224 OP[i] = (unsigned long int)(OP[i] & 0xFFFF);
230 OP[i] = (ins & 0xFFFFFF);
232 OP[i] = (ins & 0xFFFF) | (((ins >> 24) & 0xf) << 16) |
233 (((ins >> 16) & 0xf) << 20);
237 OP[i] = (OP[i] & 0xFFFFFE);
239 OP[i] = ~(OP[i]) + 1;
240 OP[i] = (unsigned long int)(OP[i] & 0xFFFFFF);
246 OP[i] = (ins) & 0xFFFFF;
248 OP[i] = (ins >> start_bit) & 0xFFFFF;
252 OP[i] = ((ins & 0xFFFF) | (((ins >> 16) & 0xf) << 20)
253 | (((ins >> 24) & 0xf) << 16));
255 OP[i] = (ins >> 16) & 0xFFFFFF;
259 case rbase: break; /* NOT USED. */
260 case rbase_disps20: case rbase_dispe20:
261 case rpbase_disps20: case rpindex_disps20:
262 OP[i] = ((((ins >> 24)&0xf) << 16)|((ins) & 0xFFFF));
263 OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */
266 OP[i] = 0; /* 4 bit disp const. */
267 OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */
270 OP[i] = ((ins >> 8) & 0xF) * 2; /* 4 bit disp const. */
271 OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */
274 OP[i] = ((ins >> 8) & 0xF); /* 4 bit disp const. */
275 OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */
278 OP[i] = (ins) & 0xFFFF;
279 OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */
283 OP[++i] = (ins >> 4) & 0xF; /* get 4 bit for reg. */
284 OP[++i] = (ins >> 8) & 0x1; /* get 1 bit for index-reg. */
286 case rpindex_disps14:
287 OP[i] = (ins) & 0x3FFF;
288 OP[++i] = (ins >> 14) & 0x1; /* get 1 bit for index-reg. */
289 OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */
292 OP[i] = (ins) & 0xFFFFF;
293 OP[++i] = (ins >> 24) & 0x1; /* get 1 bit for index-reg. */
294 OP[++i] = (ins >> 20) & 0xF; /* get 4 bit for reg. */
296 case regr: case regp: case pregr: case pregrp:
300 if (start_bit == 20) OP[i] = (ins >> 4) & 0xF;
301 else if (start_bit == 16) OP[i] = ins & 0xF;
303 case 2: OP[i] = (ins >> start_bit) & 0xF; break;
304 case 3: OP[i] = (ins >> (start_bit + 16)) & 0xF; break;
309 if (isize == 1) OP[i] = (ins >> 4) & 0xF;
310 else if (isize == 2) OP[i] = (ins >> start_bit) & 0xF;
311 else OP[i] = (ins >> (start_bit + 16)) & 0xF;
317 /* For ESC on uimm4_1 operand. */
318 if (op_type == uimm4_1)
322 /* For increment by 1. */
323 if ((op_type == pregr) || (op_type == pregrp))
326 /* FIXME: for tracing, update values that need to be updated each
327 instruction decode cycle */
328 State.trace.psw = PSR;
332 do_run (SIM_DESC sd, uint64 mcode)
334 host_callback *cr16_callback = STATE_CALLBACK (sd);
335 struct simops *s= Simops;
336 struct hash_entry *h;
340 if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
341 (*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", mcode);
344 h = lookup_hash(mcode, 1);
346 if ((h == NULL) || (h->opcode == 0))
351 iaddr = imem_addr ((uint32)PC + 2);
352 mcode = (mcode << 16) | get_longword( iaddr );
355 /* Re-set OP list. */
356 OP[0] = OP[1] = OP[2] = OP[3] = sign_flag = 0;
358 /* for push/pop/pushrtn with RA instructions. */
359 if ((h->format & REG_LIST) && (mcode & 0x800000))
360 OP[2] = 1; /* Set 1 for RA operand. */
362 /* numops == 0 means, no operands. */
363 if (((h->ops) != NULL) && (((h->ops)->numops) != 0))
364 get_operands ((h->ops)->operands, mcode, h->size, (h->ops)->numops);
366 //State.ins_type = h->flags;
377 for (i = 0; i < IMEM_SEGMENTS; i++)
379 if (State.mem.insn[i])
380 free (State.mem.insn[i]);
382 for (i = 0; i < DMEM_SEGMENTS; i++)
384 if (State.mem.data[i])
385 free (State.mem.data[i]);
387 for (i = 0; i < UMEM_SEGMENTS; i++)
389 if (State.mem.unif[i])
390 free (State.mem.unif[i]);
392 /* Always allocate dmem segment 0. This contains the IMAP and DMAP
394 State.mem.data[0] = calloc (1, SEGMENT_SIZE);
397 /* For tracing - leave info on last access around. */
398 static char *last_segname = "invalid";
399 static char *last_from = "invalid";
400 static char *last_to = "invalid";
404 IMAP0_OFFSET = 0xff00,
405 DMAP0_OFFSET = 0xff08,
406 DMAP2_SHADDOW = 0xff04,
407 DMAP2_OFFSET = 0xff0c
411 dmap_register (void *regcache, int reg_nr)
413 uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
414 + DMAP0_OFFSET + 2 * reg_nr);
415 return READ_16 (raw);
419 imap_register (void *regcache, int reg_nr)
421 uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
422 + IMAP0_OFFSET + 2 * reg_nr);
423 return READ_16 (raw);
426 /* Given a virtual address in the DMAP address space, translate it
427 into a physical address. */
430 sim_cr16_translate_dmap_addr (unsigned long offset,
434 unsigned long (*dmap_register) (void *regcache,
439 last_from = "logical-data";
440 if (offset >= DMAP_BLOCK_SIZE * SIM_CR16_NR_DMAP_REGS)
442 /* Logical address out side of data segments, not supported */
445 regno = (offset / DMAP_BLOCK_SIZE);
446 offset = (offset % DMAP_BLOCK_SIZE);
449 if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE)
451 /* Don't cross a BLOCK boundary */
452 nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE);
454 map = dmap_register (regcache, regno);
457 /* Always maps to data memory */
458 int iospi = (offset / 0x1000) % 4;
459 int iosp = (map >> (4 * (3 - iospi))) % 0x10;
460 last_to = "io-space";
461 *phys = (SIM_CR16_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset);
465 int sp = ((map & 0x3000) >> 12);
466 int segno = (map & 0x3ff);
469 case 0: /* 00: Unified memory */
470 *phys = SIM_CR16_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset;
473 case 1: /* 01: Instruction Memory */
474 *phys = SIM_CR16_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset;
475 last_to = "chip-insn";
477 case 2: /* 10: Internal data memory */
478 *phys = SIM_CR16_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset;
479 last_to = "chip-data";
481 case 3: /* 11: Reserved */
489 /* Given a virtual address in the IMAP address space, translate it
490 into a physical address. */
493 sim_cr16_translate_imap_addr (unsigned long offset,
497 unsigned long (*imap_register) (void *regcache,
504 last_from = "logical-insn";
505 if (offset >= (IMAP_BLOCK_SIZE * SIM_CR16_NR_IMAP_REGS))
507 /* Logical address outside of IMAP segments, not supported */
510 regno = (offset / IMAP_BLOCK_SIZE);
511 offset = (offset % IMAP_BLOCK_SIZE);
512 if (offset + nr_bytes > IMAP_BLOCK_SIZE)
514 /* Don't cross a BLOCK boundary */
515 nr_bytes = IMAP_BLOCK_SIZE - offset;
517 map = imap_register (regcache, regno);
518 sp = (map & 0x3000) >> 12;
519 segno = (map & 0x007f);
522 case 0: /* 00: unified memory */
523 *phys = SIM_CR16_MEMORY_UNIFIED + (segno << 17) + offset;
526 case 1: /* 01: instruction memory */
527 *phys = SIM_CR16_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset;
528 last_to = "chip-insn";
533 case 3: /* 11: for testing - instruction memory */
534 offset = (offset % 0x800);
535 *phys = SIM_CR16_MEMORY_INSN + offset;
536 if (offset + nr_bytes > 0x800)
537 /* don't cross VM boundary */
538 nr_bytes = 0x800 - offset;
539 last_to = "test-insn";
546 sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes,
547 unsigned long *targ_addr, void *regcache,
548 unsigned long (*dmap_register) (void *regcache,
550 unsigned long (*imap_register) (void *regcache,
557 last_from = "unknown";
560 seg = (memaddr >> 24);
561 off = (memaddr & 0xffffffL);
565 case 0x00: /* Physical unified memory */
566 last_from = "phys-unified";
568 phys = SIM_CR16_MEMORY_UNIFIED + off;
569 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
570 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
573 case 0x01: /* Physical instruction memory */
574 last_from = "phys-insn";
575 last_to = "chip-insn";
576 phys = SIM_CR16_MEMORY_INSN + off;
577 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
578 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
581 case 0x02: /* Physical data memory segment */
582 last_from = "phys-data";
583 last_to = "chip-data";
584 phys = SIM_CR16_MEMORY_DATA + off;
585 if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
586 nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
589 case 0x10: /* in logical data address segment */
590 nr_bytes = sim_cr16_translate_dmap_addr (off, nr_bytes, &phys, regcache,
594 case 0x11: /* in logical instruction address segment */
595 nr_bytes = sim_cr16_translate_imap_addr (off, nr_bytes, &phys, regcache,
607 /* Return a pointer into the raw buffer designated by phys_addr. It
608 is assumed that the client has already ensured that the access
609 isn't going to cross a segment boundary. */
612 map_memory (unsigned phys_addr)
617 int segment = ((phys_addr >> 24) & 0xff);
622 case 0x00: /* Unified memory */
624 memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS];
625 last_segname = "umem";
629 case 0x01: /* On-chip insn memory */
631 memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS];
632 last_segname = "imem";
636 case 0x02: /* On-chip data memory */
638 if ((phys_addr & 0xff00) == 0xff00)
640 phys_addr = (phys_addr & 0xffff);
641 if (phys_addr == DMAP2_SHADDOW)
643 phys_addr = DMAP2_OFFSET;
644 last_segname = "dmap";
647 last_segname = "reg";
650 last_segname = "dmem";
651 memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS];
657 last_segname = "scrap";
658 return State.mem.fault;
663 *memory = calloc (1, SEGMENT_SIZE);
666 (*cr16_callback->printf_filtered) (cr16_callback, "Malloc failed.\n");
667 return State.mem.fault;
671 offset = (phys_addr % SEGMENT_SIZE);
672 raw = *memory + offset;
676 /* Transfer data to/from simulated memory. Since a bug in either the
677 simulated program or in gdb or the simulator itself may cause a
678 bogus address to be passed in, we need to do some sanity checking
679 on addresses to make sure they are within bounds. When an address
680 fails the bounds check, treat it as a zero length read/write rather
681 than aborting the entire run. */
684 xfer_mem (SIM_DESC sd, SIM_ADDR virt,
685 unsigned char *buffer,
689 host_callback *cr16_callback = STATE_CALLBACK (sd);
693 phys_size = sim_cr16_translate_addr (virt, size, &phys, NULL,
694 dmap_register, imap_register);
698 memory = map_memory (phys);
701 if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
703 (*cr16_callback->printf_filtered)
705 "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
706 (write_p ? "write" : "read"),
707 phys_size, virt, last_from,
709 (long) memory, last_segname);
715 memcpy (memory, buffer, phys_size);
719 memcpy (buffer, memory, phys_size);
727 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
729 /* FIXME: this should be performing a virtual transfer */
730 return xfer_mem (sd, addr, buffer, size, 1);
734 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
736 /* FIXME: this should be performing a virtual transfer */
737 return xfer_mem (sd, addr, buffer, size, 0);
741 free_state (SIM_DESC sd)
743 if (STATE_MODULES (sd) != NULL)
744 sim_module_uninstall (sd);
745 sim_cpu_free_all (sd);
749 SIM_DESC trace_sd = NULL;
752 sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, struct bfd *abfd, char **argv)
755 struct hash_entry *h;
756 static int init_p = 0;
759 SIM_DESC sd = sim_state_alloc (kind, cb);
760 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
762 /* The cpu data is kept in a separately allocated chunk of memory. */
763 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
769 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
775 /* getopt will print the error message so we just have to exit if this fails.
776 FIXME: Hmmm... in the case of gdb we need getopt to call
778 if (sim_parse_args (sd, argv) != SIM_RC_OK)
784 /* Check for/establish the a reference program image. */
785 if (sim_analyze_program (sd,
786 (STATE_PROG_ARGV (sd) != NULL
787 ? *STATE_PROG_ARGV (sd)
788 : NULL), abfd) != SIM_RC_OK)
794 /* Configure/verify the target byte order and other runtime
795 configuration options. */
796 if (sim_config (sd) != SIM_RC_OK)
798 sim_module_uninstall (sd);
802 if (sim_post_argv_init (sd) != SIM_RC_OK)
804 /* Uninstall the modules to avoid memory leaks,
805 file descriptor leaks, etc. */
806 sim_module_uninstall (sd);
813 /* put all the opcodes in the hash table. */
816 for (s = Simops; s->func; s++)
821 h = &hash_table[hash(s->opcode, 0)];
825 if (((s->opcode << 1) >> 4) != 0)
826 h = &hash_table[hash((s->opcode << 1) >> 4, 0)];
828 h = &hash_table[hash((s->opcode << 1), 0)];
832 if ((s->opcode >> 4) != 0)
833 h = &hash_table[hash(s->opcode >> 4, 0)];
835 h = &hash_table[hash(s->opcode, 0)];
839 if (((s->opcode >> 1) >> 4) != 0)
840 h = &hash_table[hash((s->opcode >>1) >> 4, 0)];
842 h = &hash_table[hash((s->opcode >> 1), 0)];
846 if ((s->opcode >> 8) != 0)
847 h = &hash_table[hash(s->opcode >> 8, 0)];
848 else if ((s->opcode >> 4) != 0)
849 h = &hash_table[hash(s->opcode >> 4, 0)];
851 h = &hash_table[hash(s->opcode, 0)];
855 if ((s->opcode >> 8) != 0)
856 h = &hash_table[hash(s->opcode >> 8, 0)];
857 else if ((s->opcode >> 4) != 0)
858 h = &hash_table[hash(s->opcode >> 4, 0)];
860 h = &hash_table[hash(s->opcode, 0)];
864 if (((s->opcode >> 1) >> 8) != 0)
865 h = &hash_table[hash((s->opcode >>1) >> 8, 0)];
866 else if (((s->opcode >> 1) >> 4) != 0)
867 h = &hash_table[hash((s->opcode >>1) >> 4, 0)];
869 h = &hash_table[hash((s->opcode >>1), 0)];
873 if ((s->opcode >> 0xc) != 0)
874 h = &hash_table[hash(s->opcode >> 12, 0)];
875 else if ((s->opcode >> 8) != 0)
876 h = &hash_table[hash(s->opcode >> 8, 0)];
877 else if ((s->opcode >> 4) != 0)
878 h = &hash_table[hash(s->opcode >> 4, 0)];
880 h = &hash_table[hash(s->opcode, 0)];
884 if ((s->opcode >> 16) != 0)
885 h = &hash_table[hash(s->opcode >> 16, 0)];
886 else if ((s->opcode >> 12) != 0)
887 h = &hash_table[hash(s->opcode >> 12, 0)];
888 else if ((s->opcode >> 8) != 0)
889 h = &hash_table[hash(s->opcode >> 8, 0)];
890 else if ((s->opcode >> 4) != 0)
891 h = &hash_table[hash(s->opcode >> 4, 0)];
893 h = &hash_table[hash(s->opcode, 0)];
899 /* go to the last entry in the chain. */
905 h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
907 perror ("malloc failure");
913 h->opcode = s->opcode;
914 h->format = s->format;
919 /* reset the processor state */
920 if (!State.mem.data[0])
922 sim_create_inferior ((SIM_DESC) 1, NULL, NULL, NULL);
929 sim_close (SIM_DESC sd, int quitting)
935 dmem_addr (uint32 offset)
941 /* Note: DMEM address range is 0..0x10000. Calling code can compute
942 things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
943 is uint16 this is modulo'ed onto 0x0e5d. */
945 phys_size = sim_cr16_translate_dmap_addr (offset, 1, &phys, NULL,
949 mem = State.mem.fault;
952 mem = map_memory (phys);
954 if ((cr16_debug & DEBUG_MEMORY))
956 (*cr16_callback->printf_filtered)
958 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
960 phys, phys_size, last_to,
961 (long) mem, last_segname);
968 imem_addr (uint32 offset)
972 int phys_size = sim_cr16_translate_imap_addr (offset, 1, &phys, NULL,
976 return State.mem.fault;
978 mem = map_memory (phys);
980 if ((cr16_debug & DEBUG_MEMORY))
982 (*cr16_callback->printf_filtered)
984 "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
986 phys, phys_size, last_to,
987 (long) mem, last_segname);
993 static int stop_simulator = 0;
996 sim_stop (SIM_DESC sd)
1003 /* Run (or resume) the program. */
1005 sim_resume (SIM_DESC sd, int step, int siggnal)
1007 uint32 curr_ins_size = 0;
1012 // (*cr16_callback->printf_filtered) (cr16_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC);
1015 State.exception = 0;
1029 JMP (AE_VECTOR_START);
1035 SET_HW_PSR ((PSR & (PSR_C_BIT)));
1036 JMP (RIE_VECTOR_START);
1040 /* just ignore it */
1046 iaddr = imem_addr ((uint32)PC);
1047 if (iaddr == State.mem.fault)
1050 State.exception = SIGBUS;
1052 State.exception = SIGSEGV;
1057 mcode = get_longword( iaddr );
1059 State.pc_changed = 0;
1061 curr_ins_size = do_run(sd, mcode);
1064 (*cr16_callback->printf_filtered) (cr16_callback, "INS: PC=0x%X, mcode=0x%X\n",PC,mcode);
1067 if (!State.pc_changed)
1069 if (curr_ins_size == 0)
1071 State.exception = SIG_CR16_EXIT; /* exit trap */
1075 SET_PC (PC + (curr_ins_size * 2)); /* For word instructions. */
1079 /* Check for a breakpoint trap on this instruction. This
1080 overrides any pending branches or loops */
1081 if (PSR_DB && PC == DBS)
1085 SET_PC (SDBT_VECTOR_START);
1089 /* Writeback all the DATA / PC changes */
1092 while ( !State.exception && !stop_simulator);
1094 if (step && !State.exception)
1095 State.exception = SIGTRAP;
1099 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
1101 bfd_vma start_address;
1103 /* reset all state information */
1104 memset (&State.regs, 0, (uintptr_t)&State.mem - (uintptr_t)&State.regs);
1106 /* There was a hack here to copy the values of argc and argv into r0
1107 and r1. The values were also saved into some high memory that
1108 won't be overwritten by the stack (0x7C00). The reason for doing
1109 this was to allow the 'run' program to accept arguments. Without
1110 the hack, this is not possible anymore. If the simulator is run
1111 from the debugger, arguments cannot be passed in, so this makes
1116 start_address = bfd_get_start_address (abfd);
1118 start_address = 0x0;
1121 (*cr16_callback->printf_filtered) (cr16_callback, "sim_create_inferior: PC=0x%lx\n", (long) start_address);
1123 SET_CREG (PC_CR, start_address);
1130 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
1132 /* (*cr16_callback->printf_filtered) (cr16_callback, "sim_stop_reason: PC=0x%x\n",PC<<2); */
1134 switch (State.exception)
1136 case SIG_CR16_STOP: /* stop instruction */
1137 *reason = sim_stopped;
1141 case SIG_CR16_EXIT: /* exit trap */
1142 *reason = sim_exited;
1147 *reason = sim_stopped;
1148 *sigrc = GDB_SIGNAL_BUS;
1151 // case SIG_CR16_IAD:
1152 // *reason = sim_stopped;
1153 // *sigrc = GDB_SIGNAL_IAD;
1156 default: /* some signal */
1157 *reason = sim_stopped;
1158 if (stop_simulator && !State.exception)
1159 *sigrc = GDB_SIGNAL_INT;
1161 *sigrc = State.exception;
1169 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1172 switch ((enum sim_cr16_regs) rn)
1174 case SIM_CR16_R0_REGNUM:
1175 case SIM_CR16_R1_REGNUM:
1176 case SIM_CR16_R2_REGNUM:
1177 case SIM_CR16_R3_REGNUM:
1178 case SIM_CR16_R4_REGNUM:
1179 case SIM_CR16_R5_REGNUM:
1180 case SIM_CR16_R6_REGNUM:
1181 case SIM_CR16_R7_REGNUM:
1182 case SIM_CR16_R8_REGNUM:
1183 case SIM_CR16_R9_REGNUM:
1184 case SIM_CR16_R10_REGNUM:
1185 case SIM_CR16_R11_REGNUM:
1186 WRITE_16 (memory, GPR (rn - SIM_CR16_R0_REGNUM));
1189 case SIM_CR16_R12_REGNUM:
1190 case SIM_CR16_R13_REGNUM:
1191 case SIM_CR16_R14_REGNUM:
1192 case SIM_CR16_R15_REGNUM:
1193 //WRITE_32 (memory, GPR (rn - SIM_CR16_R0_REGNUM));
1194 write_longword (memory, GPR (rn - SIM_CR16_R0_REGNUM));
1197 case SIM_CR16_PC_REGNUM:
1198 case SIM_CR16_ISP_REGNUM:
1199 case SIM_CR16_USP_REGNUM:
1200 case SIM_CR16_INTBASE_REGNUM:
1201 case SIM_CR16_PSR_REGNUM:
1202 case SIM_CR16_CFG_REGNUM:
1203 case SIM_CR16_DBS_REGNUM:
1204 case SIM_CR16_DCR_REGNUM:
1205 case SIM_CR16_DSR_REGNUM:
1206 case SIM_CR16_CAR0_REGNUM:
1207 case SIM_CR16_CAR1_REGNUM:
1208 //WRITE_32 (memory, CREG (rn - SIM_CR16_PC_REGNUM));
1209 write_longword (memory, CREG (rn - SIM_CR16_PC_REGNUM));
1220 sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1223 switch ((enum sim_cr16_regs) rn)
1225 case SIM_CR16_R0_REGNUM:
1226 case SIM_CR16_R1_REGNUM:
1227 case SIM_CR16_R2_REGNUM:
1228 case SIM_CR16_R3_REGNUM:
1229 case SIM_CR16_R4_REGNUM:
1230 case SIM_CR16_R5_REGNUM:
1231 case SIM_CR16_R6_REGNUM:
1232 case SIM_CR16_R7_REGNUM:
1233 case SIM_CR16_R8_REGNUM:
1234 case SIM_CR16_R9_REGNUM:
1235 case SIM_CR16_R10_REGNUM:
1236 case SIM_CR16_R11_REGNUM:
1237 SET_GPR (rn - SIM_CR16_R0_REGNUM, READ_16 (memory));
1240 case SIM_CR16_R12_REGNUM:
1241 case SIM_CR16_R13_REGNUM:
1242 case SIM_CR16_R14_REGNUM:
1243 case SIM_CR16_R15_REGNUM:
1244 SET_GPR32 (rn - SIM_CR16_R0_REGNUM, get_longword (memory));
1247 case SIM_CR16_PC_REGNUM:
1248 case SIM_CR16_ISP_REGNUM:
1249 case SIM_CR16_USP_REGNUM:
1250 case SIM_CR16_INTBASE_REGNUM:
1251 case SIM_CR16_PSR_REGNUM:
1252 case SIM_CR16_CFG_REGNUM:
1253 case SIM_CR16_DBS_REGNUM:
1254 case SIM_CR16_DCR_REGNUM:
1255 case SIM_CR16_DSR_REGNUM:
1256 case SIM_CR16_CAR0_REGNUM:
1257 case SIM_CR16_CAR1_REGNUM:
1258 SET_CREG (rn - SIM_CR16_PC_REGNUM, get_longword (memory));