1 /* This file is part of the program psim.
3 Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 #error "N must be #defined"
29 /* N: The number of bytes of data to transfer.
30 M: The number of bytes in the type used to transfer the data */
33 #error "N (nr bytes of data) must be <= M (nr of bytes in data type)"
39 /* NOTE: see end of file for #undef of these macros */
41 #define unsigned_M XCONCAT2(unsigned_,M)
43 #define T2H_M XCONCAT2(T2H_,M)
44 #define H2T_M XCONCAT2(H2T_,M)
45 #define SWAP_M XCONCAT2(SWAP_,M)
47 #define sim_core_read_aligned_N XCONCAT2(sim_core_read_aligned_,N)
48 #define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N)
49 #define sim_core_read_misaligned_N XCONCAT2(sim_core_read_misaligned_,N)
50 #define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N)
51 #define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
52 #define sim_core_write_misaligned_N XCONCAT2(sim_core_write_misaligned_,N)
53 #define sim_core_trace_M XCONCAT2(sim_core_trace_,M)
54 #define sim_core_dummy_M XCONCAT2(sim_core_dummy_,M)
58 /* dummy variable used as a return value when nothing else is
59 available and the compiler is complaining */
60 static unsigned_M sim_core_dummy_M;
64 /* TAGS: sim_core_trace_1 sim_core_trace_2 */
65 /* TAGS: sim_core_trace_4 sim_core_trace_8 */
66 /* TAGS: sim_core_trace_16 */
70 sim_core_trace_M (sim_cpu *cpu,
79 char *transfer = (type == read_transfer ? "read" : "write");
80 char *direction = (type == read_transfer ? "->" : "<-");
82 if (TRACE_DEBUG_P (cpu))
83 trace_printf (CPU_STATE (cpu), cpu, "sim-n-core.h:%d: ", line_nr);
86 trace_printf (CPU_STATE (cpu), cpu,
87 "%s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx\n",
89 sim_core_map_to_str (map),
92 (unsigned long) V4_16 (val, 0),
93 (unsigned long) V4_16 (val, 1),
94 (unsigned long) V4_16 (val, 2),
95 (unsigned long) V4_16 (val, 3));
98 trace_printf (CPU_STATE (cpu), cpu,
99 "%s-%d %s:0x%08lx %s 0x%08lx%08lx\n",
101 sim_core_map_to_str (map),
102 (unsigned long) addr,
104 (unsigned long) V4_8 (val, 0),
105 (unsigned long) V4_8 (val, 1));
108 trace_printf (CPU_STATE (cpu), cpu,
109 "%s-%d %s:0x%08lx %s 0x%08lx\n",
112 sim_core_map_to_str (map),
113 (unsigned long) addr,
115 (unsigned long) val);
118 trace_printf (CPU_STATE (cpu), cpu,
119 "%s-%d %s:0x%08lx %s 0x%04lx\n",
122 sim_core_map_to_str (map),
123 (unsigned long) addr,
125 (unsigned long) val);
128 trace_printf (CPU_STATE (cpu), cpu,
129 "%s-%d %s:0x%08lx %s 0x%02lx\n",
132 sim_core_map_to_str (map),
133 (unsigned long) addr,
135 (unsigned long) val);
141 /* TAGS: sim_core_read_aligned_1 sim_core_read_aligned_2 */
142 /* TAGS: sim_core_read_aligned_4 sim_core_read_aligned_8 */
143 /* TAGS: sim_core_read_aligned_16 */
146 INLINE_SIM_CORE(unsigned_M)
147 sim_core_read_aligned_N(sim_cpu *cpu,
152 sim_cpu_core *cpu_core = CPU_CORE (cpu);
153 sim_core_common *core = &cpu_core->common;
155 sim_core_mapping *mapping;
157 #if WITH_XOR_ENDIAN != 0
159 addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
163 mapping = sim_core_find_mapping (core, map, addr, N, read_transfer, 1 /*abort*/, cpu, cia);
165 if (WITH_CALLBACK_MEMORY && mapping->device != NULL) {
167 if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N)
168 device_error (mapping->device, "internal error - %s - io_read_buffer should not fail",
169 XSTRING (sim_core_read_aligned_N));
174 val = T2H_M (*(unsigned_M*) sim_core_translate (mapping, addr));
175 PROFILE_COUNT_CORE (cpu, addr, N, map);
176 if (TRACE_P (cpu, TRACE_CORE_IDX))
177 sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
182 /* TAGS: sim_core_read_unaligned_1 sim_core_read_unaligned_2 */
183 /* TAGS: sim_core_read_unaligned_4 sim_core_read_unaligned_8 */
184 /* TAGS: sim_core_read_unaligned_16 */
186 #if (M == N && N > 1)
187 INLINE_SIM_CORE(unsigned_M)
188 sim_core_read_unaligned_N(sim_cpu *cpu,
193 int alignment = N - 1;
194 /* if hardwired to forced alignment just do it */
195 if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
196 return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
197 else if ((addr & alignment) == 0)
198 return sim_core_read_aligned_N (cpu, cia, map, addr);
200 switch (CURRENT_ALIGNMENT)
202 case STRICT_ALIGNMENT:
203 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
204 read_transfer, sim_core_unaligned_signal);
205 case NONSTRICT_ALIGNMENT:
208 if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
209 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
210 read_transfer, sim_core_unaligned_signal);
212 PROFILE_COUNT_CORE (cpu, addr, N, map);
213 if (TRACE_P (cpu, TRACE_CORE_IDX))
214 sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
217 case FORCED_ALIGNMENT:
218 return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
219 case MIXED_ALIGNMENT:
220 sim_engine_abort (CPU_STATE (cpu), cpu, cia,
221 "internal error - %s - mixed alignment",
222 XSTRING (sim_core_read_unaligned_N));
224 sim_engine_abort (CPU_STATE (cpu), cpu, cia,
225 "internal error - %s - bad switch",
226 XSTRING (sim_core_read_unaligned_N));
227 /* to keep some compilers happy, we return a dummy */
228 return sim_core_dummy_M;
233 /* TAGS: sim_core_read_misaligned_3 sim_core_read_misaligned_5 */
234 /* TAGS: sim_core_read_misaligned_6 sim_core_read_misaligned_7 */
237 INLINE_SIM_CORE(unsigned_M)
238 sim_core_read_misaligned_N(sim_cpu *cpu,
244 if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
245 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
246 read_transfer, sim_core_unaligned_signal);
247 if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
249 if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
251 PROFILE_COUNT_CORE (cpu, addr, N, map);
252 if (TRACE_P (cpu, TRACE_CORE_IDX))
253 sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
258 /* TAGS: sim_core_write_aligned_1 sim_core_write_aligned_2 */
259 /* TAGS: sim_core_write_aligned_4 sim_core_write_aligned_8 */
260 /* TAGS: sim_core_write_aligned_16 */
263 INLINE_SIM_CORE(void)
264 sim_core_write_aligned_N(sim_cpu *cpu,
270 sim_cpu_core *cpu_core = CPU_CORE (cpu);
271 sim_core_common *core = &cpu_core->common;
272 sim_core_mapping *mapping;
274 #if WITH_XOR_ENDIAN != 0
276 addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
280 mapping = sim_core_find_mapping (core, map, addr, N, write_transfer, 1 /*abort*/, cpu, cia);
282 if (WITH_CALLBACK_MEMORY && mapping->device != NULL) {
283 unsigned_M data = H2T_M (val);
284 if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N)
285 device_error (mapping->device, "internal error - %s - io_write_buffer should not fail",
286 XSTRING (sim_core_write_aligned_N));
290 *(unsigned_M*) sim_core_translate (mapping, addr) = H2T_M (val);
291 PROFILE_COUNT_CORE (cpu, addr, N, map);
292 if (TRACE_P (cpu, TRACE_CORE_IDX))
293 sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
297 /* TAGS: sim_core_write_unaligned_1 sim_core_write_unaligned_2 */
298 /* TAGS: sim_core_write_unaligned_4 sim_core_write_unaligned_8 */
299 /* TAGS: sim_core_write_unaligned_16 */
301 #if (M == N && N > 1)
302 INLINE_SIM_CORE(void)
303 sim_core_write_unaligned_N(sim_cpu *cpu,
309 int alignment = N - 1;
310 /* if hardwired to forced alignment just do it */
311 if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
312 sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
313 else if ((addr & alignment) == 0)
314 sim_core_write_aligned_N (cpu, cia, map, addr, val);
316 switch (CURRENT_ALIGNMENT)
318 case STRICT_ALIGNMENT:
319 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
320 write_transfer, sim_core_unaligned_signal);
322 case NONSTRICT_ALIGNMENT:
324 unsigned_M data = H2T_M (val);
325 if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
326 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
327 write_transfer, sim_core_unaligned_signal);
328 PROFILE_COUNT_CORE (cpu, addr, N, map);
329 if (TRACE_P (cpu, TRACE_CORE_IDX))
330 sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
333 case FORCED_ALIGNMENT:
334 sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
336 case MIXED_ALIGNMENT:
337 sim_engine_abort (CPU_STATE (cpu), cpu, cia,
338 "internal error - %s - mixed alignment",
339 XSTRING (sim_core_write_unaligned_N));
342 sim_engine_abort (CPU_STATE (cpu), cpu, cia,
343 "internal error - %s - bad switch",
344 XSTRING (sim_core_write_unaligned_N));
350 /* TAGS: sim_core_write_misaligned_3 sim_core_write_misaligned_5 */
351 /* TAGS: sim_core_write_misaligned_6 sim_core_write_misaligned_7 */
354 INLINE_SIM_CORE(void)
355 sim_core_write_misaligned_N(sim_cpu *cpu,
361 unsigned_M data = val;
362 if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
363 data <<= (M - N) * 8;
364 if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
365 data = SWAP_M (data);
366 if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
367 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
368 write_transfer, sim_core_unaligned_signal);
369 PROFILE_COUNT_CORE (cpu, addr, N, map);
370 if (TRACE_P (cpu, TRACE_CORE_IDX))
371 sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
376 /* NOTE: see start of file for #define of these macros */
381 #undef sim_core_read_aligned_N
382 #undef sim_core_read_unaligned_N
383 #undef sim_core_read_misaligned_N
384 #undef sim_core_write_aligned_N
385 #undef sim_core_write_unaligned_N
386 #undef sim_core_write_misaligned_N
387 #undef sim_core_trace_M
388 #undef sim_core_dummy_M