1 /* The common simulator framework for GDB, the GNU Debugger.
3 Copyright 2002 Free Software Foundation, Inc.
5 Contributed by Andrew Cagney and Red Hat.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #error "N must be #defined"
32 /* N: The number of bytes of data to transfer.
33 M: The number of bytes in the type used to transfer the data */
36 #error "N (nr bytes of data) must be <= M (nr of bytes in data type)"
42 /* NOTE: see end of file for #undef of these macros */
44 #define unsigned_M XCONCAT2(unsigned_,M)
46 #define T2H_M XCONCAT2(T2H_,M)
47 #define H2T_M XCONCAT2(H2T_,M)
48 #define SWAP_M XCONCAT2(SWAP_,M)
50 #define sim_core_read_aligned_N XCONCAT2(sim_core_read_aligned_,N)
51 #define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N)
52 #define sim_core_read_misaligned_N XCONCAT2(sim_core_read_misaligned_,N)
53 #define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N)
54 #define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
55 #define sim_core_write_misaligned_N XCONCAT2(sim_core_write_misaligned_,N)
56 #define sim_core_trace_M XCONCAT2(sim_core_trace_,M)
57 #define sim_core_dummy_M XCONCAT2(sim_core_dummy_,M)
61 /* dummy variable used as a return value when nothing else is
62 available and the compiler is complaining */
63 static unsigned_M sim_core_dummy_M;
67 /* TAGS: sim_core_trace_1 sim_core_trace_2 */
68 /* TAGS: sim_core_trace_4 sim_core_trace_8 */
69 /* TAGS: sim_core_trace_16 */
73 sim_core_trace_M (sim_cpu *cpu,
82 const char *transfer = (type == read_transfer ? "read" : "write");
83 const char *direction = (type == read_transfer ? "->" : "<-");
85 if (TRACE_DEBUG_P (cpu))
86 trace_printf (CPU_STATE (cpu), cpu, "sim-n-core.h:%d: ", line_nr);
89 trace_printf (CPU_STATE (cpu), cpu,
90 "%s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx\n",
95 (unsigned long) V4_16 (val, 0),
96 (unsigned long) V4_16 (val, 1),
97 (unsigned long) V4_16 (val, 2),
98 (unsigned long) V4_16 (val, 3));
101 trace_printf (CPU_STATE (cpu), cpu,
102 "%s-%d %s:0x%08lx %s 0x%08lx%08lx\n",
105 (unsigned long) addr,
107 (unsigned long) V4_8 (val, 0),
108 (unsigned long) V4_8 (val, 1));
111 trace_printf (CPU_STATE (cpu), cpu,
112 "%s-%d %s:0x%08lx %s 0x%08lx\n",
116 (unsigned long) addr,
118 (unsigned long) val);
121 trace_printf (CPU_STATE (cpu), cpu,
122 "%s-%d %s:0x%08lx %s 0x%04lx\n",
126 (unsigned long) addr,
128 (unsigned long) val);
131 trace_printf (CPU_STATE (cpu), cpu,
132 "%s-%d %s:0x%08lx %s 0x%02lx\n",
136 (unsigned long) addr,
138 (unsigned long) val);
144 /* TAGS: sim_core_read_aligned_1 sim_core_read_aligned_2 */
145 /* TAGS: sim_core_read_aligned_4 sim_core_read_aligned_8 */
146 /* TAGS: sim_core_read_aligned_16 */
149 INLINE_SIM_CORE(unsigned_M)
150 sim_core_read_aligned_N(sim_cpu *cpu,
155 sim_cpu_core *cpu_core = CPU_CORE (cpu);
156 sim_core_common *core = &cpu_core->common;
158 sim_core_mapping *mapping;
160 #if WITH_XOR_ENDIAN != 0
162 addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
166 mapping = sim_core_find_mapping (core, map, addr, N, read_transfer, 1 /*abort*/, cpu, cia);
170 if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
173 if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N)
174 device_error (mapping->device, "internal error - %s - io_read_buffer should not fail",
175 XSTRING (sim_core_read_aligned_N));
181 if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
184 sim_cpu_hw_io_read_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N);
189 val = T2H_M (*(unsigned_M*) sim_core_translate (mapping, addr));
192 PROFILE_COUNT_CORE (cpu, addr, N, map);
193 if (TRACE_P (cpu, TRACE_CORE_IDX))
194 sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
199 /* TAGS: sim_core_read_unaligned_1 sim_core_read_unaligned_2 */
200 /* TAGS: sim_core_read_unaligned_4 sim_core_read_unaligned_8 */
201 /* TAGS: sim_core_read_unaligned_16 */
203 #if (M == N && N > 1)
204 INLINE_SIM_CORE(unsigned_M)
205 sim_core_read_unaligned_N(sim_cpu *cpu,
210 int alignment = N - 1;
211 /* if hardwired to forced alignment just do it */
212 if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
213 return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
214 else if ((addr & alignment) == 0)
215 return sim_core_read_aligned_N (cpu, cia, map, addr);
217 switch (CURRENT_ALIGNMENT)
219 case STRICT_ALIGNMENT:
220 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
221 read_transfer, sim_core_unaligned_signal);
222 case NONSTRICT_ALIGNMENT:
225 if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
226 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
227 read_transfer, sim_core_unaligned_signal);
229 PROFILE_COUNT_CORE (cpu, addr, N, map);
230 if (TRACE_P (cpu, TRACE_CORE_IDX))
231 sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
234 case FORCED_ALIGNMENT:
235 return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
236 case MIXED_ALIGNMENT:
237 sim_engine_abort (CPU_STATE (cpu), cpu, cia,
238 "internal error - %s - mixed alignment",
239 XSTRING (sim_core_read_unaligned_N));
241 sim_engine_abort (CPU_STATE (cpu), cpu, cia,
242 "internal error - %s - bad switch",
243 XSTRING (sim_core_read_unaligned_N));
244 /* to keep some compilers happy, we return a dummy */
245 return sim_core_dummy_M;
250 /* TAGS: sim_core_read_misaligned_3 sim_core_read_misaligned_5 */
251 /* TAGS: sim_core_read_misaligned_6 sim_core_read_misaligned_7 */
254 INLINE_SIM_CORE(unsigned_M)
255 sim_core_read_misaligned_N(sim_cpu *cpu,
261 if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
262 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
263 read_transfer, sim_core_unaligned_signal);
264 if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
266 if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
268 PROFILE_COUNT_CORE (cpu, addr, N, map);
269 if (TRACE_P (cpu, TRACE_CORE_IDX))
270 sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
275 /* TAGS: sim_core_write_aligned_1 sim_core_write_aligned_2 */
276 /* TAGS: sim_core_write_aligned_4 sim_core_write_aligned_8 */
277 /* TAGS: sim_core_write_aligned_16 */
280 INLINE_SIM_CORE(void)
281 sim_core_write_aligned_N(sim_cpu *cpu,
287 sim_cpu_core *cpu_core = CPU_CORE (cpu);
288 sim_core_common *core = &cpu_core->common;
289 sim_core_mapping *mapping;
291 #if WITH_XOR_ENDIAN != 0
293 addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
297 mapping = sim_core_find_mapping (core, map, addr, N, write_transfer, 1 /*abort*/, cpu, cia);
301 if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
303 unsigned_M data = H2T_M (val);
304 if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N)
305 device_error (mapping->device, "internal error - %s - io_write_buffer should not fail",
306 XSTRING (sim_core_write_aligned_N));
311 if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
313 unsigned_M data = H2T_M (val);
314 sim_cpu_hw_io_write_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N);
318 *(unsigned_M*) sim_core_translate (mapping, addr) = H2T_M (val);
321 PROFILE_COUNT_CORE (cpu, addr, N, map);
322 if (TRACE_P (cpu, TRACE_CORE_IDX))
323 sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
327 /* TAGS: sim_core_write_unaligned_1 sim_core_write_unaligned_2 */
328 /* TAGS: sim_core_write_unaligned_4 sim_core_write_unaligned_8 */
329 /* TAGS: sim_core_write_unaligned_16 */
331 #if (M == N && N > 1)
332 INLINE_SIM_CORE(void)
333 sim_core_write_unaligned_N(sim_cpu *cpu,
339 int alignment = N - 1;
340 /* if hardwired to forced alignment just do it */
341 if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
342 sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
343 else if ((addr & alignment) == 0)
344 sim_core_write_aligned_N (cpu, cia, map, addr, val);
346 switch (CURRENT_ALIGNMENT)
348 case STRICT_ALIGNMENT:
349 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
350 write_transfer, sim_core_unaligned_signal);
352 case NONSTRICT_ALIGNMENT:
354 unsigned_M data = H2T_M (val);
355 if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
356 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
357 write_transfer, sim_core_unaligned_signal);
358 PROFILE_COUNT_CORE (cpu, addr, N, map);
359 if (TRACE_P (cpu, TRACE_CORE_IDX))
360 sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
363 case FORCED_ALIGNMENT:
364 sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
366 case MIXED_ALIGNMENT:
367 sim_engine_abort (CPU_STATE (cpu), cpu, cia,
368 "internal error - %s - mixed alignment",
369 XSTRING (sim_core_write_unaligned_N));
372 sim_engine_abort (CPU_STATE (cpu), cpu, cia,
373 "internal error - %s - bad switch",
374 XSTRING (sim_core_write_unaligned_N));
380 /* TAGS: sim_core_write_misaligned_3 sim_core_write_misaligned_5 */
381 /* TAGS: sim_core_write_misaligned_6 sim_core_write_misaligned_7 */
384 INLINE_SIM_CORE(void)
385 sim_core_write_misaligned_N(sim_cpu *cpu,
391 unsigned_M data = val;
392 if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
393 data <<= (M - N) * 8;
394 if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
395 data = SWAP_M (data);
396 if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
397 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
398 write_transfer, sim_core_unaligned_signal);
399 PROFILE_COUNT_CORE (cpu, addr, N, map);
400 if (TRACE_P (cpu, TRACE_CORE_IDX))
401 sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
406 /* NOTE: see start of file for #define of these macros */
411 #undef sim_core_read_aligned_N
412 #undef sim_core_read_unaligned_N
413 #undef sim_core_read_misaligned_N
414 #undef sim_core_write_aligned_N
415 #undef sim_core_write_unaligned_N
416 #undef sim_core_write_misaligned_N
417 #undef sim_core_trace_M
418 #undef sim_core_dummy_M