1 /* The common simulator framework for GDB, the GNU Debugger.
3 Copyright 2002, 2007 Free Software Foundation, Inc.
5 Contributed by Andrew Cagney and Red Hat.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #error "N must be #defined"
30 /* N: The number of bytes of data to transfer.
31 M: The number of bytes in the type used to transfer the data */
34 #error "N (nr bytes of data) must be <= M (nr of bytes in data type)"
40 /* NOTE: see end of file for #undef of these macros */
42 #define unsigned_M XCONCAT2(unsigned_,M)
44 #define T2H_M XCONCAT2(T2H_,M)
45 #define H2T_M XCONCAT2(H2T_,M)
46 #define SWAP_M XCONCAT2(SWAP_,M)
48 #define sim_core_read_aligned_N XCONCAT2(sim_core_read_aligned_,N)
49 #define sim_core_read_unaligned_N XCONCAT2(sim_core_read_unaligned_,N)
50 #define sim_core_read_misaligned_N XCONCAT2(sim_core_read_misaligned_,N)
51 #define sim_core_write_aligned_N XCONCAT2(sim_core_write_aligned_,N)
52 #define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
53 #define sim_core_write_misaligned_N XCONCAT2(sim_core_write_misaligned_,N)
54 #define sim_core_trace_M XCONCAT2(sim_core_trace_,M)
55 #define sim_core_dummy_M XCONCAT2(sim_core_dummy_,M)
59 /* dummy variable used as a return value when nothing else is
60 available and the compiler is complaining */
61 static unsigned_M sim_core_dummy_M;
65 /* TAGS: sim_core_trace_1 sim_core_trace_2 */
66 /* TAGS: sim_core_trace_4 sim_core_trace_8 */
67 /* TAGS: sim_core_trace_16 */
71 sim_core_trace_M (sim_cpu *cpu,
80 const char *transfer = (type == read_transfer ? "read" : "write");
81 const char *direction = (type == read_transfer ? "->" : "<-");
83 if (TRACE_DEBUG_P (cpu))
84 trace_printf (CPU_STATE (cpu), cpu, "sim-n-core.h:%d: ", line_nr);
87 trace_printf (CPU_STATE (cpu), cpu,
88 "%s-%d %s:0x%08lx %s 0x%08lx%08lx%08lx%08lx\n",
93 (unsigned long) V4_16 (val, 0),
94 (unsigned long) V4_16 (val, 1),
95 (unsigned long) V4_16 (val, 2),
96 (unsigned long) V4_16 (val, 3));
99 trace_printf (CPU_STATE (cpu), cpu,
100 "%s-%d %s:0x%08lx %s 0x%08lx%08lx\n",
103 (unsigned long) addr,
105 (unsigned long) V4_8 (val, 0),
106 (unsigned long) V4_8 (val, 1));
109 trace_printf (CPU_STATE (cpu), cpu,
110 "%s-%d %s:0x%08lx %s 0x%08lx\n",
114 (unsigned long) addr,
116 (unsigned long) val);
119 trace_printf (CPU_STATE (cpu), cpu,
120 "%s-%d %s:0x%08lx %s 0x%04lx\n",
124 (unsigned long) addr,
126 (unsigned long) val);
129 trace_printf (CPU_STATE (cpu), cpu,
130 "%s-%d %s:0x%08lx %s 0x%02lx\n",
134 (unsigned long) addr,
136 (unsigned long) val);
142 /* TAGS: sim_core_read_aligned_1 sim_core_read_aligned_2 */
143 /* TAGS: sim_core_read_aligned_4 sim_core_read_aligned_8 */
144 /* TAGS: sim_core_read_aligned_16 */
147 INLINE_SIM_CORE(unsigned_M)
148 sim_core_read_aligned_N(sim_cpu *cpu,
153 sim_cpu_core *cpu_core = CPU_CORE (cpu);
154 sim_core_common *core = &cpu_core->common;
156 sim_core_mapping *mapping;
158 #if WITH_XOR_ENDIAN != 0
160 addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
164 mapping = sim_core_find_mapping (core, map, addr, N, read_transfer, 1 /*abort*/, cpu, cia);
168 if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
171 if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N)
172 device_error (mapping->device, "internal error - %s - io_read_buffer should not fail",
173 XSTRING (sim_core_read_aligned_N));
179 if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
182 sim_cpu_hw_io_read_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N);
187 val = T2H_M (*(unsigned_M*) sim_core_translate (mapping, addr));
190 PROFILE_COUNT_CORE (cpu, addr, N, map);
191 if (TRACE_P (cpu, TRACE_CORE_IDX))
192 sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
197 /* TAGS: sim_core_read_unaligned_1 sim_core_read_unaligned_2 */
198 /* TAGS: sim_core_read_unaligned_4 sim_core_read_unaligned_8 */
199 /* TAGS: sim_core_read_unaligned_16 */
201 #if (M == N && N > 1)
202 INLINE_SIM_CORE(unsigned_M)
203 sim_core_read_unaligned_N(sim_cpu *cpu,
208 int alignment = N - 1;
209 /* if hardwired to forced alignment just do it */
210 if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
211 return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
212 else if ((addr & alignment) == 0)
213 return sim_core_read_aligned_N (cpu, cia, map, addr);
215 switch (CURRENT_ALIGNMENT)
217 case STRICT_ALIGNMENT:
218 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
219 read_transfer, sim_core_unaligned_signal);
220 case NONSTRICT_ALIGNMENT:
223 if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
224 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
225 read_transfer, sim_core_unaligned_signal);
227 PROFILE_COUNT_CORE (cpu, addr, N, map);
228 if (TRACE_P (cpu, TRACE_CORE_IDX))
229 sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
232 case FORCED_ALIGNMENT:
233 return sim_core_read_aligned_N (cpu, cia, map, addr & ~alignment);
234 case MIXED_ALIGNMENT:
235 sim_engine_abort (CPU_STATE (cpu), cpu, cia,
236 "internal error - %s - mixed alignment",
237 XSTRING (sim_core_read_unaligned_N));
239 sim_engine_abort (CPU_STATE (cpu), cpu, cia,
240 "internal error - %s - bad switch",
241 XSTRING (sim_core_read_unaligned_N));
242 /* to keep some compilers happy, we return a dummy */
243 return sim_core_dummy_M;
248 /* TAGS: sim_core_read_misaligned_3 sim_core_read_misaligned_5 */
249 /* TAGS: sim_core_read_misaligned_6 sim_core_read_misaligned_7 */
252 INLINE_SIM_CORE(unsigned_M)
253 sim_core_read_misaligned_N(sim_cpu *cpu,
259 if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr, N) != N)
260 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
261 read_transfer, sim_core_unaligned_signal);
262 if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
264 if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
266 PROFILE_COUNT_CORE (cpu, addr, N, map);
267 if (TRACE_P (cpu, TRACE_CORE_IDX))
268 sim_core_trace_M (cpu, cia, __LINE__, read_transfer, map, addr, val, N);
273 /* TAGS: sim_core_write_aligned_1 sim_core_write_aligned_2 */
274 /* TAGS: sim_core_write_aligned_4 sim_core_write_aligned_8 */
275 /* TAGS: sim_core_write_aligned_16 */
278 INLINE_SIM_CORE(void)
279 sim_core_write_aligned_N(sim_cpu *cpu,
285 sim_cpu_core *cpu_core = CPU_CORE (cpu);
286 sim_core_common *core = &cpu_core->common;
287 sim_core_mapping *mapping;
289 #if WITH_XOR_ENDIAN != 0
291 addr = xaddr ^ cpu_core->xor[(N - 1) % WITH_XOR_ENDIAN];
295 mapping = sim_core_find_mapping (core, map, addr, N, write_transfer, 1 /*abort*/, cpu, cia);
299 if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
301 unsigned_M data = H2T_M (val);
302 if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N)
303 device_error (mapping->device, "internal error - %s - io_write_buffer should not fail",
304 XSTRING (sim_core_write_aligned_N));
309 if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
311 unsigned_M data = H2T_M (val);
312 sim_cpu_hw_io_write_buffer (cpu, cia, mapping->device, &data, mapping->space, addr, N);
316 *(unsigned_M*) sim_core_translate (mapping, addr) = H2T_M (val);
319 PROFILE_COUNT_CORE (cpu, addr, N, map);
320 if (TRACE_P (cpu, TRACE_CORE_IDX))
321 sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
325 /* TAGS: sim_core_write_unaligned_1 sim_core_write_unaligned_2 */
326 /* TAGS: sim_core_write_unaligned_4 sim_core_write_unaligned_8 */
327 /* TAGS: sim_core_write_unaligned_16 */
329 #if (M == N && N > 1)
330 INLINE_SIM_CORE(void)
331 sim_core_write_unaligned_N(sim_cpu *cpu,
337 int alignment = N - 1;
338 /* if hardwired to forced alignment just do it */
339 if (WITH_ALIGNMENT == FORCED_ALIGNMENT)
340 sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
341 else if ((addr & alignment) == 0)
342 sim_core_write_aligned_N (cpu, cia, map, addr, val);
344 switch (CURRENT_ALIGNMENT)
346 case STRICT_ALIGNMENT:
347 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
348 write_transfer, sim_core_unaligned_signal);
350 case NONSTRICT_ALIGNMENT:
352 unsigned_M data = H2T_M (val);
353 if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
354 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
355 write_transfer, sim_core_unaligned_signal);
356 PROFILE_COUNT_CORE (cpu, addr, N, map);
357 if (TRACE_P (cpu, TRACE_CORE_IDX))
358 sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
361 case FORCED_ALIGNMENT:
362 sim_core_write_aligned_N (cpu, cia, map, addr & ~alignment, val);
364 case MIXED_ALIGNMENT:
365 sim_engine_abort (CPU_STATE (cpu), cpu, cia,
366 "internal error - %s - mixed alignment",
367 XSTRING (sim_core_write_unaligned_N));
370 sim_engine_abort (CPU_STATE (cpu), cpu, cia,
371 "internal error - %s - bad switch",
372 XSTRING (sim_core_write_unaligned_N));
378 /* TAGS: sim_core_write_misaligned_3 sim_core_write_misaligned_5 */
379 /* TAGS: sim_core_write_misaligned_6 sim_core_write_misaligned_7 */
382 INLINE_SIM_CORE(void)
383 sim_core_write_misaligned_N(sim_cpu *cpu,
389 unsigned_M data = val;
390 if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
391 data <<= (M - N) * 8;
392 if (CURRENT_HOST_BYTE_ORDER != CURRENT_TARGET_BYTE_ORDER)
393 data = SWAP_M (data);
394 if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &data, addr, N) != N)
395 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, N, addr,
396 write_transfer, sim_core_unaligned_signal);
397 PROFILE_COUNT_CORE (cpu, addr, N, map);
398 if (TRACE_P (cpu, TRACE_CORE_IDX))
399 sim_core_trace_M (cpu, cia, __LINE__, write_transfer, map, addr, val, N);
404 /* NOTE: see start of file for #define of these macros */
409 #undef sim_core_read_aligned_N
410 #undef sim_core_read_unaligned_N
411 #undef sim_core_read_misaligned_N
412 #undef sim_core_write_aligned_N
413 #undef sim_core_write_unaligned_N
414 #undef sim_core_write_misaligned_N
415 #undef sim_core_trace_M
416 #undef sim_core_dummy_M