1 /* Simulator Floating-point support.
2 Copyright (C) 1997 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
28 /* The FPU intermediate type - this object, passed by reference,
29 should be treated as opaque.
32 Pragmatics - pass struct by ref:
34 The alternatives for this object/interface that were considered
35 were: a packed 64 bit value; an unpacked structure passed by value;
36 and an unpacked structure passed by reference.
38 The packed 64 bit value was rejected because: it limited the
39 precision of intermediate values; reasonable performance would only
40 be achieved when the sim_fpu package was in-lined allowing repeated
41 unpacking operations to be eliminated.
43 For unpacked structures (passed by value and reference), the code
44 quality of GCC-2.7 (on x86) for each alternative was compared.
45 Needless to say the results, while better then for a packed 64 bit
46 object, were still poor (GCC had only limited support for the
47 optimization of references to structure members). Regardless, the
48 struct-by-ref alternative achieved better results when compiled
49 with (better speed) and without (better code density) in-lining.
50 Here's looking forward to an improved GCC optimizer.
53 Pragmatics - avoid host FP hardware:
55 FP operations can be implemented by either: the host's floating
56 point hardware; or by emulating the FP operations using integer
57 only routines. This is direct tradeoff between speed, portability
60 The two principal reasons for selecting portability and correctness
63 1 - Correctness. The assumption that FP correctness wasn't an
64 issue for code being run on simulators was wrong. Instead of
65 running FP tolerant (?) code, simulator users instead typically run
66 very aggressive FP code sequences. The sole purpose of those
67 sequences being to test the target ISA's FP implementation.
69 2 - Portability. The host FP implementation is not predictable. A
70 simulator modeling aggressive FP code sequences using the hosts FPU
71 relies heavily on the correctness of the hosts FP implementation.
72 It turns out that such trust can be misplaced. The behavior of
73 host FP implementations when handling edge conditions such as SNaNs
74 and exceptions varied widely.
87 sim_fpu_class_infinity,
90 typedef struct _sim_fpu {
102 The value zero (sim_fpu_round_default) for ALU operations indicates
103 that, when possible, rounding should be avoided. */
107 sim_fpu_round_default = 0,
108 sim_fpu_round_near = 1,
109 sim_fpu_round_zero = 2,
110 sim_fpu_round_up = 3,
111 sim_fpu_round_down = 4,
115 /* Options when handling denormalized numbers. */
119 sim_fpu_denorm_underflow_inexact = 1,
120 sim_fpu_denorm_zero = 2,
125 /* Status values returned by FPU operators.
127 When checking the result of an FP sequence (ex 32to, add, single,
128 to32) the caller may either: check the return value of each FP
129 operator; or form the union (OR) of the returned values and examine
130 them once at the end.
132 FIXME: This facility is still being developed. The choice of
133 status values returned and their exact meaning may changed in the
138 sim_fpu_status_invalid_snan = 1,
139 sim_fpu_status_invalid_qnan = 2,
140 sim_fpu_status_invalid_isi = 4, /* (inf - inf) */
141 sim_fpu_status_invalid_idi = 8, /* (inf / inf) */
142 sim_fpu_status_invalid_zdz = 16, /* (0 / 0) */
143 sim_fpu_status_invalid_imz = 32, /* (inf * 0) */
144 sim_fpu_status_invalid_cvi = 64, /* convert to integer */
145 sim_fpu_status_invalid_div0 = 128, /* (X / 0) */
146 sim_fpu_status_invalid_cmp = 256, /* compare */
147 sim_fpu_status_invalid_sqrt = 512,
148 sim_fpu_status_rounded = 1024,
149 sim_fpu_status_inexact = 2048,
150 sim_fpu_status_overflow = 4096,
151 sim_fpu_status_underflow = 8192,
152 sim_fpu_status_denorm = 16384,
158 /* Directly map between a 32/64 bit register and the sim_fpu internal
161 When converting from the 32/64 bit packed format to the sim_fpu
162 internal type, the operation is exact.
164 When converting from the sim_fpu internal type to 32/64 bit packed
165 format, the operation may result in a loss of precision. The
166 configuration macro WITH_FPU_CONVERSION controls this. By default,
167 silent round to nearest is performed. Alternativly, round up,
168 round down and round to zero can be performed. In a simulator
169 emulating exact FPU behavour, sim_fpu_round_{32,64} should be
170 called before packing the sim_fpu value. */
172 INLINE_SIM_FPU (void) sim_fpu_32to (sim_fpu *f, unsigned32 s);
173 INLINE_SIM_FPU (void) sim_fpu_232to (sim_fpu *f, unsigned32 h, unsigned32 l);
174 INLINE_SIM_FPU (void) sim_fpu_64to (sim_fpu *f, unsigned64 d);
176 INLINE_SIM_FPU (void) sim_fpu_to32 (unsigned32 *s, const sim_fpu *f);
177 INLINE_SIM_FPU (void) sim_fpu_to232 (unsigned32 *h, unsigned32 *l, const sim_fpu *f);
178 INLINE_SIM_FPU (void) sim_fpu_to64 (unsigned64 *d, const sim_fpu *f);
180 #if WITH_TARGET_FLOATING_POINT_BITSIZE == 32
181 #define sim_fpu_tofp sim_fpu_to32
182 #define sim_fpu_fpto sim_fpu_32to
183 #define sim_fpu_round_fp sim_fpu_round_32
185 #if WITH_TARGET_FLOATING_POINT_BITSIZE == 64
186 #define sim_fpu_tofp sim_fpu_to64
187 #define sim_fpu_fpto sim_fpu_64to
188 #define sim_fpu_round_fp sim_fpu_round_64
192 /* Rounding operators.
194 Force an intermediate result to an exact 32/64 bit
197 INLINE_SIM_FPU (int) sim_fpu_round_32 (sim_fpu *f,
199 sim_fpu_denorm denorm);
200 INLINE_SIM_FPU (int) sim_fpu_round_64 (sim_fpu *f,
202 sim_fpu_denorm denorm);
206 /* Arrithmetic operators.
208 FIXME: In the future, additional arguments ROUNDING and BITSIZE may
211 INLINE_SIM_FPU (int) sim_fpu_add (sim_fpu *f,
212 const sim_fpu *l, const sim_fpu *r);
213 INLINE_SIM_FPU (int) sim_fpu_sub (sim_fpu *f,
214 const sim_fpu *l, const sim_fpu *r);
215 INLINE_SIM_FPU (int) sim_fpu_mul (sim_fpu *f,
216 const sim_fpu *l, const sim_fpu *r);
217 INLINE_SIM_FPU (int) sim_fpu_div (sim_fpu *f,
218 const sim_fpu *l, const sim_fpu *r);
219 INLINE_SIM_FPU (int) sim_fpu_neg (sim_fpu *f,
221 INLINE_SIM_FPU (int) sim_fpu_abs (sim_fpu *f,
223 INLINE_SIM_FPU (int) sim_fpu_inv (sim_fpu *f,
225 INLINE_SIM_FPU (int) sim_fpu_sqrt (sim_fpu *f,
230 /* Conversion of integer <-> floating point. */
232 INLINE_SIM_FPU (int) sim_fpu_i32to (sim_fpu *f, signed32 i,
233 sim_fpu_round round);
234 INLINE_SIM_FPU (int) sim_fpu_u32to (sim_fpu *f, unsigned32 u,
235 sim_fpu_round round);
236 INLINE_SIM_FPU (int) sim_fpu_i64to (sim_fpu *f, signed64 i,
237 sim_fpu_round round);
238 INLINE_SIM_FPU (int) sim_fpu_u64to (sim_fpu *f, unsigned64 u,
239 sim_fpu_round round);
240 INLINE_SIM_FPU (int) sim_fpu_i232to (sim_fpu *f, signed32 h, signed32 l,
241 sim_fpu_round round);
242 INLINE_SIM_FPU (int) sim_fpu_u232to (sim_fpu *f, unsigned32 h, unsigned32 l,
243 sim_fpu_round round);
245 INLINE_SIM_FPU (int) sim_fpu_to32i (signed32 *i, const sim_fpu *f,
246 sim_fpu_round round);
247 INLINE_SIM_FPU (int) sim_fpu_to32u (unsigned32 *u, const sim_fpu *f,
248 sim_fpu_round round);
249 INLINE_SIM_FPU (int) sim_fpu_to64i (signed64 *i, const sim_fpu *f,
250 sim_fpu_round round);
251 INLINE_SIM_FPU (int) sim_fpu_to64u (unsigned64 *u, const sim_fpu *f,
252 sim_fpu_round round);
253 INLINE_SIM_FPU (int) sim_fpu_to232i (signed64 *h, signed64 *l, const sim_fpu *f,
254 sim_fpu_round round);
255 INLINE_SIM_FPU (int) sim_fpu_to232u (unsigned64 *h, unsigned64 *l, const sim_fpu *f,
256 sim_fpu_round round);
260 /* Conversion of internal sim_fpu type to host double format.
262 For debuging/tracing only. A SNaN is never returned. */
264 /* INLINE_SIM_FPU (float) sim_fpu_2f (const sim_fpu *f); */
265 INLINE_SIM_FPU (double) sim_fpu_2d (const sim_fpu *d);
267 /* INLINE_SIM_FPU (void) sim_fpu_f2 (sim_fpu *f, float s); */
268 INLINE_SIM_FPU (void) sim_fpu_d2 (sim_fpu *f, double d);
272 /* Specific number classes.
274 NB: When either a 32/64 bit floating points is converted to
275 internal format, or an internal format number is rounded to 32/64
276 bit precision, a special marker is retained that indicates that the
277 value was normalized. For such numbers both is_number and
278 is_denorm will return true. */
280 INLINE_SIM_FPU (int) sim_fpu_is_nan (const sim_fpu *s); /* 1 => SNaN or QNaN */
281 INLINE_SIM_FPU (int) sim_fpu_is_snan (const sim_fpu *s); /* 1 => SNaN */
282 INLINE_SIM_FPU (int) sim_fpu_is_qnan (const sim_fpu *s); /* 1 => QNaN */
284 INLINE_SIM_FPU (int) sim_fpu_is_zero (const sim_fpu *s);
285 INLINE_SIM_FPU (int) sim_fpu_is_infinity (const sim_fpu *s);
286 INLINE_SIM_FPU (int) sim_fpu_is_number (const sim_fpu *s); /* !zero */
287 INLINE_SIM_FPU (int) sim_fpu_is_denorm (const sim_fpu *s); /* !zero */
290 /* Specific comparison operators
292 The comparison operators set *IS to zero and return a nonzero
293 result for NaNs et.al. */
295 INLINE_SIM_FPU (int) sim_fpu_lt (int *is, const sim_fpu *l, const sim_fpu *r);
296 INLINE_SIM_FPU (int) sim_fpu_le (int *is, const sim_fpu *l, const sim_fpu *r);
297 INLINE_SIM_FPU (int) sim_fpu_eq (int *is, const sim_fpu *l, const sim_fpu *r);
298 INLINE_SIM_FPU (int) sim_fpu_ne (int *is, const sim_fpu *l, const sim_fpu *r);
299 INLINE_SIM_FPU (int) sim_fpu_ge (int *is, const sim_fpu *l, const sim_fpu *r);
300 INLINE_SIM_FPU (int) sim_fpu_gt (int *is, const sim_fpu *l, const sim_fpu *r);
302 INLINE_SIM_FPU (int) sim_fpu_is_lt (const sim_fpu *l, const sim_fpu *r);
303 INLINE_SIM_FPU (int) sim_fpu_is_le (const sim_fpu *l, const sim_fpu *r);
304 INLINE_SIM_FPU (int) sim_fpu_is_eq (const sim_fpu *l, const sim_fpu *r);
305 INLINE_SIM_FPU (int) sim_fpu_is_ne (const sim_fpu *l, const sim_fpu *r);
306 INLINE_SIM_FPU (int) sim_fpu_is_ge (const sim_fpu *l, const sim_fpu *r);
307 INLINE_SIM_FPU (int) sim_fpu_is_gt (const sim_fpu *l, const sim_fpu *r);
311 /* General number class and comparison operators.
313 The result of the comparison is indicated by returning one of the
314 values below. Efficient emulation of a target FP compare
315 instruction can be achieved by redefining the values below to match
316 corresponding target FP status bits.
318 For instance. SIM_FPU_QNAN may be redefined to be the bit
319 `INVALID' while SIM_FPU_NINF might be redefined as the bits
320 `NEGATIVE | INFINITY | VALID'. */
322 #ifndef SIM_FPU_IS_SNAN
324 SIM_FPU_IS_SNAN = 1, /* Noisy not-a-number */
325 SIM_FPU_IS_QNAN = 2, /* Quite not-a-number */
326 SIM_FPU_IS_NINF = 3, /* -infinity */
327 SIM_FPU_IS_PINF = 4, /* +infinity */
328 SIM_FPU_IS_NNUMBER = 5, /* -number - [ -MAX .. -MIN ] */
329 SIM_FPU_IS_PNUMBER = 6, /* +number - [ +MIN .. +MAX ] */
330 SIM_FPU_IS_NDENORM = 7, /* -denorm - ( MIN .. 0 ) */
331 SIM_FPU_IS_PDENORM = 8, /* +denorm - ( 0 .. MIN ) */
332 SIM_FPU_IS_NZERO = 9, /* -0 */
333 SIM_FPU_IS_PZERO = 10, /* +0 */
337 INLINE_SIM_FPU (int) sim_fpu_is (const sim_fpu *l);
338 INLINE_SIM_FPU (int) sim_fpu_cmp (const sim_fpu *l, const sim_fpu *r);
342 /* A constant of useful numbers */
344 extern const sim_fpu sim_fpu_zero;
345 extern const sim_fpu sim_fpu_one;
346 extern const sim_fpu sim_fpu_two;
347 extern const sim_fpu sim_fpu_qnan;
352 typedef void sim_fpu_print_func (void *, char *, ...);
354 INLINE_SIM_FPU (void) sim_fpu_print_fpu (const sim_fpu *f,
355 sim_fpu_print_func *print,
358 INLINE_SIM_FPU (void) sim_fpu_print_status (int status,
359 sim_fpu_print_func *print,