1 /* This file is part of the program psim.
3 Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #include "sim-assert.h"
29 /* "core" module install handler.
31 This is called via sim_module_install to install the "core" subsystem
32 into the simulator. */
34 static MODULE_INIT_FN sim_core_init;
35 static MODULE_UNINSTALL_FN sim_core_uninstall;
39 sim_core_install (SIM_DESC sd)
41 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
42 sim_module_add_uninstall_fn (sd, sim_core_uninstall);
43 sim_module_add_init_fn (sd, sim_core_init);
48 /* Uninstall the "core" subsystem from the simulator. */
52 sim_core_uninstall (SIM_DESC sd)
54 /* FIXME: free buffers, etc. */
60 sim_core_init (SIM_DESC sd)
62 sim_core *core = STATE_CORE(sd);
64 for (map = 0; map < nr_sim_core_maps; map++) {
65 /* blow away old mappings */
66 sim_core_mapping *curr = core->common.map[map].first;
67 while (curr != NULL) {
68 sim_core_mapping *tbd = curr;
70 if (tbd->free_buffer) {
71 SIM_ASSERT(tbd->buffer != NULL);
76 core->common.map[map].first = NULL;
79 /* Just copy this map to each of the processor specific data structures.
80 FIXME - later this will be replaced by true processor specific
84 for (i = 0; i < MAX_NR_PROCESSORS; i++)
87 CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
88 for (j = 0; j < WITH_XOR_ENDIAN; j++)
89 CPU_CORE (STATE_CPU (sd, i))->xor [j] = 0;
97 #ifndef SIM_CORE_SIGNAL
98 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
99 sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
103 sim_core_signal (SIM_DESC sd,
109 transfer_type transfer,
110 sim_core_signals sig)
112 const char *copy = (transfer == read_transfer ? "read" : "write");
115 case sim_core_unmapped_signal:
116 sim_engine_abort (sd, cpu, cia, "sim-core: %d byte %s to unmaped address 0x%lx",
117 nr_bytes, copy, (unsigned long) addr);
119 case sim_core_unaligned_signal:
120 sim_engine_abort (sd, cpu, cia, "sim-core: %d byte misaligned %s to address 0x%lx",
121 nr_bytes, copy, (unsigned long) addr);
124 sim_engine_abort (sd, cpu, cia, "sim_core_signal - internal error - bad switch");
130 STATIC_INLINE_SIM_CORE\
132 sim_core_map_to_str (sim_core_maps map)
136 case sim_core_read_map: return "read";
137 case sim_core_write_map: return "write";
138 case sim_core_execute_map: return "exec";
139 default: return "(invalid-map)";
146 new_sim_core_mapping(SIM_DESC sd,
155 sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping);
157 new_mapping->level = attach;
158 new_mapping->space = space;
159 new_mapping->base = addr;
160 new_mapping->nr_bytes = nr_bytes;
161 new_mapping->bound = addr + (nr_bytes - 1);
162 if (attach == attach_raw_memory) {
163 new_mapping->buffer = buffer;
164 new_mapping->free_buffer = free_buffer;
166 else if (attach >= attach_callback) {
167 new_mapping->device = device;
170 sim_io_error (sd, "new_sim_core_mapping - internal error - unknown attach type %d\n",
179 sim_core_map_attach(SIM_DESC sd,
180 sim_core_map *access_map,
184 unsigned nr_bytes, /* host limited */
185 device *client, /*callback/default*/
186 void *buffer, /*raw_memory*/
187 int free_buffer) /*raw_memory*/
189 /* find the insertion point for this additional mapping and then
191 sim_core_mapping *next_mapping;
192 sim_core_mapping **last_mapping;
194 SIM_ASSERT((attach >= attach_callback && client != NULL && buffer == NULL && !free_buffer)
195 || (attach == attach_raw_memory && client == NULL && buffer != NULL));
197 /* actually do occasionally get a zero size map */
200 device_error(client, "called on sim_core_map_attach with size zero");
202 sim_io_error (sd, "called on sim_core_map_attach with size zero");
206 /* find the insertion point (between last/next) */
207 next_mapping = access_map->first;
208 last_mapping = &access_map->first;
209 while(next_mapping != NULL
210 && (next_mapping->level < (int) attach
211 || (next_mapping->level == (int) attach
212 && next_mapping->bound < addr))) {
213 /* provided levels are the same */
214 /* assert: next_mapping->base > all bases before next_mapping */
215 /* assert: next_mapping->bound >= all bounds before next_mapping */
216 last_mapping = &next_mapping->next;
217 next_mapping = next_mapping->next;
220 /* check insertion point correct */
221 SIM_ASSERT (next_mapping == NULL || next_mapping->level >= (int) attach);
222 if (next_mapping != NULL && next_mapping->level == (int) attach
223 && next_mapping->base < (addr + (nr_bytes - 1))) {
225 device_error(client, "map overlap when attaching %d:0x%lx (%ld)",
226 space, (long)addr, (long)nr_bytes);
228 sim_io_error (sd, "map overlap when attaching %d:0x%lx (%ld)",
229 space, (long)addr, (long)nr_bytes);
233 /* create/insert the new mapping */
234 *last_mapping = new_sim_core_mapping(sd,
236 space, addr, nr_bytes,
237 client, buffer, free_buffer);
238 (*last_mapping)->next = next_mapping;
244 sim_core_attach(SIM_DESC sd,
250 unsigned nr_bytes, /* host limited */
252 void *optional_buffer)
254 sim_core *memory = STATE_CORE(sd);
259 /* check for for attempt to use unimplemented per-processor core map */
261 sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported");
263 if ((access & access_read_write_exec) == 0
264 || (access & ~access_read_write_exec) != 0) {
266 device_error(client, "invalid access for core attach");
268 sim_io_error (sd, "invalid access for core attach");
271 /* verify the attach type */
272 if (attach == attach_raw_memory) {
273 if (optional_buffer == NULL) {
274 buffer = zalloc(nr_bytes);
278 buffer = optional_buffer;
282 else if (attach >= attach_callback) {
288 device_error(client, "sim_core_attach - conflicting buffer and attach arguments");
290 sim_io_error (sd, "sim_core_attach - conflicting buffer and attach arguments");
295 /* attach the region to all applicable access maps */
297 map < nr_sim_core_maps;
300 case sim_core_read_map:
301 if (access & access_read)
302 sim_core_map_attach(sd, &memory->common.map[map],
304 space, addr, nr_bytes,
305 client, buffer, !buffer_freed);
308 case sim_core_write_map:
309 if (access & access_write)
310 sim_core_map_attach(sd, &memory->common.map[map],
312 space, addr, nr_bytes,
313 client, buffer, !buffer_freed);
316 case sim_core_execute_map:
317 if (access & access_exec)
318 sim_core_map_attach(sd, &memory->common.map[map],
320 space, addr, nr_bytes,
321 client, buffer, !buffer_freed);
324 case nr_sim_core_maps:
325 sim_io_error (sd, "sim_core_attach - internal error - bad switch");
330 /* Just copy this map to each of the processor specific data structures.
331 FIXME - later this will be replaced by true processor specific
335 for (i = 0; i < MAX_NR_PROCESSORS; i++)
337 CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
343 STATIC_INLINE_SIM_CORE\
345 sim_core_find_mapping(sim_core_common *core,
349 transfer_type transfer,
350 int abort, /*either 0 or 1 - hint to inline/-O */
351 sim_cpu *cpu, /* abort => cpu != NULL */
354 sim_core_mapping *mapping = core->map[map].first;
355 ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
356 ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
357 ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
358 while (mapping != NULL)
360 if (addr >= mapping->base
361 && (addr + (nr_bytes - 1)) <= mapping->bound)
363 mapping = mapping->next;
367 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer,
368 sim_core_unmapped_signal);
374 STATIC_INLINE_SIM_CORE\
376 sim_core_translate (sim_core_mapping *mapping,
379 return (void *)(((char *)mapping->buffer) + addr - mapping->base);
385 sim_core_read_buffer (SIM_DESC sd,
392 sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
394 while (count < len) {
395 unsigned_word raddr = addr + count;
396 sim_core_mapping *mapping =
397 sim_core_find_mapping(core, map,
398 raddr, /*nr-bytes*/1,
400 0 /*dont-abort*/, NULL, NULL_CIA);
404 if (mapping->device != NULL) {
405 int nr_bytes = len - count;
406 if (raddr + nr_bytes - 1> mapping->bound)
407 nr_bytes = mapping->bound - raddr + 1;
408 if (device_io_read_buffer(mapping->device,
409 (unsigned_1*)buffer + count,
412 nr_bytes) != nr_bytes)
419 ((unsigned_1*)buffer)[count] =
420 *(unsigned_1*)sim_core_translate(mapping, raddr);
430 sim_core_write_buffer (SIM_DESC sd,
437 sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
439 while (count < len) {
440 unsigned_word raddr = addr + count;
441 sim_core_mapping *mapping =
442 sim_core_find_mapping(core, map,
443 raddr, /*nr-bytes*/1,
445 0 /*dont-abort*/, NULL, NULL_CIA);
449 if (WITH_CALLBACK_MEMORY
450 && mapping->device != NULL) {
451 int nr_bytes = len - count;
452 if (raddr + nr_bytes - 1 > mapping->bound)
453 nr_bytes = mapping->bound - raddr + 1;
454 if (device_io_write_buffer(mapping->device,
455 (unsigned_1*)buffer + count,
458 nr_bytes) != nr_bytes)
465 *(unsigned_1*)sim_core_translate(mapping, raddr) =
466 ((unsigned_1*)buffer)[count];
476 sim_core_set_xor (SIM_DESC sd,
480 /* set up the XOR map if required. */
481 if (WITH_XOR_ENDIAN) {
483 sim_core *core = STATE_CORE (sd);
484 sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
485 if (cpu_core != NULL)
490 mask = WITH_XOR_ENDIAN - 1;
493 while (i - 1 < WITH_XOR_ENDIAN)
495 cpu_core->xor[i-1] = mask;
496 mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
503 core->byte_xor = WITH_XOR_ENDIAN - 1;
511 sim_engine_abort (sd, cpu, NULL_CIA,
512 "Attempted to enable xor-endian mode when permenantly disabled.");
516 STATIC_INLINE_SIM_CORE\
518 reverse_n (unsigned_1 *dest,
519 const unsigned_1 *src,
523 for (i = 0; i < nr_bytes; i++)
525 dest [nr_bytes - i - 1] = src [i];
532 sim_core_xor_read_buffer (SIM_DESC sd,
539 address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
540 if (!WITH_XOR_ENDIAN || !byte_xor)
541 return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
543 /* only break up transfers when xor-endian is both selected and enabled */
545 unsigned_1 x[WITH_XOR_ENDIAN];
546 unsigned nr_transfered = 0;
547 address_word start = addr;
548 unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
550 /* initial and intermediate transfers are broken when they cross
551 an XOR endian boundary */
552 while (nr_transfered + nr_this_transfer < nr_bytes)
553 /* initial/intermediate transfers */
555 /* since xor-endian is enabled stop^xor defines the start
556 address of the transfer */
557 stop = start + nr_this_transfer - 1;
558 SIM_ASSERT (start <= stop);
559 SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
560 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
562 return nr_transfered;
563 reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
564 nr_transfered += nr_this_transfer;
565 nr_this_transfer = WITH_XOR_ENDIAN;
569 nr_this_transfer = nr_bytes - nr_transfered;
570 stop = start + nr_this_transfer - 1;
571 SIM_ASSERT (stop == (addr + nr_bytes - 1));
572 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
574 return nr_transfered;
575 reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
583 sim_core_xor_write_buffer (SIM_DESC sd,
590 address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
591 if (!WITH_XOR_ENDIAN || !byte_xor)
592 return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
594 /* only break up transfers when xor-endian is both selected and enabled */
596 unsigned_1 x[WITH_XOR_ENDIAN];
597 unsigned nr_transfered = 0;
598 address_word start = addr;
599 unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
601 /* initial and intermediate transfers are broken when they cross
602 an XOR endian boundary */
603 while (nr_transfered + nr_this_transfer < nr_bytes)
604 /* initial/intermediate transfers */
606 /* since xor-endian is enabled stop^xor defines the start
607 address of the transfer */
608 stop = start + nr_this_transfer - 1;
609 SIM_ASSERT (start <= stop);
610 SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
611 reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
612 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
614 return nr_transfered;
615 nr_transfered += nr_this_transfer;
616 nr_this_transfer = WITH_XOR_ENDIAN;
620 nr_this_transfer = nr_bytes - nr_transfered;
621 stop = start + nr_this_transfer - 1;
622 SIM_ASSERT (stop == (addr + nr_bytes - 1));
623 reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
624 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
626 return nr_transfered;
633 /* define the read/write 1/2/4/8/word functions */
636 #include "sim-n-core.h"
640 #include "sim-n-core.h"
644 #include "sim-n-core.h"
648 #include "sim-n-core.h"
652 #include "sim-n-core.h"