1 /* This file is part of the program psim.
3 Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #include "sim-assert.h"
28 /* "core" module install handler.
30 This is called via sim_module_install to install the "core" subsystem
31 into the simulator. */
33 static MODULE_INIT_FN sim_core_init;
34 static MODULE_UNINSTALL_FN sim_core_uninstall;
37 /* TODO: create sim/common/device.h */
38 void device_error (device *me, char* message, ...);
39 int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
40 int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
45 sim_core_install (SIM_DESC sd)
47 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
49 /* establish the other handlers */
50 sim_module_add_uninstall_fn (sd, sim_core_uninstall);
51 sim_module_add_init_fn (sd, sim_core_init);
53 /* establish any initial data structures - none */
58 /* Uninstall the "core" subsystem from the simulator. */
62 sim_core_uninstall (SIM_DESC sd)
64 sim_core *core = STATE_CORE(sd);
66 /* blow away any mappings */
67 for (map = 0; map < nr_sim_core_maps; map++) {
68 sim_core_mapping *curr = core->common.map[map].first;
69 while (curr != NULL) {
70 sim_core_mapping *tbd = curr;
72 if (tbd->free_buffer != NULL) {
73 SIM_ASSERT(tbd->buffer != NULL);
74 zfree(tbd->free_buffer);
78 core->common.map[map].first = NULL;
85 sim_core_init (SIM_DESC sd)
93 #ifndef SIM_CORE_SIGNAL
94 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
95 sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
99 sim_core_signal (SIM_DESC sd,
105 transfer_type transfer,
106 sim_core_signals sig)
108 const char *copy = (transfer == read_transfer ? "read" : "write");
109 address_word ip = CIA_ADDR (cia);
112 case sim_core_unmapped_signal:
113 sim_io_eprintf (sd, "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
114 nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
115 sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGSEGV);
117 case sim_core_unaligned_signal:
118 sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
119 nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
120 sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGBUS);
123 sim_engine_abort (sd, cpu, cia,
124 "sim_core_signal - internal error - bad switch");
130 STATIC_INLINE_SIM_CORE\
132 sim_core_map_to_str (sim_core_maps map)
136 case sim_core_read_map: return "read";
137 case sim_core_write_map: return "write";
138 case sim_core_execute_map: return "exec";
139 default: return "(invalid-map)";
146 new_sim_core_mapping (SIM_DESC sd,
150 address_word nr_bytes,
156 sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping);
158 new_mapping->level = level;
159 new_mapping->space = space;
160 new_mapping->base = addr;
161 new_mapping->nr_bytes = nr_bytes;
162 new_mapping->bound = addr + (nr_bytes - 1);
164 new_mapping->mask = (unsigned) 0 - 1;
166 new_mapping->mask = modulo - 1;
167 new_mapping->buffer = buffer;
168 new_mapping->free_buffer = free_buffer;
169 new_mapping->device = device;
176 sim_core_map_attach (SIM_DESC sd,
177 sim_core_map *access_map,
181 address_word nr_bytes,
183 device *client, /*callback/default*/
184 void *buffer, /*raw_memory*/
185 void *free_buffer) /*raw_memory*/
187 /* find the insertion point for this additional mapping and then
189 sim_core_mapping *next_mapping;
190 sim_core_mapping **last_mapping;
192 SIM_ASSERT ((client == NULL) != (buffer == NULL));
193 SIM_ASSERT ((client == NULL) >= (free_buffer != NULL));
195 /* actually do occasionally get a zero size map */
199 device_error(client, "called on sim_core_map_attach with size zero");
201 sim_io_error (sd, "called on sim_core_map_attach with size zero");
205 /* find the insertion point (between last/next) */
206 next_mapping = access_map->first;
207 last_mapping = &access_map->first;
208 while(next_mapping != NULL
209 && (next_mapping->level < level
210 || (next_mapping->level == level
211 && next_mapping->bound < addr)))
213 /* provided levels are the same */
214 /* assert: next_mapping->base > all bases before next_mapping */
215 /* assert: next_mapping->bound >= all bounds before next_mapping */
216 last_mapping = &next_mapping->next;
217 next_mapping = next_mapping->next;
220 /* check insertion point correct */
221 SIM_ASSERT (next_mapping == NULL || next_mapping->level >= level);
222 if (next_mapping != NULL && next_mapping->level == level
223 && next_mapping->base < (addr + (nr_bytes - 1)))
226 device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
230 (long) (addr + (nr_bytes - 1)),
232 (long) next_mapping->base,
233 (long) next_mapping->bound,
234 (long) next_mapping->nr_bytes);
236 sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
240 (long) (addr + (nr_bytes - 1)),
242 (long) next_mapping->base,
243 (long) next_mapping->bound,
244 (long) next_mapping->nr_bytes);
248 /* create/insert the new mapping */
249 *last_mapping = new_sim_core_mapping(sd,
251 space, addr, nr_bytes, modulo,
252 client, buffer, free_buffer);
253 (*last_mapping)->next = next_mapping;
259 sim_core_attach (SIM_DESC sd,
265 address_word nr_bytes,
268 void *optional_buffer)
270 sim_core *memory = STATE_CORE(sd);
275 /* check for for attempt to use unimplemented per-processor core map */
277 sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported");
279 if ((access & access_read_write_exec) == 0
280 || (access & ~access_read_write_exec) != 0)
283 device_error(client, "invalid access for core attach");
285 sim_io_error (sd, "invalid access for core attach");
289 /* verify modulo memory */
290 if (!WITH_MODULO_MEMORY && modulo != 0)
293 device_error (client, "sim_core_attach - internal error - modulo memory disabled");
295 sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled");
298 if (client != NULL && modulo != 0)
301 device_error (client, "sim_core_attach - internal error - modulo and callback memory conflict");
303 sim_io_error (sd, "sim_core_attach - internal error - modulo and callback memory conflict");
308 unsigned mask = modulo - 1;
310 while (mask >= sizeof (unsigned64)) /* minimum modulo */
317 if (mask != sizeof (unsigned64) - 1)
320 device_error (client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
322 sim_io_error (sd, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
327 /* verify consistency between device and buffer */
328 if (client != NULL && optional_buffer != NULL)
331 device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments");
333 sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments");
338 if (optional_buffer == NULL)
340 int padding = (addr % sizeof (unsigned64));
341 free_buffer = zalloc ((modulo == 0 ? nr_bytes : modulo) + padding);
342 buffer = (char*) free_buffer + padding;
346 buffer = optional_buffer;
357 /* attach the region to all applicable access maps */
359 map < nr_sim_core_maps;
364 case sim_core_read_map:
365 if (access & access_read)
366 sim_core_map_attach (sd, &memory->common.map[map],
367 level, space, addr, nr_bytes, modulo,
368 client, buffer, free_buffer);
371 case sim_core_write_map:
372 if (access & access_write)
373 sim_core_map_attach (sd, &memory->common.map[map],
374 level, space, addr, nr_bytes, modulo,
375 client, buffer, free_buffer);
378 case sim_core_execute_map:
379 if (access & access_exec)
380 sim_core_map_attach (sd, &memory->common.map[map],
381 level, space, addr, nr_bytes, modulo,
382 client, buffer, free_buffer);
385 case nr_sim_core_maps:
386 sim_io_error (sd, "sim_core_attach - internal error - bad switch");
391 /* Just copy this map to each of the processor specific data structures.
392 FIXME - later this will be replaced by true processor specific
396 for (i = 0; i < MAX_NR_PROCESSORS; i++)
398 CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
404 /* Remove any memory reference related to this address */
405 STATIC_INLINE_SIM_CORE\
407 sim_core_map_detach (SIM_DESC sd,
408 sim_core_map *access_map,
413 sim_core_mapping **entry;
414 for (entry = &access_map->first;
416 entry = &(*entry)->next)
418 if ((*entry)->base == addr
419 && (*entry)->level == level
420 && (*entry)->space == space)
422 sim_core_mapping *dead = (*entry);
423 (*entry) = dead->next;
424 if (dead->free_buffer != NULL)
425 zfree (dead->free_buffer);
434 sim_core_detach (SIM_DESC sd,
440 sim_core *memory = STATE_CORE (sd);
442 for (map = 0; map < nr_sim_core_maps; map++)
444 sim_core_map_detach (sd, &memory->common.map[map],
445 level, address_space, addr);
447 /* Just copy this update to each of the processor specific data
448 structures. FIXME - later this will be replaced by true
449 processor specific maps. */
452 for (i = 0; i < MAX_NR_PROCESSORS; i++)
454 CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
460 STATIC_INLINE_SIM_CORE\
462 sim_core_find_mapping(sim_core_common *core,
466 transfer_type transfer,
467 int abort, /*either 0 or 1 - hint to inline/-O */
468 sim_cpu *cpu, /* abort => cpu != NULL */
471 sim_core_mapping *mapping = core->map[map].first;
472 ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
473 ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
474 ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
475 while (mapping != NULL)
477 if (addr >= mapping->base
478 && (addr + (nr_bytes - 1)) <= mapping->bound)
480 mapping = mapping->next;
484 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer,
485 sim_core_unmapped_signal);
491 STATIC_INLINE_SIM_CORE\
493 sim_core_translate (sim_core_mapping *mapping,
496 if (WITH_MODULO_MEMORY)
497 return (void *)((unsigned8 *) mapping->buffer
498 + ((addr - mapping->base) & mapping->mask));
500 return (void *)((unsigned8 *) mapping->buffer
501 + addr - mapping->base);
507 sim_core_read_buffer (SIM_DESC sd,
514 sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
516 while (count < len) {
517 unsigned_word raddr = addr + count;
518 sim_core_mapping *mapping =
519 sim_core_find_mapping(core, map,
520 raddr, /*nr-bytes*/1,
522 0 /*dont-abort*/, NULL, NULL_CIA);
526 if (mapping->device != NULL) {
527 int nr_bytes = len - count;
528 if (raddr + nr_bytes - 1> mapping->bound)
529 nr_bytes = mapping->bound - raddr + 1;
530 if (device_io_read_buffer(mapping->device,
531 (unsigned_1*)buffer + count,
536 CIA_GET(cpu)) != nr_bytes)
543 ((unsigned_1*)buffer)[count] =
544 *(unsigned_1*)sim_core_translate(mapping, raddr);
554 sim_core_write_buffer (SIM_DESC sd,
561 sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
563 while (count < len) {
564 unsigned_word raddr = addr + count;
565 sim_core_mapping *mapping =
566 sim_core_find_mapping(core, map,
567 raddr, /*nr-bytes*/1,
569 0 /*dont-abort*/, NULL, NULL_CIA);
573 if (WITH_CALLBACK_MEMORY
574 && mapping->device != NULL) {
575 int nr_bytes = len - count;
576 if (raddr + nr_bytes - 1 > mapping->bound)
577 nr_bytes = mapping->bound - raddr + 1;
578 if (device_io_write_buffer(mapping->device,
579 (unsigned_1*)buffer + count,
584 CIA_GET(cpu)) != nr_bytes)
591 *(unsigned_1*)sim_core_translate(mapping, raddr) =
592 ((unsigned_1*)buffer)[count];
602 sim_core_set_xor (SIM_DESC sd,
606 /* set up the XOR map if required. */
607 if (WITH_XOR_ENDIAN) {
609 sim_core *core = STATE_CORE (sd);
610 sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
611 if (cpu_core != NULL)
616 mask = WITH_XOR_ENDIAN - 1;
619 while (i - 1 < WITH_XOR_ENDIAN)
621 cpu_core->xor[i-1] = mask;
622 mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
629 core->byte_xor = WITH_XOR_ENDIAN - 1;
637 sim_engine_abort (sd, cpu, NULL_CIA,
638 "Attempted to enable xor-endian mode when permenantly disabled.");
642 STATIC_INLINE_SIM_CORE\
644 reverse_n (unsigned_1 *dest,
645 const unsigned_1 *src,
649 for (i = 0; i < nr_bytes; i++)
651 dest [nr_bytes - i - 1] = src [i];
658 sim_core_xor_read_buffer (SIM_DESC sd,
665 address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
666 if (!WITH_XOR_ENDIAN || !byte_xor)
667 return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
669 /* only break up transfers when xor-endian is both selected and enabled */
671 unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
672 unsigned nr_transfered = 0;
673 address_word start = addr;
674 unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
676 /* initial and intermediate transfers are broken when they cross
677 an XOR endian boundary */
678 while (nr_transfered + nr_this_transfer < nr_bytes)
679 /* initial/intermediate transfers */
681 /* since xor-endian is enabled stop^xor defines the start
682 address of the transfer */
683 stop = start + nr_this_transfer - 1;
684 SIM_ASSERT (start <= stop);
685 SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
686 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
688 return nr_transfered;
689 reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
690 nr_transfered += nr_this_transfer;
691 nr_this_transfer = WITH_XOR_ENDIAN;
695 nr_this_transfer = nr_bytes - nr_transfered;
696 stop = start + nr_this_transfer - 1;
697 SIM_ASSERT (stop == (addr + nr_bytes - 1));
698 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
700 return nr_transfered;
701 reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
709 sim_core_xor_write_buffer (SIM_DESC sd,
716 address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
717 if (!WITH_XOR_ENDIAN || !byte_xor)
718 return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
720 /* only break up transfers when xor-endian is both selected and enabled */
722 unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */
723 unsigned nr_transfered = 0;
724 address_word start = addr;
725 unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
727 /* initial and intermediate transfers are broken when they cross
728 an XOR endian boundary */
729 while (nr_transfered + nr_this_transfer < nr_bytes)
730 /* initial/intermediate transfers */
732 /* since xor-endian is enabled stop^xor defines the start
733 address of the transfer */
734 stop = start + nr_this_transfer - 1;
735 SIM_ASSERT (start <= stop);
736 SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
737 reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
738 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
740 return nr_transfered;
741 nr_transfered += nr_this_transfer;
742 nr_this_transfer = WITH_XOR_ENDIAN;
746 nr_this_transfer = nr_bytes - nr_transfered;
747 stop = start + nr_this_transfer - 1;
748 SIM_ASSERT (stop == (addr + nr_bytes - 1));
749 reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
750 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
752 return nr_transfered;
759 /* define the read/write 1/2/4/8/16/word functions */
762 #include "sim-n-core.h"
765 #include "sim-n-core.h"
769 #include "sim-n-core.h"
773 #include "sim-n-core.h"
777 #include "sim-n-core.h"
780 #include "sim-n-core.h"
784 #include "sim-n-core.h"
787 #include "sim-n-core.h"
790 #include "sim-n-core.h"