1 /* This file is part of the program psim.
3 Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #include "libiberty.h"
27 #include "sim-assert.h"
29 /* "core" module install handler.
31 This is called via sim_module_install to install the "core" subsystem
32 into the simulator. */
34 static MODULE_INIT_FN sim_core_init;
35 static MODULE_UNINSTALL_FN sim_core_uninstall;
38 /* TODO: create sim/common/device.h */
39 void device_error (device *me, char* message, ...);
40 int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
41 int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
46 sim_core_install (SIM_DESC sd)
48 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
50 /* establish the other handlers */
51 sim_module_add_uninstall_fn (sd, sim_core_uninstall);
52 sim_module_add_init_fn (sd, sim_core_init);
54 /* establish any initial data structures - none */
59 /* Uninstall the "core" subsystem from the simulator. */
63 sim_core_uninstall (SIM_DESC sd)
65 sim_core *core = STATE_CORE(sd);
67 /* blow away any mappings */
68 for (map = 0; map < nr_sim_core_maps; map++) {
69 sim_core_mapping *curr = core->common.map[map].first;
70 while (curr != NULL) {
71 sim_core_mapping *tbd = curr;
73 if (tbd->free_buffer != NULL) {
74 SIM_ASSERT(tbd->buffer != NULL);
75 zfree(tbd->free_buffer);
79 core->common.map[map].first = NULL;
86 sim_core_init (SIM_DESC sd)
94 #ifndef SIM_CORE_SIGNAL
95 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
96 sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
100 sim_core_signal (SIM_DESC sd,
106 transfer_type transfer,
107 sim_core_signals sig)
109 const char *copy = (transfer == read_transfer ? "read" : "write");
110 address_word ip = CIA_ADDR (cia);
113 case sim_core_unmapped_signal:
114 sim_io_eprintf (sd, "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
115 nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
116 sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGSEGV);
118 case sim_core_unaligned_signal:
119 sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
120 nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
121 sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGBUS);
124 sim_engine_abort (sd, cpu, cia,
125 "sim_core_signal - internal error - bad switch");
133 sim_core_map_to_str (sim_core_maps map)
137 case sim_core_read_map: return "read";
138 case sim_core_write_map: return "write";
139 case sim_core_execute_map: return "exec";
140 default: return "(invalid-map)";
147 new_sim_core_mapping (SIM_DESC sd,
151 address_word nr_bytes,
157 sim_core_mapping *new_mapping = ZALLOC(sim_core_mapping);
159 new_mapping->level = level;
160 new_mapping->space = space;
161 new_mapping->base = addr;
162 new_mapping->nr_bytes = nr_bytes;
163 new_mapping->bound = addr + (nr_bytes - 1);
165 new_mapping->mask = (unsigned) 0 - 1;
167 new_mapping->mask = modulo - 1;
168 new_mapping->buffer = buffer;
169 new_mapping->free_buffer = free_buffer;
170 new_mapping->device = device;
177 sim_core_map_attach (SIM_DESC sd,
178 sim_core_map *access_map,
182 address_word nr_bytes,
184 device *client, /*callback/default*/
185 void *buffer, /*raw_memory*/
186 void *free_buffer) /*raw_memory*/
188 /* find the insertion point for this additional mapping and then
190 sim_core_mapping *next_mapping;
191 sim_core_mapping **last_mapping;
193 SIM_ASSERT ((client == NULL) != (buffer == NULL));
194 SIM_ASSERT ((client == NULL) >= (free_buffer != NULL));
196 /* actually do occasionally get a zero size map */
200 device_error(client, "called on sim_core_map_attach with size zero");
202 sim_io_error (sd, "called on sim_core_map_attach with size zero");
206 /* find the insertion point (between last/next) */
207 next_mapping = access_map->first;
208 last_mapping = &access_map->first;
209 while(next_mapping != NULL
210 && (next_mapping->level < level
211 || (next_mapping->level == level
212 && next_mapping->bound < addr)))
214 /* provided levels are the same */
215 /* assert: next_mapping->base > all bases before next_mapping */
216 /* assert: next_mapping->bound >= all bounds before next_mapping */
217 last_mapping = &next_mapping->next;
218 next_mapping = next_mapping->next;
221 /* check insertion point correct */
222 SIM_ASSERT (next_mapping == NULL || next_mapping->level >= level);
223 if (next_mapping != NULL && next_mapping->level == level
224 && next_mapping->base < (addr + (nr_bytes - 1)))
227 device_error (client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
231 (long) (addr + (nr_bytes - 1)),
233 (long) next_mapping->base,
234 (long) next_mapping->bound,
235 (long) next_mapping->nr_bytes);
237 sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
241 (long) (addr + (nr_bytes - 1)),
243 (long) next_mapping->base,
244 (long) next_mapping->bound,
245 (long) next_mapping->nr_bytes);
249 /* create/insert the new mapping */
250 *last_mapping = new_sim_core_mapping(sd,
252 space, addr, nr_bytes, modulo,
253 client, buffer, free_buffer);
254 (*last_mapping)->next = next_mapping;
257 /* Attach memory or a memory mapped device to the simulator.
258 See sim-core.h for a full description. */
262 sim_core_attach (SIM_DESC sd,
268 address_word nr_bytes,
271 void *optional_buffer)
273 sim_core *memory = STATE_CORE(sd);
278 /* check for for attempt to use unimplemented per-processor core map */
280 sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported");
282 if ((access & access_read_write_exec) == 0
283 || (access & ~access_read_write_exec) != 0)
286 device_error(client, "invalid access for core attach");
288 sim_io_error (sd, "invalid access for core attach");
292 /* verify modulo memory */
293 if (!WITH_MODULO_MEMORY && modulo != 0)
296 device_error (client, "sim_core_attach - internal error - modulo memory disabled");
298 sim_io_error (sd, "sim_core_attach - internal error - modulo memory disabled");
301 if (client != NULL && modulo != 0)
304 device_error (client, "sim_core_attach - internal error - modulo and callback memory conflict");
306 sim_io_error (sd, "sim_core_attach - internal error - modulo and callback memory conflict");
311 unsigned mask = modulo - 1;
313 while (mask >= sizeof (unsigned64)) /* minimum modulo */
320 if (mask != sizeof (unsigned64) - 1)
323 device_error (client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
325 sim_io_error (sd, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
330 /* verify consistency between device and buffer */
331 if (client != NULL && optional_buffer != NULL)
334 device_error (client, "sim_core_attach - internal error - conflicting buffer and attach arguments");
336 sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments");
341 if (optional_buffer == NULL)
343 int padding = (addr % sizeof (unsigned64));
344 unsigned int bytes = (modulo == 0 ? nr_bytes : modulo) + padding;
345 free_buffer = xmalloc (bytes);
346 /* #if WITH_DETERMINISTIC_SIMULATION? */
347 memset (free_buffer, 0xa5, bytes);
348 buffer = (char*) free_buffer + padding;
352 buffer = optional_buffer;
363 /* attach the region to all applicable access maps */
365 map < nr_sim_core_maps;
370 case sim_core_read_map:
371 if (access & access_read)
372 sim_core_map_attach (sd, &memory->common.map[map],
373 level, space, addr, nr_bytes, modulo,
374 client, buffer, free_buffer);
377 case sim_core_write_map:
378 if (access & access_write)
379 sim_core_map_attach (sd, &memory->common.map[map],
380 level, space, addr, nr_bytes, modulo,
381 client, buffer, free_buffer);
384 case sim_core_execute_map:
385 if (access & access_exec)
386 sim_core_map_attach (sd, &memory->common.map[map],
387 level, space, addr, nr_bytes, modulo,
388 client, buffer, free_buffer);
392 sim_io_error (sd, "sim_core_attach - internal error - bad switch");
397 /* Just copy this map to each of the processor specific data structures.
398 FIXME - later this will be replaced by true processor specific
402 for (i = 0; i < MAX_NR_PROCESSORS; i++)
404 CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
410 /* Remove any memory reference related to this address */
411 STATIC_INLINE_SIM_CORE\
413 sim_core_map_detach (SIM_DESC sd,
414 sim_core_map *access_map,
419 sim_core_mapping **entry;
420 for (entry = &access_map->first;
422 entry = &(*entry)->next)
424 if ((*entry)->base == addr
425 && (*entry)->level == level
426 && (*entry)->space == space)
428 sim_core_mapping *dead = (*entry);
429 (*entry) = dead->next;
430 if (dead->free_buffer != NULL)
431 free (dead->free_buffer);
440 sim_core_detach (SIM_DESC sd,
446 sim_core *memory = STATE_CORE (sd);
448 for (map = 0; map < nr_sim_core_maps; map++)
450 sim_core_map_detach (sd, &memory->common.map[map],
451 level, address_space, addr);
453 /* Just copy this update to each of the processor specific data
454 structures. FIXME - later this will be replaced by true
455 processor specific maps. */
458 for (i = 0; i < MAX_NR_PROCESSORS; i++)
460 CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
466 STATIC_INLINE_SIM_CORE\
468 sim_core_find_mapping(sim_core_common *core,
472 transfer_type transfer,
473 int abort, /*either 0 or 1 - hint to inline/-O */
474 sim_cpu *cpu, /* abort => cpu != NULL */
477 sim_core_mapping *mapping = core->map[map].first;
478 ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
479 ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
480 ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
481 while (mapping != NULL)
483 if (addr >= mapping->base
484 && (addr + (nr_bytes - 1)) <= mapping->bound)
486 mapping = mapping->next;
490 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer,
491 sim_core_unmapped_signal);
497 STATIC_INLINE_SIM_CORE\
499 sim_core_translate (sim_core_mapping *mapping,
502 if (WITH_MODULO_MEMORY)
503 return (void *)((unsigned8 *) mapping->buffer
504 + ((addr - mapping->base) & mapping->mask));
506 return (void *)((unsigned8 *) mapping->buffer
507 + addr - mapping->base);
513 sim_core_read_buffer (SIM_DESC sd,
520 sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
522 while (count < len) {
523 unsigned_word raddr = addr + count;
524 sim_core_mapping *mapping =
525 sim_core_find_mapping(core, map,
526 raddr, /*nr-bytes*/1,
528 0 /*dont-abort*/, NULL, NULL_CIA);
532 if (mapping->device != NULL) {
533 int nr_bytes = len - count;
534 if (raddr + nr_bytes - 1> mapping->bound)
535 nr_bytes = mapping->bound - raddr + 1;
536 if (device_io_read_buffer(mapping->device,
537 (unsigned_1*)buffer + count,
542 CIA_GET(cpu)) != nr_bytes)
549 ((unsigned_1*)buffer)[count] =
550 *(unsigned_1*)sim_core_translate(mapping, raddr);
560 sim_core_write_buffer (SIM_DESC sd,
567 sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
569 while (count < len) {
570 unsigned_word raddr = addr + count;
571 sim_core_mapping *mapping =
572 sim_core_find_mapping(core, map,
573 raddr, /*nr-bytes*/1,
575 0 /*dont-abort*/, NULL, NULL_CIA);
579 if (WITH_CALLBACK_MEMORY
580 && mapping->device != NULL) {
581 int nr_bytes = len - count;
582 if (raddr + nr_bytes - 1 > mapping->bound)
583 nr_bytes = mapping->bound - raddr + 1;
584 if (device_io_write_buffer(mapping->device,
585 (unsigned_1*)buffer + count,
590 CIA_GET(cpu)) != nr_bytes)
597 *(unsigned_1*)sim_core_translate(mapping, raddr) =
598 ((unsigned_1*)buffer)[count];
608 sim_core_set_xor (SIM_DESC sd,
612 /* set up the XOR map if required. */
613 if (WITH_XOR_ENDIAN) {
615 sim_core *core = STATE_CORE (sd);
616 sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
617 if (cpu_core != NULL)
622 mask = WITH_XOR_ENDIAN - 1;
625 while (i - 1 < WITH_XOR_ENDIAN)
627 cpu_core->xor[i-1] = mask;
628 mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
635 core->byte_xor = WITH_XOR_ENDIAN - 1;
643 sim_engine_abort (sd, cpu, NULL_CIA,
644 "Attempted to enable xor-endian mode when permenantly disabled.");
648 STATIC_INLINE_SIM_CORE\
650 reverse_n (unsigned_1 *dest,
651 const unsigned_1 *src,
655 for (i = 0; i < nr_bytes; i++)
657 dest [nr_bytes - i - 1] = src [i];
664 sim_core_xor_read_buffer (SIM_DESC sd,
671 address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
672 if (!WITH_XOR_ENDIAN || !byte_xor)
673 return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
675 /* only break up transfers when xor-endian is both selected and enabled */
677 unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
678 unsigned nr_transfered = 0;
679 address_word start = addr;
680 unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
682 /* initial and intermediate transfers are broken when they cross
683 an XOR endian boundary */
684 while (nr_transfered + nr_this_transfer < nr_bytes)
685 /* initial/intermediate transfers */
687 /* since xor-endian is enabled stop^xor defines the start
688 address of the transfer */
689 stop = start + nr_this_transfer - 1;
690 SIM_ASSERT (start <= stop);
691 SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
692 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
694 return nr_transfered;
695 reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
696 nr_transfered += nr_this_transfer;
697 nr_this_transfer = WITH_XOR_ENDIAN;
701 nr_this_transfer = nr_bytes - nr_transfered;
702 stop = start + nr_this_transfer - 1;
703 SIM_ASSERT (stop == (addr + nr_bytes - 1));
704 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
706 return nr_transfered;
707 reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
715 sim_core_xor_write_buffer (SIM_DESC sd,
722 address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
723 if (!WITH_XOR_ENDIAN || !byte_xor)
724 return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
726 /* only break up transfers when xor-endian is both selected and enabled */
728 unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */
729 unsigned nr_transfered = 0;
730 address_word start = addr;
731 unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
733 /* initial and intermediate transfers are broken when they cross
734 an XOR endian boundary */
735 while (nr_transfered + nr_this_transfer < nr_bytes)
736 /* initial/intermediate transfers */
738 /* since xor-endian is enabled stop^xor defines the start
739 address of the transfer */
740 stop = start + nr_this_transfer - 1;
741 SIM_ASSERT (start <= stop);
742 SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
743 reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
744 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
746 return nr_transfered;
747 nr_transfered += nr_this_transfer;
748 nr_this_transfer = WITH_XOR_ENDIAN;
752 nr_this_transfer = nr_bytes - nr_transfered;
753 stop = start + nr_this_transfer - 1;
754 SIM_ASSERT (stop == (addr + nr_bytes - 1));
755 reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
756 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
758 return nr_transfered;
765 /* define the read/write 1/2/4/8/16/word functions */
768 #include "sim-n-core.h"
771 #include "sim-n-core.h"
775 #include "sim-n-core.h"
779 #include "sim-n-core.h"
783 #include "sim-n-core.h"
786 #include "sim-n-core.h"
790 #include "sim-n-core.h"
793 #include "sim-n-core.h"
796 #include "sim-n-core.h"