1 /* The common simulator framework for GDB, the GNU Debugger.
3 Copyright 2002-2018 Free Software Foundation, Inc.
5 Contributed by Andrew Cagney and Red Hat.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
27 #include "sim-assert.h"
33 /* "core" module install handler.
35 This is called via sim_module_install to install the "core"
36 subsystem into the simulator. */
39 static MODULE_INIT_FN sim_core_init;
40 static MODULE_UNINSTALL_FN sim_core_uninstall;
45 sim_core_install (SIM_DESC sd)
47 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
49 /* establish the other handlers */
50 sim_module_add_uninstall_fn (sd, sim_core_uninstall);
51 sim_module_add_init_fn (sd, sim_core_init);
53 /* establish any initial data structures - none */
59 /* Uninstall the "core" subsystem from the simulator. */
63 sim_core_uninstall (SIM_DESC sd)
65 sim_core *core = STATE_CORE (sd);
67 /* blow away any mappings */
68 for (map = 0; map < nr_maps; map++) {
69 sim_core_mapping *curr = core->common.map[map].first;
70 while (curr != NULL) {
71 sim_core_mapping *tbd = curr;
73 if (tbd->free_buffer != NULL) {
74 SIM_ASSERT (tbd->buffer != NULL);
75 free (tbd->free_buffer);
79 core->common.map[map].first = NULL;
87 sim_core_init (SIM_DESC sd)
96 #ifndef SIM_CORE_SIGNAL
97 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
98 sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
101 #if EXTERN_SIM_CORE_P
103 sim_core_signal (SIM_DESC sd,
109 transfer_type transfer,
110 sim_core_signals sig)
112 const char *copy = (transfer == read_transfer ? "read" : "write");
113 address_word ip = CIA_ADDR (cia);
116 case sim_core_unmapped_signal:
117 sim_io_eprintf (sd, "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
118 nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
119 sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGSEGV);
121 case sim_core_unaligned_signal:
122 sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
123 nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
124 sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGBUS);
127 sim_engine_abort (sd, cpu, cia,
128 "sim_core_signal - internal error - bad switch");
134 #if EXTERN_SIM_CORE_P
135 static sim_core_mapping *
136 new_sim_core_mapping (SIM_DESC sd,
140 address_word nr_bytes,
146 sim_core_mapping *new_mapping = ZALLOC (sim_core_mapping);
148 new_mapping->level = level;
149 new_mapping->space = space;
150 new_mapping->base = addr;
151 new_mapping->nr_bytes = nr_bytes;
152 new_mapping->bound = addr + (nr_bytes - 1);
153 new_mapping->mask = modulo - 1;
154 new_mapping->buffer = buffer;
155 new_mapping->free_buffer = free_buffer;
156 new_mapping->device = device;
162 #if EXTERN_SIM_CORE_P
164 sim_core_map_attach (SIM_DESC sd,
165 sim_core_map *access_map,
169 address_word nr_bytes,
171 struct hw *client, /*callback/default*/
172 void *buffer, /*raw_memory*/
173 void *free_buffer) /*raw_memory*/
175 /* find the insertion point for this additional mapping and then
177 sim_core_mapping *next_mapping;
178 sim_core_mapping **last_mapping;
180 SIM_ASSERT ((client == NULL) != (buffer == NULL));
181 SIM_ASSERT ((client == NULL) >= (free_buffer != NULL));
183 /* actually do occasionally get a zero size map */
187 sim_hw_abort (sd, client, "called on sim_core_map_attach with size zero");
189 sim_io_error (sd, "called on sim_core_map_attach with size zero");
192 /* find the insertion point (between last/next) */
193 next_mapping = access_map->first;
194 last_mapping = &access_map->first;
195 while (next_mapping != NULL
196 && (next_mapping->level < level
197 || (next_mapping->level == level
198 && next_mapping->bound < addr)))
200 /* provided levels are the same */
201 /* assert: next_mapping->base > all bases before next_mapping */
202 /* assert: next_mapping->bound >= all bounds before next_mapping */
203 last_mapping = &next_mapping->next;
204 next_mapping = next_mapping->next;
207 /* check insertion point correct */
208 SIM_ASSERT (next_mapping == NULL || next_mapping->level >= level);
209 if (next_mapping != NULL && next_mapping->level == level
210 && next_mapping->base < (addr + (nr_bytes - 1)))
213 sim_hw_abort (sd, client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
216 (long) (addr + (nr_bytes - 1)),
219 (long) next_mapping->base,
220 (long) next_mapping->bound,
221 (long) next_mapping->nr_bytes);
223 sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
226 (long) (addr + (nr_bytes - 1)),
229 (long) next_mapping->base,
230 (long) next_mapping->bound,
231 (long) next_mapping->nr_bytes);
234 /* create/insert the new mapping */
235 *last_mapping = new_sim_core_mapping (sd,
237 space, addr, nr_bytes, modulo,
238 client, buffer, free_buffer);
239 (*last_mapping)->next = next_mapping;
244 /* Attach memory or a memory mapped device to the simulator.
245 See sim-core.h for a full description. */
247 #if EXTERN_SIM_CORE_P
249 sim_core_attach (SIM_DESC sd,
255 address_word nr_bytes,
258 void *optional_buffer)
260 sim_core *memory = STATE_CORE (sd);
265 /* check for for attempt to use unimplemented per-processor core map */
267 sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported");
269 if (client != NULL && modulo != 0)
272 sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo and callback memory conflict");
274 sim_io_error (sd, "sim_core_attach - internal error - modulo and callback memory conflict");
278 unsigned mask = modulo - 1;
280 while (mask >= sizeof (unsigned64)) /* minimum modulo */
287 if (mask != sizeof (unsigned64) - 1)
290 sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
292 sim_io_error (sd, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
296 /* verify consistency between device and buffer */
297 if (client != NULL && optional_buffer != NULL)
300 sim_hw_abort (sd, client, "sim_core_attach - internal error - conflicting buffer and attach arguments");
302 sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments");
306 if (optional_buffer == NULL)
308 int padding = (addr % sizeof (unsigned64));
309 unsigned long bytes = (modulo == 0 ? nr_bytes : modulo) + padding;
310 free_buffer = zalloc (bytes);
311 buffer = (char*) free_buffer + padding;
315 buffer = optional_buffer;
326 /* attach the region to all applicable access maps */
331 if (mapmask & (1 << map))
333 sim_core_map_attach (sd, &memory->common.map[map],
334 level, space, addr, nr_bytes, modulo,
335 client, buffer, free_buffer);
340 /* Just copy this map to each of the processor specific data structures.
341 FIXME - later this will be replaced by true processor specific
345 for (i = 0; i < MAX_NR_PROCESSORS; i++)
347 CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
354 /* Remove any memory reference related to this address */
355 #if EXTERN_SIM_CORE_P
357 sim_core_map_detach (SIM_DESC sd,
358 sim_core_map *access_map,
363 sim_core_mapping **entry;
364 for (entry = &access_map->first;
366 entry = &(*entry)->next)
368 if ((*entry)->base == addr
369 && (*entry)->level == level
370 && (*entry)->space == space)
372 sim_core_mapping *dead = (*entry);
373 (*entry) = dead->next;
374 if (dead->free_buffer != NULL)
375 free (dead->free_buffer);
383 #if EXTERN_SIM_CORE_P
385 sim_core_detach (SIM_DESC sd,
391 sim_core *memory = STATE_CORE (sd);
393 for (map = 0; map < nr_maps; map++)
395 sim_core_map_detach (sd, &memory->common.map[map],
396 level, address_space, addr);
398 /* Just copy this update to each of the processor specific data
399 structures. FIXME - later this will be replaced by true
400 processor specific maps. */
403 for (i = 0; i < MAX_NR_PROCESSORS; i++)
405 CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
412 STATIC_INLINE_SIM_CORE\
414 sim_core_find_mapping (sim_core_common *core,
418 transfer_type transfer,
419 int abort, /*either 0 or 1 - hint to inline/-O */
420 sim_cpu *cpu, /* abort => cpu != NULL */
423 sim_core_mapping *mapping = core->map[map].first;
424 ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
425 ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
426 ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
427 while (mapping != NULL)
429 if (addr >= mapping->base
430 && (addr + (nr_bytes - 1)) <= mapping->bound)
432 mapping = mapping->next;
436 SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer,
437 sim_core_unmapped_signal);
443 STATIC_INLINE_SIM_CORE\
445 sim_core_translate (sim_core_mapping *mapping,
448 return (void *)((unsigned8 *) mapping->buffer
449 + ((addr - mapping->base) & mapping->mask));
453 #if EXTERN_SIM_CORE_P
455 sim_core_read_buffer (SIM_DESC sd,
462 sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
466 address_word raddr = addr + count;
467 sim_core_mapping *mapping =
468 sim_core_find_mapping (core, map,
469 raddr, /*nr-bytes*/1,
471 0 /*dont-abort*/, NULL, NULL_CIA);
475 if (mapping->device != NULL)
477 int nr_bytes = len - count;
478 if (raddr + nr_bytes - 1> mapping->bound)
479 nr_bytes = mapping->bound - raddr + 1;
480 /* If the access was initiated by a cpu, pass it down so errors can
481 be propagated properly. For other sources (e.g. GDB or DMA), we
482 can only signal errors via the return value. */
485 sim_cia cia = cpu ? CPU_PC_GET (cpu) : NULL_CIA;
486 sim_cpu_hw_io_read_buffer (cpu, cia, mapping->device,
487 (unsigned_1*)buffer + count,
492 else if (sim_hw_io_read_buffer (sd, mapping->device,
493 (unsigned_1*)buffer + count,
496 nr_bytes) != nr_bytes)
502 ((unsigned_1*)buffer)[count] =
503 *(unsigned_1*)sim_core_translate (mapping, raddr);
511 #if EXTERN_SIM_CORE_P
513 sim_core_write_buffer (SIM_DESC sd,
520 sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
524 address_word raddr = addr + count;
525 sim_core_mapping *mapping =
526 sim_core_find_mapping (core, map,
527 raddr, /*nr-bytes*/1,
529 0 /*dont-abort*/, NULL, NULL_CIA);
533 if (mapping->device != NULL)
535 int nr_bytes = len - count;
536 if (raddr + nr_bytes - 1 > mapping->bound)
537 nr_bytes = mapping->bound - raddr + 1;
538 /* If the access was initiated by a cpu, pass it down so errors can
539 be propagated properly. For other sources (e.g. GDB or DMA), we
540 can only signal errors via the return value. */
543 sim_cia cia = cpu ? CPU_PC_GET (cpu) : NULL_CIA;
544 sim_cpu_hw_io_write_buffer (cpu, cia, mapping->device,
545 (unsigned_1*)buffer + count,
550 else if (sim_hw_io_write_buffer (sd, mapping->device,
551 (unsigned_1*)buffer + count,
554 nr_bytes) != nr_bytes)
560 *(unsigned_1*)sim_core_translate (mapping, raddr) =
561 ((unsigned_1*)buffer)[count];
569 #if EXTERN_SIM_CORE_P
571 sim_core_set_xor (SIM_DESC sd,
575 /* set up the XOR map if required. */
576 if (WITH_XOR_ENDIAN) {
578 sim_core *core = STATE_CORE (sd);
579 sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
580 if (cpu_core != NULL)
585 mask = WITH_XOR_ENDIAN - 1;
588 while (i - 1 < WITH_XOR_ENDIAN)
590 cpu_core->xor[i-1] = mask;
591 mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
598 core->byte_xor = WITH_XOR_ENDIAN - 1;
606 sim_engine_abort (sd, NULL, NULL_CIA,
607 "Attempted to enable xor-endian mode when permenantly disabled.");
613 #if EXTERN_SIM_CORE_P
615 reverse_n (unsigned_1 *dest,
616 const unsigned_1 *src,
620 for (i = 0; i < nr_bytes; i++)
622 dest [nr_bytes - i - 1] = src [i];
628 #if EXTERN_SIM_CORE_P
630 sim_core_xor_read_buffer (SIM_DESC sd,
637 address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
638 if (!WITH_XOR_ENDIAN || !byte_xor)
639 return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
641 /* only break up transfers when xor-endian is both selected and enabled */
643 unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
644 unsigned nr_transfered = 0;
645 address_word start = addr;
646 unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
648 /* initial and intermediate transfers are broken when they cross
649 an XOR endian boundary */
650 while (nr_transfered + nr_this_transfer < nr_bytes)
651 /* initial/intermediate transfers */
653 /* since xor-endian is enabled stop^xor defines the start
654 address of the transfer */
655 stop = start + nr_this_transfer - 1;
656 SIM_ASSERT (start <= stop);
657 SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
658 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
660 return nr_transfered;
661 reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
662 nr_transfered += nr_this_transfer;
663 nr_this_transfer = WITH_XOR_ENDIAN;
667 nr_this_transfer = nr_bytes - nr_transfered;
668 stop = start + nr_this_transfer - 1;
669 SIM_ASSERT (stop == (addr + nr_bytes - 1));
670 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
672 return nr_transfered;
673 reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
680 #if EXTERN_SIM_CORE_P
682 sim_core_xor_write_buffer (SIM_DESC sd,
689 address_word byte_xor = (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->xor[0]);
690 if (!WITH_XOR_ENDIAN || !byte_xor)
691 return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
693 /* only break up transfers when xor-endian is both selected and enabled */
695 unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */
696 unsigned nr_transfered = 0;
697 address_word start = addr;
698 unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
700 /* initial and intermediate transfers are broken when they cross
701 an XOR endian boundary */
702 while (nr_transfered + nr_this_transfer < nr_bytes)
703 /* initial/intermediate transfers */
705 /* since xor-endian is enabled stop^xor defines the start
706 address of the transfer */
707 stop = start + nr_this_transfer - 1;
708 SIM_ASSERT (start <= stop);
709 SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
710 reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
711 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
713 return nr_transfered;
714 nr_transfered += nr_this_transfer;
715 nr_this_transfer = WITH_XOR_ENDIAN;
719 nr_this_transfer = nr_bytes - nr_transfered;
720 stop = start + nr_this_transfer - 1;
721 SIM_ASSERT (stop == (addr + nr_bytes - 1));
722 reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
723 if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
725 return nr_transfered;
731 #if EXTERN_SIM_CORE_P
733 sim_core_trans_addr (SIM_DESC sd,
738 sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
739 sim_core_mapping *mapping =
740 sim_core_find_mapping (core, map,
743 0 /*dont-abort*/, NULL, NULL_CIA);
746 return sim_core_translate (mapping, addr);
752 /* define the read/write 1/2/4/8/16/word functions */
755 #include "sim-n-core.h"
758 #include "sim-n-core.h"
762 #include "sim-n-core.h"
766 #include "sim-n-core.h"
770 #include "sim-n-core.h"
773 #include "sim-n-core.h"
777 #include "sim-n-core.h"
780 #include "sim-n-core.h"
783 #include "sim-n-core.h"