1 # Generate the main loop of the simulator.
2 # Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
3 # Contributed by Cygnus Support.
5 # This file is part of the GNU simulators.
7 # This program is free software; you can redistribute it and/or modify
8 # it under the terms of the GNU General Public License as published by
9 # the Free Software Foundation; either version 2, or (at your option)
12 # This program is distributed in the hope that it will be useful,
13 # but WITHOUT ANY WARRANTY; without even the implied warranty of
14 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 # GNU General Public License for more details.
17 # You should have received a copy of the GNU General Public License along
18 # with this program; if not, write to the Free Software Foundation, Inc.,
19 # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 # This file creates two files: eng.hin and mloop.cin.
22 # eng.hin defines a few macros that specify what kind of engine was selected
23 # based on the arguments to this script.
24 # mloop.cin contains the engine.
26 # ??? Rename mloop.c to eng.c?
27 # ??? Rename mainloop.in to engine.in?
28 # ??? Add options to specify output file names?
29 # ??? Rename this file to genengine.sh?
31 # Syntax: genmloop.sh [options]
36 # - specify single cpu or multiple cpus (number specifyable at runtime),
37 # maximum number is a configuration parameter
40 # -fast: include support for fast execution in addition to full featured mode
42 # Full featured mode is for tracing, profiling, etc. and is always
43 # provided. Fast mode contains no frills, except speed.
44 # A target need only provide a "full" version of one of
45 # simple,scache,pbb. If the target wants it can also provide a fast
46 # version of same. It can't provide more than this.
47 # ??? Later add ability to have another set of full/fast semantics
48 # for use in with-devices/with-smp situations (pbb can be inappropriate
51 # -full-switch: same as -fast but for full featured version of -switch
52 # Only needed if -fast present.
54 # -simple: simple execution engine (the default)
56 # This engine fetches and executes one instruction at a time.
57 # Field extraction is done in the semantic routines.
59 # ??? There are two possible flavours of -simple. One that extracts
60 # fields in the semantic routine (which is what is implemented here),
61 # and one that stores the extracted fields in ARGBUF before calling the
62 # semantic routine. The latter is essentially the -scache case with a
63 # cache size of one (and the scache lookup code removed). There are no
64 # current uses of this and it's not clear when doing this would be a win.
65 # More complicated ISA's that want to use -simple may find this a win.
66 # Should this ever be desirable, implement a new engine style here and
67 # call it -extract (or some such). It's believed that the CGEN-generated
68 # code for the -scache case would be usable here, so no new code
69 # generation option would be needed for CGEN.
71 # -scache: use the scache to speed things up (not always a win)
73 # This engine caches the extracted instruction before executing it.
74 # When executing instructions they are first looked up in the scache.
76 # -pbb: same as -scache but extract a (pseudo-) basic block at a time
78 # This engine is basically identical to the scache version except that
79 # extraction is done a pseudo-basic-block at a time and the address of
80 # the scache entry of a branch target is recorded as well.
81 # Additional speedups are then possible by defering Ctrl-C checking
82 # to the end of basic blocks and by threading the insns together.
83 # We call them pseudo-basic-block's instead of just basic-blocks because
84 # they're not necessarily basic-blocks, though normally are.
86 # -parallel-read: support parallel execution with read-before-exec support.
87 # -parallel-write: support parallel execution with write-after-exec support.
89 # One of these options is specified in addition to -simple, -scache,
90 # -pbb. Note that while the code can determine if the cpu supports
91 # parallel execution with HAVE_PARALLEL_INSNS [and thus this option is
92 # technically unnecessary], having this option cuts down on the clutter
95 # -switch file: specify file containing semantics implemented as a switch()
99 # Specify the cpu family name.
101 # -infile <input-file>
103 # Specify the mainloop.in input file.
105 # Only one of -scache/-pbb may be selected.
106 # -simple is the default.
111 # - build mainloop.in from .cpu file
127 -multi) type=multi ;;
130 -full-switch) full_switch=yes ;;
132 -scache) scache=yes ;;
135 -parallel-read) parallel=read ;;
136 -parallel-write) parallel=write ;;
137 -switch) shift ; switch=$1 ;;
138 -cpu) shift ; cpu=$1 ;;
139 -infile) shift ; infile=$1 ;;
140 *) echo "unknown option: $1" >&2 ; exit 1 ;;
145 # Argument validation.
147 if [ x$scache = xyes -a x$pbb = xyes ] ; then
148 echo "only one of -scache and -pbb may be selected" >&2
152 if [ "x$cpu" = xunknown ] ; then
153 echo "cpu family not specified" >&2
157 if [ "x$infile" = x ] ; then
158 echo "mainloop.in not specified" >&2
162 lowercase='abcdefghijklmnopqrstuvwxyz'
163 uppercase='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
164 CPU=`echo ${cpu} | tr "${lowercase}" "${uppercase}"`
166 ##########################################################################
171 echo "/* engine configuration for ${cpu} */"
174 echo "/* WITH_FAST: non-zero if a fast version of the engine is available"
175 echo " in addition to the full-featured version. */"
176 if [ x$fast = xyes ] ; then
177 echo "#define WITH_FAST 1"
179 echo "#define WITH_FAST 0"
183 echo "/* WITH_SCACHE_PBB_${CPU}: non-zero if the pbb engine was selected. */"
184 if [ x$pbb = xyes ] ; then
185 echo "#define WITH_SCACHE_PBB_${CPU} 1"
187 echo "#define WITH_SCACHE_PBB_${CPU} 0"
191 echo "/* HAVE_PARALLEL_INSNS: non-zero if cpu can parallelly execute > 1 insn. */"
192 if [ x$parallel != xno ] ; then
193 echo "#define HAVE_PARALLEL_INSNS 1"
194 if [ x$parallel = xread ] ; then
195 echo "/* Parallel execution is supported by read-before-exec. */"
196 echo "#define WITH_PARALLEL_READ 1"
197 echo "#define WITH_PARALLEL_WRITE 0"
199 echo "/* Parallel execution is supported by write-after-exec. */"
200 echo "#define WITH_PARALLEL_READ 0"
201 echo "#define WITH_PARALLEL_WRITE 1"
204 echo "#define HAVE_PARALLEL_INSNS 0"
205 echo "#define WITH_PARALLEL_READ 0"
206 echo "#define WITH_PARALLEL_WRITE 0"
209 if [ "x$switch" != x ] ; then
211 echo "/* WITH_SEM_SWITCH_FULL: non-zero if full-featured engine is"
212 echo " implemented as a switch(). */"
213 if [ x$fast != xyes -o x$full_switch = xyes ] ; then
214 echo "#define WITH_SEM_SWITCH_FULL 1"
216 echo "#define WITH_SEM_SWITCH_FULL 0"
219 echo "/* WITH_SEM_SWITCH_FAST: non-zero if fast engine is"
220 echo " implemented as a switch(). */"
221 if [ x$fast = xyes ] ; then
222 echo "#define WITH_SEM_SWITCH_FAST 1"
224 echo "#define WITH_SEM_SWITCH_FAST 0"
228 # Decls of functions we define.
231 echo "/* Functions defined in the generated mainloop.c file"
232 echo " (which doesn't necessarily have that file name). */"
234 echo "extern ENGINE_FN ${cpu}_engine_run_full;"
235 echo "extern ENGINE_FN ${cpu}_engine_run_fast;"
237 if [ x$pbb = xyes ] ; then
239 echo "extern SEM_PC ${cpu}_pbb_begin (SIM_CPU *, int);"
240 echo "extern SEM_PC ${cpu}_pbb_chain (SIM_CPU *, SEM_ARG);"
241 echo "extern SEM_PC ${cpu}_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_PC *, PCADDR);"
242 echo "extern void ${cpu}_pbb_before (SIM_CPU *, SCACHE *);"
243 echo "extern void ${cpu}_pbb_after (SIM_CPU *, SCACHE *);"
246 ##########################################################################
248 rm -f tmp-mloop.cin mloop.cin
251 # We use @cpu@ instead of ${cpu} because we still need to run sed to handle
252 # transformation of @cpu@ for mainloop.in, so there's no need to use ${cpu}
256 /* This file is generated by the genmloop script. DO NOT EDIT! */
258 /* Enable switch() support in cgen headers. */
259 #define SEM_IN_SWITCH
261 #define WANT_CPU @cpu@
262 #define WANT_CPU_@CPU@
264 #include "sim-main.h"
266 #include "cgen-mem.h"
267 #include "cgen-ops.h"
268 #include "sim-assert.h"
270 /* Fill in the administrative ARGBUF fields required by all insns,
274 @cpu@_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
275 PCADDR pc, int fast_p)
278 SEM_SET_CODE (abuf, idesc, fast_p);
279 ARGBUF_ADDR (abuf) = pc;
281 ARGBUF_IDESC (abuf) = idesc;
284 /* Fill in tracing/profiling fields of an ARGBUF. */
287 @cpu@_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
288 int trace_p, int profile_p)
290 ARGBUF_TRACE_P (abuf) = trace_p;
291 ARGBUF_PROFILE_P (abuf) = profile_p;
296 /* Emit the "x-before" handler.
297 x-before is emitted before each insn (serial or parallel).
298 This is as opposed to x-after which is only emitted at the end of a group
299 of parallel insns. */
302 @cpu@_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
304 ARGBUF *abuf = &sc[0].argbuf;
305 const IDESC *id = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEFORE];
307 abuf->fields.before.first_p = first_p;
308 @cpu@_fill_argbuf (current_cpu, abuf, id, pc, 0);
309 /* no need to set trace_p,profile_p */
312 /* Emit the "x-after" handler.
313 x-after is emitted after a serial insn or at the end of a group of
317 @cpu@_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
319 ARGBUF *abuf = &sc[0].argbuf;
320 const IDESC *id = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_AFTER];
322 @cpu@_fill_argbuf (current_cpu, abuf, id, pc, 0);
323 /* no need to set trace_p,profile_p */
326 #endif /* WITH_SCACHE_PBB */
330 ${SHELL} $infile support
332 ##########################################################################
334 # Simple engine: fetch an instruction, execute the instruction.
336 # Instruction fields are not extracted into ARGBUF, they are extracted in
337 # the semantic routines themselves. However, there is still a need to pass
338 # and return misc. information to the semantic routines so we still use ARGBUF.
339 # [One could certainly implement things differently and remove ARGBUF.
340 # It's not clear this is necessarily always a win.]
341 # ??? The use of the SCACHE struct is for consistency with the with-scache
342 # case though it might be a source of confusion.
344 if [ x$scache != xyes -a x$pbb != xyes ] ; then
351 @cpu@_engine_run_full (SIM_CPU *current_cpu)
354 SIM_DESC current_state = CPU_STATE (current_cpu);
355 /* ??? Use of SCACHE is a bit of a hack as we don't actually use the scache.
356 We do however use ARGBUF so for consistency with the other engine flavours
357 the SCACHE type is used. */
358 SCACHE cache[MAX_LIW_INSNS];
359 SCACHE *sc = &cache[0];
363 if [ x$parallel != xno ] ; then
365 PAREXEC pbufs[MAX_PARALLEL_INSNS];
371 # Any initialization code before looping starts.
372 # Note that this code may declare some locals.
373 ${SHELL} $infile init
375 if [ x$parallel != xno ] ; then
378 #if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__)
380 if (! CPU_IDESC_READ_INIT_P (current_cpu))
382 /* ??? Later maybe paste read.c in when building mainloop.c. */
383 #define DEFINE_LABELS
385 CPU_IDESC_READ_INIT_P (current_cpu) = 1;
395 #if WITH_SEM_SWITCH_FULL && defined (__GNUC__)
397 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
399 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
400 #define DEFINE_LABELS
402 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
409 /* begin full-exec-simple */
412 ${SHELL} $infile full-exec-simple
415 /* end full-exec-simple */
417 ++ CPU_INSN_COUNT (current_cpu);
419 while (0 /*CPU_RUNNING_P (current_cpu)*/);
426 ####################################
428 # Simple engine: fast version.
429 # ??? A somewhat dubious effort, but for completeness' sake.
431 if [ x$fast = xyes ] ; then
437 FIXME: "fast simple version unimplemented, delete -fast arg to genmloop.sh."
447 ##########################################################################
449 # Scache engine: lookup insn in scache, fetch if missing, then execute it.
451 if [ x$scache = xyes ] ; then
455 static INLINE SCACHE *
456 @cpu@_scache_lookup (SIM_CPU *current_cpu, PCADDR vpc, SCACHE *scache,
457 unsigned int hash_mask, int FAST_P)
459 /* First step: look up current insn in hash table. */
460 SCACHE *sc = scache + SCACHE_HASH_PC (vpc, hash_mask);
462 /* If the entry isn't the one we want (cache miss),
463 fetch and decode the instruction. */
464 if (sc->argbuf.addr != vpc)
469 PROFILE_COUNT_SCACHE_MISS (current_cpu);
471 /* begin extract-scache */
474 ${SHELL} $infile extract-scache
477 /* end extract-scache */
481 PROFILE_COUNT_SCACHE_HIT (current_cpu);
482 /* Make core access statistics come out right.
483 The size is a guess, but it's currently not used either. */
484 PROFILE_COUNT_CORE (current_cpu, vpc, 2, exec_map);
493 @cpu@_engine_run_full (SIM_CPU *current_cpu)
495 SIM_DESC current_state = CPU_STATE (current_cpu);
496 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
497 unsigned int hash_mask = CPU_SCACHE_HASH_MASK (current_cpu);
502 if [ x$parallel != xno ] ; then
504 PAREXEC pbufs[MAX_PARALLEL_INSNS];
510 # Any initialization code before looping starts.
511 # Note that this code may declare some locals.
512 ${SHELL} $infile init
514 if [ x$parallel != xno ] ; then
517 #if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__)
519 if (! CPU_IDESC_READ_INIT_P (current_cpu))
521 /* ??? Later maybe paste read.c in when building mainloop.c. */
522 #define DEFINE_LABELS
524 CPU_IDESC_READ_INIT_P (current_cpu) = 1;
540 sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
542 /* begin full-exec-scache */
545 ${SHELL} $infile full-exec-scache
548 /* end full-exec-scache */
552 ++ CPU_INSN_COUNT (current_cpu);
554 while (0 /*CPU_RUNNING_P (current_cpu)*/);
561 ####################################
563 # Scache engine: fast version.
565 if [ x$fast = xyes ] ; then
572 @cpu@_engine_run_fast (SIM_CPU *current_cpu)
574 SIM_DESC current_state = CPU_STATE (current_cpu);
575 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
576 unsigned int hash_mask = CPU_SCACHE_HASH_MASK (current_cpu);
581 if [ x$parallel != xno ] ; then
583 PAREXEC pbufs[MAX_PARALLEL_INSNS];
589 # Any initialization code before looping starts.
590 # Note that this code may declare some locals.
591 ${SHELL} $infile init
593 if [ x$parallel != xno ] ; then
596 #if defined (HAVE_PARALLEL_EXEC) && defined (__GNUC__)
598 if (! CPU_IDESC_READ_INIT_P (current_cpu))
600 /* ??? Later maybe paste read.c in when building mainloop.c. */
601 #define DEFINE_LABELS
603 CPU_IDESC_READ_INIT_P (current_cpu) = 1;
613 #if WITH_SEM_SWITCH_FAST && defined (__GNUC__)
615 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
617 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
618 #define DEFINE_LABELS
620 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
631 sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
633 /* begin fast-exec-scache */
636 ${SHELL} $infile fast-exec-scache
639 /* end fast-exec-scache */
643 ++ CPU_INSN_COUNT (current_cpu);
645 while (0 /*CPU_RUNNING_P (current_cpu)*/);
656 ##########################################################################
658 # Compilation engine: lookup insn in scache, extract a pbb
659 # (pseudo-basic-block) if missing, then execute the pbb.
660 # A "pbb" is a sequence of insns up to the next cti insn or until
661 # some prespecified maximum.
662 # CTI: control transfer instruction.
664 if [ x$pbb = xyes ] ; then
668 /* Record address of cti terminating a pbb. */
669 #define SET_CTI_VPC(sc) do { _cti_sc = (sc); } while (0)
670 /* Record number of [real] insns in pbb. */
671 #define SET_INSN_COUNT(n) do { _insn_count = (n); } while (0)
673 /* Fetch and extract a pseudo-basic-block.
674 FAST_P is non-zero if no tracing/profiling/etc. is wanted. */
677 @cpu@_pbb_begin (SIM_CPU *current_cpu, int FAST_P)
682 int max_insns = CPU_SCACHE_MAX_CHAIN_LENGTH (current_cpu);
686 new_vpc = scache_lookup_or_alloc (current_cpu, pc, max_insns, &sc);
689 /* Leading '_' to avoid collision with mainloop.in. */
691 SCACHE *orig_sc = sc;
692 SCACHE *_cti_sc = NULL;
693 int slice_insns = CPU_MAX_SLICE_INSNS (current_cpu);
695 /* First figure out how many instructions to compile.
696 MAX_INSNS is the size of the allocated buffer, which includes space
697 for before/after handlers if they're being used.
698 SLICE_INSNS is the maxinum number of real insns that can be
699 executed. Zero means "as many as we want". */
700 /* ??? max_insns is serving two incompatible roles.
701 1) Number of slots available in scache buffer.
702 2) Number of real insns to execute.
703 They're incompatible because there are virtual insns emitted too
704 (chain,cti-chain,before,after handlers). */
706 if (slice_insns == 1)
708 /* No need to worry about extra slots required for virtual insns
709 and parallel exec support because MAX_CHAIN_LENGTH is
710 guaranteed to be big enough to execute at least 1 insn! */
715 /* Allow enough slop so that while compiling insns, if max_insns > 0
716 then there's guaranteed to be enough space to emit one real insn.
717 MAX_CHAIN_LENGTH is typically much longer than
718 the normal number of insns between cti's anyway. */
719 max_insns -= (1 /* one for the trailing chain insn */
722 : (1 + MAX_PARALLEL_INSNS) /* before+after */)
723 + (MAX_PARALLEL_INSNS > 1
724 ? (MAX_PARALLEL_INSNS * 2)
727 /* Account for before/after handlers. */
732 && slice_insns < max_insns)
733 max_insns = slice_insns;
738 /* SC,PC must be updated to point passed the last entry used.
739 SET_CTI_VPC must be called if pbb is terminated by a cti.
740 SET_INSN_COUNT must be called to record number of real insns in
741 pbb [could be computed by us of course, extra cpu but perhaps
742 negligible enough]. */
744 /* begin extract-pbb */
747 ${SHELL} $infile extract-pbb
750 /* end extract-pbb */
752 /* The last one is a pseudo-insn to link to the next chain.
753 It is also used to record the insn count for this chain. */
757 /* Was pbb terminated by a cti? */
760 id = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_CTI_CHAIN];
764 id = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_CHAIN];
766 SEM_SET_CODE (&sc->argbuf, id, FAST_P);
767 sc->argbuf.idesc = id;
768 sc->argbuf.addr = pc;
769 sc->argbuf.fields.chain.insn_count = _insn_count;
770 sc->argbuf.fields.chain.next = 0;
774 /* Update the pointer to the next free entry. */
775 CPU_SCACHE_NEXT_FREE (current_cpu) = sc;
776 /* Record length of chain if profiling.
777 This includes virtual insns since they count against
780 PROFILE_COUNT_SCACHE_CHAIN_LENGTH (current_cpu, sc - orig_sc);
786 /* Chain to the next block from a non-cti terminated previous block. */
789 @cpu@_pbb_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg)
791 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
793 PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
795 SET_H_PC (abuf->addr);
797 /* If not running forever, exit back to main loop. */
798 if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
799 /* Also exit back to main loop if there's an event.
800 Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
801 at the "right" time, but then that was what was asked for.
802 There is no silver bullet for simulator engines.
803 ??? Clearly this needs a cleaner interface.
804 At present it's just so Ctrl-C works. */
805 || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
806 CPU_RUNNING_P (current_cpu) = 0;
808 /* If chained to next block, go straight to it. */
809 if (abuf->fields.chain.next)
810 return abuf->fields.chain.next;
811 /* See if next block has already been compiled. */
812 abuf->fields.chain.next = scache_lookup (current_cpu, abuf->addr);
813 if (abuf->fields.chain.next)
814 return abuf->fields.chain.next;
815 /* Nope, so next insn is a virtual insn to invoke the compiler
817 return CPU_SCACHE_PBB_BEGIN (current_cpu);
820 /* Chain to the next block from a cti terminated previous block.
821 NEW_VPC_PTR is one of SEM_BRANCH_UNTAKEN, SEM_BRANCH_UNCACHEABLE, or
822 a pointer to a location containing the SEM_PC of the branch's address.
823 NEW_PC is the target's branch address, and is only valid if
824 NEW_VPC_PTR != SEM_BRANCH_UNTAKEN. */
827 @cpu@_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg,
828 SEM_PC *new_vpc_ptr, PCADDR new_pc)
832 PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
834 /* If not running forever, exit back to main loop. */
835 if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
836 /* Also exit back to main loop if there's an event.
837 Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
838 at the "right" time, but then that was what was asked for.
839 There is no silver bullet for simulator engines.
840 ??? Clearly this needs a cleaner interface.
841 At present it's just so Ctrl-C works. */
842 || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
843 CPU_RUNNING_P (current_cpu) = 0;
845 /* Restart compiler if we branched to an uncacheable address
847 if (new_vpc_ptr == SEM_BRANCH_UNCACHEABLE)
850 return CPU_SCACHE_PBB_BEGIN (current_cpu);
853 /* If branch wasn't taken, update the pc and set BR_ADDR_PTR to our
855 if (new_vpc_ptr == SEM_BRANCH_UNTAKEN)
857 abuf = SEM_ARGBUF (sem_arg);
858 SET_H_PC (abuf->addr);
859 new_vpc_ptr = &abuf->fields.chain.next;
866 /* If chained to next block, go straight to it. */
869 /* See if next block has already been compiled. */
870 *new_vpc_ptr = scache_lookup (current_cpu, GET_H_PC ());
873 /* Nope, so next insn is a virtual insn to invoke the compiler
875 return CPU_SCACHE_PBB_BEGIN (current_cpu);
879 This is called before each insn. */
882 @cpu@_pbb_before (SIM_CPU *current_cpu, SCACHE *sc)
884 SEM_ARG sem_arg = sc;
885 const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
886 int first_p = abuf->fields.before.first_p;
887 const ARGBUF *cur_abuf = SEM_ARGBUF (sc + 1);
888 const IDESC *cur_idesc = cur_abuf->idesc;
889 PCADDR pc = cur_abuf->addr;
891 if (ARGBUF_PROFILE_P (cur_abuf))
892 PROFILE_COUNT_INSN (current_cpu, pc, cur_idesc->num);
894 /* If this isn't the first insn, finish up the previous one. */
898 if (PROFILE_MODEL_P (current_cpu))
900 const SEM_ARG prev_sem_arg = sc - 1;
901 const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
902 const IDESC *prev_idesc = prev_abuf->idesc;
905 /* ??? May want to measure all insns if doing insn tracing. */
906 if (ARGBUF_PROFILE_P (prev_abuf))
908 cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
909 @cpu@_model_insn_after (current_cpu, 0 /*last_p*/, cycles);
913 TRACE_INSN_FINI (current_cpu, cur_abuf, 0 /*last_p*/);
916 /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
917 if (PROFILE_MODEL_P (current_cpu)
918 && ARGBUF_PROFILE_P (cur_abuf))
919 @cpu@_model_insn_before (current_cpu, first_p);
921 TRACE_INSN_INIT (current_cpu, cur_abuf, first_p);
922 TRACE_INSN (current_cpu, cur_idesc->idata, cur_abuf, pc);
926 This is called after a serial insn or at the end of a group of parallel
930 @cpu@_pbb_after (SIM_CPU *current_cpu, SCACHE *sc)
932 SEM_ARG sem_arg = sc;
933 const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
934 const SEM_ARG prev_sem_arg = sc - 1;
935 const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
937 /* ??? May want to measure all insns if doing insn tracing. */
938 if (PROFILE_MODEL_P (current_cpu)
939 && ARGBUF_PROFILE_P (prev_abuf))
941 const IDESC *prev_idesc = prev_abuf->idesc;
944 cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
945 @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
947 TRACE_INSN_FINI (current_cpu, prev_abuf, 1 /*last_p*/);
953 @cpu@_engine_run_full (SIM_CPU *current_cpu)
955 SIM_DESC current_state = CPU_STATE (current_cpu);
956 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
957 /* virtual program counter */
959 #if WITH_SEM_SWITCH_FULL
960 /* For communication between cti's and cti-chain. */
962 SEM_PC *pbb_br_npc_ptr;
967 if [ x$parallel != xno ] ; then
969 PAREXEC pbufs[MAX_PARALLEL_INSNS];
970 PAREXEC *par_exec = &pbufs[0];
975 # Any initialization code before looping starts.
976 # Note that this code may declare some locals.
977 ${SHELL} $infile init
981 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
983 /* ??? 'twould be nice to move this up a level and only call it once.
984 On the other hand, in the "let's go fast" case the test is only done
985 once per pbb (since we only return to the main loop at the end of
986 a pbb). And in the "let's run until we're done" case we don't return
987 until the program exits. */
989 #if WITH_SEM_SWITCH_FULL && defined (__GNUC__)
990 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
991 #define DEFINE_LABELS
995 /* Initialize the "begin (compile) a pbb" virtual insn. */
996 vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
997 SEM_SET_FULL_CODE (SEM_ARGBUF (vpc),
998 & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEGIN]);
999 vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEGIN];
1001 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
1004 CPU_RUNNING_P (current_cpu) = 1;
1005 /* ??? In the case where we're returning to the main loop after every
1006 pbb we don't want to call pbb_begin each time (which hashes on the pc
1007 and does a table lookup). A way to speed this up is to save vpc
1009 vpc = @cpu@_pbb_begin (current_cpu, FAST_P);
1013 /* begin full-exec-pbb */
1016 ${SHELL} $infile full-exec-pbb
1019 /* end full-exec-pbb */
1021 while (CPU_RUNNING_P (current_cpu));
1028 ####################################
1030 # Compile engine: fast version.
1032 if [ x$fast = xyes ] ; then
1039 @cpu@_engine_run_fast (SIM_CPU *current_cpu)
1041 SIM_DESC current_state = CPU_STATE (current_cpu);
1042 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
1043 /* virtual program counter */
1045 #if WITH_SEM_SWITCH_FAST
1046 /* For communication between cti's and cti-chain. */
1048 SEM_PC *pbb_br_npc_ptr;
1053 if [ x$parallel != xno ] ; then
1055 PAREXEC pbufs[MAX_PARALLEL_INSNS];
1056 PAREXEC *par_exec = &pbufs[0];
1061 # Any initialization code before looping starts.
1062 # Note that this code may declare some locals.
1063 ${SHELL} $infile init
1067 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
1069 /* ??? 'twould be nice to move this up a level and only call it once.
1070 On the other hand, in the "let's go fast" case the test is only done
1071 once per pbb (since we only return to the main loop at the end of
1072 a pbb). And in the "let's run until we're done" case we don't return
1073 until the program exits. */
1075 #if WITH_SEM_SWITCH_FAST && defined (__GNUC__)
1076 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
1077 #define DEFINE_LABELS
1081 /* Initialize the "begin (compile) a pbb" virtual insn. */
1082 vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
1083 SEM_SET_FAST_CODE (SEM_ARGBUF (vpc),
1084 & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEGIN]);
1085 vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEGIN];
1087 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
1090 CPU_RUNNING_P (current_cpu) = 1;
1091 /* ??? In the case where we're returning to the main loop after every
1092 pbb we don't want to call pbb_begin each time (which hashes on the pc
1093 and does a table lookup). A way to speed this up is to save vpc
1095 vpc = @cpu@_pbb_begin (current_cpu, FAST_P);
1099 /* begin fast-exec-pbb */
1102 ${SHELL} $infile fast-exec-pbb
1105 /* end fast-exec-pbb */
1107 while (CPU_RUNNING_P (current_cpu));
1117 # Process @cpu@,@CPU@ appearing in mainloop.in.
1118 sed -e "s/@cpu@/$cpu/g" -e "s/@CPU@/$CPU/g" < tmp-mloop.cin > mloop.cin