1 /* Tracing support for CGEN-based simulators.
2 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #define min(a,b) ((a) < (b) ? (a) : (b))
29 #ifndef SIZE_INSTRUCTION
30 #define SIZE_INSTRUCTION 16
34 #define SIZE_LOCATION 20
41 #ifndef SIZE_LINE_NUMBER
42 #define SIZE_LINE_NUMBER 4
45 #ifndef SIZE_CYCLE_COUNT
46 #define SIZE_CYCLE_COUNT 2
49 #ifndef SIZE_TOTAL_CYCLE_COUNT
50 #define SIZE_TOTAL_CYCLE_COUNT 9
53 #ifndef SIZE_TRACE_BUF
54 #define SIZE_TRACE_BUF 1024
57 /* Text is queued in TRACE_BUF because we want to output the insn's cycle
58 count first but that isn't known until after the insn has executed.
59 This also handles the queueing of trace results, TRACE_RESULT may be
60 called multiple times for one insn. */
61 static char trace_buf[SIZE_TRACE_BUF];
62 /* If NULL, output to stdout directly. */
65 /* Non-zero if this is the first insn in a set of parallel insns. */
66 static int first_insn_p;
68 /* For communication between trace_insn and trace_result. */
69 static int printed_result_p;
71 /* Insn and its extracted fields.
72 Set by trace_insn, used by trace_insn_fini.
73 ??? Move to SIM_CPU to support heterogeneous multi-cpu case. */
74 static const struct cgen_insn *current_insn;
75 static const struct argbuf *current_abuf;
78 trace_insn_init (SIM_CPU *cpu, int first_p)
82 first_insn_p = first_p;
84 /* Set to NULL so trace_insn_fini can know if trace_insn was called. */
90 trace_insn_fini (SIM_CPU *cpu, const struct argbuf *abuf, int last_p)
92 SIM_DESC sd = CPU_STATE (cpu);
94 /* Was insn traced? It might not be if trace ranges are in effect. */
95 if (current_insn == NULL)
98 /* The first thing printed is current and total cycle counts. */
100 if (PROFILE_MODEL_P (cpu)
101 && ARGBUF_PROFILE_P (current_abuf))
103 unsigned long total = PROFILE_MODEL_TOTAL_CYCLES (CPU_PROFILE_DATA (cpu));
104 unsigned long this_insn = PROFILE_MODEL_CUR_INSN_CYCLES (CPU_PROFILE_DATA (cpu));
108 trace_printf (sd, cpu, "%-*ld %-*ld ",
109 SIZE_CYCLE_COUNT, this_insn,
110 SIZE_TOTAL_CYCLE_COUNT, total);
114 trace_printf (sd, cpu, "%-*ld %-*s ",
115 SIZE_CYCLE_COUNT, this_insn,
116 SIZE_TOTAL_CYCLE_COUNT, "---");
120 /* Print the disassembled insn. */
122 trace_printf (sd, cpu, "%s", TRACE_PREFIX (CPU_TRACE_DATA (cpu)));
125 /* Print insn results. */
127 const CGEN_OPINST *opinst = CGEN_INSN_OPERANDS (current_insn);
132 int indices[MAX_OPERAND_INSTANCES];
134 /* Fetch the operands used by the insn. */
135 /* FIXME: Add fn ptr to CGEN_CPU_DESC. */
136 CGEN_SYM (get_insn_operands) (CPU_CPU_DESC (cpu), current_insn,
137 0, CGEN_FIELDS_BITSIZE (&insn_fields),
141 CGEN_OPINST_TYPE (opinst) != CGEN_OPINST_END;
144 if (CGEN_OPINST_TYPE (opinst) == CGEN_OPINST_OUTPUT)
145 trace_result (cpu, current_insn, opinst, indices[i]);
151 /* Print anything else requested. */
154 trace_printf (sd, cpu, " %s\n", trace_buf);
156 trace_printf (sd, cpu, "\n");
160 trace_insn (SIM_CPU *cpu, const struct cgen_insn *opcode,
161 const struct argbuf *abuf, IADDR pc)
165 printed_result_p = 0;
166 current_insn = opcode;
169 if (CGEN_INSN_VIRTUAL_P (opcode))
171 trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, 0,
172 NULL, 0, CGEN_INSN_NAME (opcode));
176 CPU_DISASSEMBLER (cpu) (cpu, opcode, abuf, pc, disasm_buf);
177 trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu),
180 first_insn_p ? " " : "|",
181 SIZE_INSTRUCTION, disasm_buf);
185 trace_extract (SIM_CPU *cpu, IADDR pc, char *name, ...)
188 int printed_one_p = 0;
191 va_start (args, name);
193 trace_printf (CPU_STATE (cpu), cpu, "Extract: 0x%.*lx: %s ",
199 fmt = va_arg (args, char *);
204 trace_printf (CPU_STATE (cpu), cpu, ", ");
206 type = va_arg (args, int);
210 ival = va_arg (args, int);
211 trace_printf (CPU_STATE (cpu), cpu, fmt, ival);
220 trace_printf (CPU_STATE (cpu), cpu, "\n");
224 trace_result (SIM_CPU *cpu, char *name, int type, ...)
228 va_start (args, type);
229 if (printed_result_p)
230 cgen_trace_printf (cpu, ", ");
236 cgen_trace_printf (cpu, "%s <- 0x%x", name, va_arg (args, int));
241 /* this is separated from previous line for sunos cc */
242 di = va_arg (args, DI);
243 cgen_trace_printf (cpu, "%s <- 0x%x%08x", name,
244 GETHIDI(di), GETLODI (di));
249 printed_result_p = 1;
253 /* Print trace output to BUFPTR if active, otherwise print normally.
254 This is only for tracing semantic code. */
257 cgen_trace_printf (SIM_CPU *cpu, char *fmt, ...)
261 va_start (args, fmt);
265 if (TRACE_FILE (CPU_TRACE_DATA (cpu)) == NULL)
266 (* STATE_CALLBACK (CPU_STATE (cpu))->evprintf_filtered)
267 (STATE_CALLBACK (CPU_STATE (cpu)), fmt, args);
269 vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu)), fmt, args);
273 vsprintf (bufptr, fmt, args);
274 bufptr += strlen (bufptr);
275 /* ??? Need version of SIM_ASSERT that is always enabled. */
276 if (bufptr - trace_buf > SIZE_TRACE_BUF)
283 /* Disassembly support. */
285 /* sprintf to a "stream" */
288 sim_disasm_sprintf VPARAMS ((SFILE *f, const char *format, ...))
297 VA_START (args, format);
299 f = va_arg (args, SFILE *);
300 format = va_arg (args, char *);
302 vsprintf (f->current, format, args);
303 f->current += n = strlen (f->current);
308 /* Memory read support for an opcodes disassembler. */
311 sim_disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
312 struct disassemble_info *info)
314 SIM_CPU *cpu = (SIM_CPU *) info->application_data;
315 SIM_DESC sd = CPU_STATE (cpu);
318 length_read = sim_core_read_buffer (sd, cpu, read_map, myaddr, memaddr,
320 if (length_read != length)
325 /* Memory error support for an opcodes disassembler. */
328 sim_disasm_perror_memory (int status, bfd_vma memaddr,
329 struct disassemble_info *info)
333 info->fprintf_func (info->stream, "Unknown error %d.", status);
335 /* Actually, address between memaddr and memaddr + len was
337 info->fprintf_func (info->stream,
338 "Address 0x%x is out of bounds.",
342 /* Disassemble using the CGEN opcode table.
343 ??? While executing an instruction, the insn has been decoded and all its
344 fields have been extracted. It is certainly possible to do the disassembly
345 with that data. This seems simpler, but maybe in the future the already
346 extracted fields will be used. */
349 sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
350 const ARGBUF *abuf, IADDR pc, char *buf)
353 unsigned int base_length;
354 unsigned long insn_value;
355 struct disassemble_info disasm_info;
358 unsigned8 bytes[CGEN_MAX_INSN_SIZE];
359 unsigned16 shorts[8];
362 SIM_DESC sd = CPU_STATE (cpu);
363 CGEN_CPU_DESC cd = CPU_CPU_DESC (cpu);
364 CGEN_EXTRACT_INFO ex_info;
365 CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd));
366 int insn_bit_length = CGEN_INSN_BITSIZE (insn);
367 int insn_length = insn_bit_length / 8;
369 sfile.buffer = sfile.current = buf;
370 INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
371 (fprintf_ftype) sim_disasm_sprintf);
373 (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
374 : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
375 : BFD_ENDIAN_UNKNOWN);
377 length = sim_core_read_buffer (sd, cpu, read_map, &insn_buf, pc,
380 if (length != insn_length)
382 sim_io_error (sd, "unable to read address %x", pc);
385 /* If the entire insn will fit into an integer, then do it. Otherwise, just
386 use the bits of the base_insn. */
387 if (insn_bit_length <= 32)
388 base_length = insn_bit_length;
390 base_length = min (cd->base_insn_bitsize, insn_bit_length);
393 case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
394 case 8 : insn_value = insn_buf.bytes[0]; break;
395 case 16 : insn_value = T2H_2 (insn_buf.shorts[0]); break;
396 case 32 : insn_value = T2H_4 (insn_buf.words[0]); break;
400 disasm_info.buffer_vma = pc;
401 disasm_info.buffer = insn_buf.bytes;
402 disasm_info.buffer_length = length;
404 ex_info.dis_info = (PTR) &disasm_info;
405 ex_info.valid = (1 << length) - 1;
406 ex_info.insn_bytes = insn_buf.bytes;
408 length = (*CGEN_EXTRACT_FN (cd, insn)) (cd, insn, &ex_info, insn_value, fields, pc);
409 /* Result of extract fn is in bits. */
410 /* ??? This assumes that each instruction has a fixed length (and thus
411 for insns with multiple versions of variable lengths they would each
412 have their own table entry). */
413 if (length == insn_bit_length)
415 (*CGEN_PRINT_FN (cd, insn)) (cd, &disasm_info, insn, fields, pc, length);
419 /* This shouldn't happen, but aborting is too drastic. */
420 strcpy (buf, "***unknown***");