1 /* Simulator header for Cpu tools GENerated simulators.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
28 /* Instruction field support macros. */
30 #define EXTRACT_SIGNED(val, total, start, length) \
31 (((((val) >> ((total) - ((start) + (length)))) & ((1 << (length)) - 1)) \
32 ^ (1 << ((length) - 1))) \
33 - (1 << ((length) - 1)))
35 #define EXTRACT_UNSIGNED(val, total, start, length) \
36 (((val) >> ((total) - ((start) + (length)))) & ((1 << (length)) - 1))
38 /* Compute number of longs required to hold N bits. */
39 #define HOST_LONGS_FOR_BITS(n) \
40 (((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8)
42 /* Execution support. */
44 /* Forward decls. Defined in the machine generated arch.h and cpu.h files. */
45 typedef struct argbuf ARGBUF;
46 typedef struct scache SCACHE;
47 typedef struct parallel_exec PARALLEL_EXEC;
49 /* Types of the machine generated extract and semantic fns. */
50 typedef void (EXTRACT_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *);
51 typedef void (READ_FN) (SIM_CPU *, PCADDR, insn_t, PARALLEL_EXEC *);
52 /*typedef CIA (SEMANTIC_FN) (SEM_ARG);*/
53 typedef PCADDR (SEMANTIC_FN) (SIM_CPU *, ARGBUF *);
55 typedef void (EXTRACT_CACHE_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *);
57 typedef PCADDR (SEMANTIC_CACHE_FN) (SIM_CPU *, SCACHE *);
60 /* Using cgen_insn_type requires <cpu>-opc.h. */
61 int /*enum cgen_insn_type*/ insn_type;
62 const struct cgen_insn *opcode;
64 #ifdef HAVE_PARALLEL_EXEC
65 #ifdef USE_READ_SWITCH
75 SEMANTIC_FN *semantic;
77 EXTRACT_CACHE_FN *extract_fast;
79 SEMANTIC_CACHE_FN *semantic_fast;
80 #if WITH_SEM_SWITCH_FULL && defined (__GNUC__)
84 #if WITH_SEM_SWITCH_FAST && defined (__GNUC__)
86 void *semantic_lab; /* FIXME: Rename to sem_fast_lab. */
92 Semantic functions come in two versions.
93 One that uses the cache, and one that doesn't.
94 ??? The one that doesn't may eventually be thrown away or replaced with
99 /* instruction address */
100 typedef PCADDR IADDR;
101 /* current instruction address */
103 /* argument to semantic functions */
104 typedef SCACHE *SEM_ARG;
106 #else /* ! SCACHE_P */
108 /* instruction address */
109 typedef PCADDR IADDR;
110 /* current instruction address */
112 /* argument to semantic functions */
113 typedef ARGBUF *SEM_ARG;
115 #endif /* ! SCACHE_P */
117 /* Scache data for each cpu. */
119 typedef struct cpu_scache {
120 /* Simulator cache size. */
122 #define CPU_SCACHE_SIZE(cpu) ((cpu) -> cgen_cpu.scache.size)
125 #define CPU_SCACHE_CACHE(cpu) ((cpu) -> cgen_cpu.scache.cache)
126 #if 0 /* FIXME: wip */
129 #define CPU_SCACHE_FREE(cpu) ((cpu) -> cgen_cpu.scache.free)
132 #define CPU_SCACHE_HASH_TABLE(cpu) ((cpu) -> cgen_cpu.scache.hash_table)
135 #if WITH_PROFILE_SCACHE_P
136 /* Cache hits, misses. */
137 unsigned long hits, misses;
138 #define CPU_SCACHE_HITS(cpu) ((cpu) -> cgen_cpu.scache.hits)
139 #define CPU_SCACHE_MISSES(cpu) ((cpu) -> cgen_cpu.scache.misses)
143 /* Default number of cached blocks. */
144 #ifdef CONFIG_SIM_CACHE_SIZE
145 #define SCACHE_DEFAULT_CACHE_SIZE CONFIG_SIM_CACHE_SIZE
147 #define SCACHE_DEFAULT_CACHE_SIZE 1024
150 /* Hash a PC value. */
151 /* FIXME: cpu specific */
152 #define SCACHE_HASH_PC(state, pc) \
153 (((pc) >> 1) & (STATE_SCACHE_SIZE (sd) - 1))
155 /* Non-zero if cache is in use. */
156 #define USING_SCACHE_P(sd) (STATE_SCACHE_SIZE (sd) > 0)
158 /* Install the simulator cache into the simulator. */
159 MODULE_INSTALL_FN scache_install;
161 /* Flush all cpu's caches. */
162 void scache_flush (SIM_DESC);
164 /* Scache profiling support. */
166 /* Print summary scache usage information. */
167 void scache_print_profile (SIM_CPU *cpu, int verbose);
169 #if WITH_PROFILE_SCACHE_P
170 #define PROFILE_COUNT_SCACHE_HIT(cpu) \
172 if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \
173 ++ CPU_SCACHE_HITS (cpu); \
175 #define PROFILE_COUNT_SCACHE_MISS(cpu) \
177 if (CPU_PROFILE_FLAGS (cpu) [PROFILE_SCACHE_IDX]) \
178 ++ CPU_SCACHE_MISSES (cpu); \
181 #define PROFILE_COUNT_SCACHE_HIT(cpu)
182 #define PROFILE_COUNT_SCACHE_MISS(cpu)
185 /* Engine support. */
187 /* Values to denote parallel/sequential execution. */
188 #define EXEC_SEQUENCE 0
189 #define EXEC_PARALLEL 1
193 #define CIA_ADDR(cia) (cia)
195 /* These are used so that we can compile two copies of the semantic code,
196 one with scache support and one without. */
197 /* FIXME: Do we want _ex_ or _exc_? */
198 /*#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_exc_,fn)*/
199 #define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn)
200 #define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semc_,fn)
202 /* extract.c support */
203 /* scache_unset is a cache entry that is never used.
204 It's raison d'etre is so BRANCH_VIA_CACHE doesn't have to test for
205 newval.cache == NULL. */
206 extern struct scache scache_unset;
207 #define RECORD_IADDR(fld, val) \
208 do { (fld) = (val); } while (0)
210 /* semantics.c support */
211 #define SEM_ARGBUF(sem_arg) (&(sem_arg) -> argbuf)
212 #define SEM_INSN(sem_arg) shouldnt_be_used
213 #define SEM_NEXT_PC(sc) ((sc) -> next)
214 #define SEM_BRANCH_VIA_CACHE(sc, newval) (newval)
215 #define SEM_BRANCH_VIA_ADDR(sc, newval) (newval)
216 /* Return address a branch insn will branch to.
217 This is only used during tracing. */
218 #define SEM_NEW_PC_ADDR(new_pc) (new_pc)
220 #else /* ! SCACHE_P */
222 #define CIA_ADDR(cia) (cia)
224 /* These are used so that we can compile two copies of the semantic code,
225 one with scache support and one without. */
226 #define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn)
227 #define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
229 /* extract.c support */
230 #define RECORD_IADDR(fld, val) \
231 do { (fld) = (val); } while (0)
233 /* semantics.c support */
234 #define SEM_ARGBUF(sem_arg) (sem_arg)
235 #define SEM_INSN(sem_arg) (SEM_ARGBUF (sem_arg) -> insn)
236 #define SEM_NEXT_PC(abuf) (abuf -> addr + abuf -> length)
237 #define SEM_BRANCH_VIA_CACHE(abuf, newval) (newval)
238 #define SEM_BRANCH_VIA_ADDR(abuf, newval) (newval)
239 #define SEM_NEW_PC_ADDR(new_pc) (new_pc)
241 #endif /* ! SCACHE_P */
243 /* GNU C's "computed goto" facility is used to speed things up where
244 possible. These macros provide a portable way to use them.
245 Nesting of these switch statements is done by providing an extra argument
246 that distinguishes them. `N' can be a number or symbol.
247 Variable `labels_##N' must be initialized with the labels of each case. */
249 #define SWITCH(N, X) goto *X;
250 #define CASE(N, X) case_##N##_##X
251 #define BREAK(N) goto end_switch_##N
252 #define DEFAULT(N) default_##N
253 #define ENDSWITCH(N) end_switch_##N:
255 #define SWITCH(N, X) switch (X)
256 #define CASE(N, X) case X /* FIXME: old sem-switch had (@arch@_,X) here */
257 #define BREAK(N) break
258 #define DEFAULT(N) default
262 /* Engine control (FIXME). */
263 int engine_stop (SIM_DESC);
264 void engine_run (SIM_DESC, int, int);
265 /*void engine_resume (SIM_DESC, int, int);*/
267 /* Simulator state. */
269 /* Records simulator descriptor so utilities like @cpu@_dump_regs can be
271 extern SIM_DESC current_state;
273 /* Simulator state. */
275 /* CGEN_STATE contains additional state information not present in
278 typedef struct cgen_state {
279 /* FIXME: Moved to sim_state_base. */
282 #define STATE_ARGV(s) ((s) -> cgen_state.argv)
283 /* FIXME: Move to sim_state_base. */
285 #define STATE_ENVP(s) ((s) -> cgen_state.envp)
287 /* Non-zero if no tracing or profiling is selected. */
289 #define STATE_RUN_FAST_P(sd) ((sd) -> cgen_state.run_fast_p)
292 /* Additional non-machine generated per-cpu data to go in SIM_CPU.
293 The member's name must be `cgen_cpu'. */
296 /* Simulator's execution cache. */
299 #endif /* WITH_SCACHE */
301 /* Allow slop in size calcs for case where multiple cpu types are supported
302 and space for the specified cpu is malloc'd at run time. */
306 /* Various utilities. */
308 /* Called after sim_post_argv_init to do any cgen initialization. */
309 void cgen_init (SIM_DESC);
312 sim_disassemble_insn (SIM_CPU *, const struct cgen_insn *,
313 const struct argbuf *, PCADDR, char *);
315 #endif /* CGEN_SIM_H */