1 /* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model.
2 For "new style" UARTs on BF50x/BF54x parts.
4 Copyright (C) 2010-2014 Free Software Foundation, Inc.
5 Contributed by Analog Devices, Inc.
7 This file is part of simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "dv-bfin_uart2.h"
28 /* XXX: Should we bother emulating the TX/RX FIFOs ? */
30 /* Internal state needs to be the same as bfin_uart. */
33 /* This top portion matches common dv_bfin struct. */
35 struct hw *dma_master;
38 struct hw_event *handler;
42 /* Accessed indirectly by ier_{set,clear}. */
45 /* Order after here is important -- matches hardware MMR layout. */
46 bu16 BFIN_MMR_16(dll);
47 bu16 BFIN_MMR_16(dlh);
48 bu16 BFIN_MMR_16(gctl);
49 bu16 BFIN_MMR_16(lcr);
50 bu16 BFIN_MMR_16(mcr);
51 bu16 BFIN_MMR_16(lsr);
52 bu16 BFIN_MMR_16(msr);
53 bu16 BFIN_MMR_16(scr);
54 bu16 BFIN_MMR_16(ier_set);
55 bu16 BFIN_MMR_16(ier_clear);
56 bu16 BFIN_MMR_16(thr);
57 bu16 BFIN_MMR_16(rbr);
59 #define mmr_base() offsetof(struct bfin_uart, dll)
60 #define mmr_offset(mmr) (offsetof(struct bfin_uart, mmr) - mmr_base())
62 static const char * const mmr_names[] =
64 "UART_DLL", "UART_DLH", "UART_GCTL", "UART_LCR", "UART_MCR", "UART_LSR",
65 "UART_MSR", "UART_SCR", "UART_IER_SET", "UART_IER_CLEAR", "UART_THR",
68 #define mmr_name(off) mmr_names[(off) / 4]
71 bfin_uart_io_write_buffer (struct hw *me, const void *source,
72 int space, address_word addr, unsigned nr_bytes)
74 struct bfin_uart *uart = hw_data (me);
79 value = dv_load_2 (source);
80 mmr_off = addr - uart->base;
81 valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
85 dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
87 /* XXX: All MMRs are "8bit" ... what happens to high 8bits ? */
92 uart->thr = bfin_uart_write_byte (me, value, uart->mcr);
93 if (uart->ier & ETBEI)
94 hw_port_event (me, DV_PORT_TX, 1);
96 case mmr_offset(ier_set):
99 case mmr_offset(ier_clear):
100 dv_w1c_2 (&uart->ier, value, -1);
102 case mmr_offset(lsr):
103 dv_w1c_2 (valuep, value, TFI | BI | FE | PE | OE);
105 case mmr_offset(rbr):
106 /* XXX: Writes are ignored ? */
108 case mmr_offset(msr):
109 dv_w1c_2 (valuep, value, SCTS);
111 case mmr_offset(dll):
112 case mmr_offset(dlh):
113 case mmr_offset(gctl):
114 case mmr_offset(lcr):
115 case mmr_offset(mcr):
116 case mmr_offset(scr):
120 dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
128 bfin_uart_io_read_buffer (struct hw *me, void *dest,
129 int space, address_word addr, unsigned nr_bytes)
131 struct bfin_uart *uart = hw_data (me);
135 mmr_off = addr - uart->base;
136 valuep = (void *)((unsigned long)uart + mmr_base() + mmr_off);
140 dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
144 case mmr_offset(rbr):
145 uart->rbr = bfin_uart_get_next_byte (me, uart->rbr, uart->mcr, NULL);
146 dv_store_2 (dest, uart->rbr);
148 case mmr_offset(ier_set):
149 case mmr_offset(ier_clear):
150 dv_store_2 (dest, uart->ier);
151 bfin_uart_reschedule (me);
153 case mmr_offset(lsr):
154 uart->lsr &= ~(DR | THRE | TEMT);
155 uart->lsr |= bfin_uart_get_status (me);
156 case mmr_offset(thr):
157 case mmr_offset(msr):
158 case mmr_offset(dll):
159 case mmr_offset(dlh):
160 case mmr_offset(gctl):
161 case mmr_offset(lcr):
162 case mmr_offset(mcr):
163 case mmr_offset(scr):
164 dv_store_2 (dest, *valuep);
167 dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
175 bfin_uart_dma_read_buffer (struct hw *me, void *dest, int space,
176 unsigned_word addr, unsigned nr_bytes)
178 HW_TRACE_DMA_READ ();
179 return bfin_uart_read_buffer (me, dest, nr_bytes);
183 bfin_uart_dma_write_buffer (struct hw *me, const void *source,
184 int space, unsigned_word addr,
186 int violate_read_only_section)
188 struct bfin_uart *uart = hw_data (me);
191 HW_TRACE_DMA_WRITE ();
193 ret = bfin_uart_write_buffer (me, source, nr_bytes);
195 if (ret == nr_bytes && (uart->ier & ETBEI))
196 hw_port_event (me, DV_PORT_TX, 1);
201 static const struct hw_port_descriptor bfin_uart_ports[] =
203 { "tx", DV_PORT_TX, 0, output_port, },
204 { "rx", DV_PORT_RX, 0, output_port, },
205 { "stat", DV_PORT_STAT, 0, output_port, },
210 attach_bfin_uart_regs (struct hw *me, struct bfin_uart *uart)
212 address_word attach_address;
214 unsigned attach_size;
215 reg_property_spec reg;
217 if (hw_find_property (me, "reg") == NULL)
218 hw_abort (me, "Missing \"reg\" property");
220 if (!hw_find_reg_array_property (me, "reg", 0, ®))
221 hw_abort (me, "\"reg\" property must contain three addr/size entries");
223 hw_unit_address_to_attach_address (hw_parent (me),
225 &attach_space, &attach_address, me);
226 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
228 if (attach_size != BFIN_MMR_UART2_SIZE)
229 hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_UART2_SIZE);
231 hw_attach_address (hw_parent (me),
232 0, attach_space, attach_address, attach_size, me);
234 uart->base = attach_address;
238 bfin_uart_finish (struct hw *me)
240 struct bfin_uart *uart;
242 uart = HW_ZALLOC (me, struct bfin_uart);
244 set_hw_data (me, uart);
245 set_hw_io_read_buffer (me, bfin_uart_io_read_buffer);
246 set_hw_io_write_buffer (me, bfin_uart_io_write_buffer);
247 set_hw_dma_read_buffer (me, bfin_uart_dma_read_buffer);
248 set_hw_dma_write_buffer (me, bfin_uart_dma_write_buffer);
249 set_hw_ports (me, bfin_uart_ports);
251 attach_bfin_uart_regs (me, uart);
253 /* Initialize the UART. */
258 const struct hw_descriptor dv_bfin_uart2_descriptor[] =
260 {"bfin_uart2", bfin_uart_finish,},