1 /* Blackfin Serial Peripheral Interface (SPI) model
3 Copyright (C) 2010-2023 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 /* This must come before any other includes. */
26 #include "dv-bfin_spi.h"
28 /* XXX: This is merely a stub. */
32 /* This top portion matches common dv_bfin struct. */
34 struct hw *dma_master;
37 struct hw_event *handler;
41 /* Order after here is important -- matches hardware MMR layout. */
42 bu16 BFIN_MMR_16(ctl);
43 bu16 BFIN_MMR_16(flg);
44 bu16 BFIN_MMR_16(stat);
45 bu16 BFIN_MMR_16(tdbr);
46 bu16 BFIN_MMR_16(rdbr);
47 bu16 BFIN_MMR_16(baud);
48 bu16 BFIN_MMR_16(shadow);
50 #define mmr_base() offsetof(struct bfin_spi, ctl)
51 #define mmr_offset(mmr) (offsetof(struct bfin_spi, mmr) - mmr_base())
53 static const char * const mmr_names[] =
55 "SPI_CTL", "SPI_FLG", "SPI_STAT", "SPI_TDBR",
56 "SPI_RDBR", "SPI_BAUD", "SPI_SHADOW",
58 #define mmr_name(off) mmr_names[(off) / 4]
61 bfin_spi_enabled (struct bfin_spi *spi)
63 return (spi->ctl & SPE);
67 bfin_spi_timod (struct bfin_spi *spi)
69 return (spi->ctl & TIMOD);
73 bfin_spi_io_write_buffer (struct hw *me, const void *source, int space,
74 address_word addr, unsigned nr_bytes)
76 struct bfin_spi *spi = hw_data (me);
81 /* Invalid access mode is higher priority than missing register. */
82 if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
85 value = dv_load_2 (source);
86 mmr_off = addr - spi->base;
87 valuep = (void *)((uintptr_t)spi + mmr_base() + mmr_off);
93 case mmr_offset(stat):
94 dv_w1c_2 (valuep, value, ~(SPIF | TXS | RXS));
96 case mmr_offset(tdbr):
98 if (bfin_spi_enabled (spi) && bfin_spi_timod (spi) == TDBR_CORE)
104 case mmr_offset(rdbr):
105 case mmr_offset(ctl):
106 case mmr_offset(flg):
107 case mmr_offset(baud):
108 case mmr_offset(shadow):
112 dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
120 bfin_spi_io_read_buffer (struct hw *me, void *dest, int space,
121 address_word addr, unsigned nr_bytes)
123 struct bfin_spi *spi = hw_data (me);
127 /* Invalid access mode is higher priority than missing register. */
128 if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
131 mmr_off = addr - spi->base;
132 valuep = (void *)((uintptr_t)spi + mmr_base() + mmr_off);
138 case mmr_offset(rdbr):
139 dv_store_2 (dest, *valuep);
140 if (bfin_spi_enabled (spi) && bfin_spi_timod (spi) == RDBR_CORE)
141 spi->stat &= ~(RXS | TXS);
143 case mmr_offset(ctl):
144 case mmr_offset(stat):
145 case mmr_offset(flg):
146 case mmr_offset(tdbr):
147 case mmr_offset(baud):
148 case mmr_offset(shadow):
149 dv_store_2 (dest, *valuep);
152 dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
160 bfin_spi_dma_read_buffer (struct hw *me, void *dest, int space,
161 unsigned_word addr, unsigned nr_bytes)
163 HW_TRACE_DMA_READ ();
168 bfin_spi_dma_write_buffer (struct hw *me, const void *source,
169 int space, unsigned_word addr,
171 int violate_read_only_section)
173 HW_TRACE_DMA_WRITE ();
177 static const struct hw_port_descriptor bfin_spi_ports[] =
179 { "stat", 0, 0, output_port, },
184 attach_bfin_spi_regs (struct hw *me, struct bfin_spi *spi)
186 address_word attach_address;
188 unsigned attach_size;
189 reg_property_spec reg;
191 if (hw_find_property (me, "reg") == NULL)
192 hw_abort (me, "Missing \"reg\" property");
194 if (!hw_find_reg_array_property (me, "reg", 0, ®))
195 hw_abort (me, "\"reg\" property must contain three addr/size entries");
197 hw_unit_address_to_attach_address (hw_parent (me),
199 &attach_space, &attach_address, me);
200 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
202 if (attach_size != BFIN_MMR_SPI_SIZE)
203 hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_SPI_SIZE);
205 hw_attach_address (hw_parent (me),
206 0, attach_space, attach_address, attach_size, me);
208 spi->base = attach_address;
212 bfin_spi_finish (struct hw *me)
214 struct bfin_spi *spi;
216 spi = HW_ZALLOC (me, struct bfin_spi);
218 set_hw_data (me, spi);
219 set_hw_io_read_buffer (me, bfin_spi_io_read_buffer);
220 set_hw_io_write_buffer (me, bfin_spi_io_write_buffer);
221 set_hw_dma_read_buffer (me, bfin_spi_dma_read_buffer);
222 set_hw_dma_write_buffer (me, bfin_spi_dma_write_buffer);
223 set_hw_ports (me, bfin_spi_ports);
225 attach_bfin_spi_regs (me, spi);
227 /* Initialize the SPI. */
233 const struct hw_descriptor dv_bfin_spi_descriptor[] =
235 {"bfin_spi", bfin_spi_finish,},