1 /* Blackfin System Interrupt Controller (SIC) model.
3 Copyright (C) 2010-2014 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "dv-bfin_sic.h"
26 #include "dv-bfin_cec.h"
30 /* We assume first element is the base. */
33 /* Order after here is important -- matches hardware MMR layout. */
34 bu16 BFIN_MMR_16(swrst);
35 bu16 BFIN_MMR_16(syscr);
36 bu16 BFIN_MMR_16(rvect); /* XXX: BF59x has a 32bit AUX_REVID here. */
40 bu32 iar0, iar1, iar2, iar3;
44 bu32 iar4, iar5, iar6, iar7;
49 bu32 iar0, iar1, iar2, iar3;
53 bu32 imask0, imask1, imask2;
54 bu32 isr0, isr1, isr2;
55 bu32 iwr0, iwr1, iwr2;
56 bu32 iar0, iar1, iar2, iar3;
57 bu32 iar4, iar5, iar6, iar7;
58 bu32 iar8, iar9, iar10, iar11;
62 bu32 iar0, iar1, iar2, iar3;
63 bu32 iar4, iar5, iar6, iar7;
69 #define mmr_base() offsetof(struct bfin_sic, swrst)
70 #define mmr_offset(mmr) (offsetof(struct bfin_sic, mmr) - mmr_base())
71 #define mmr_idx(mmr) (mmr_offset (mmr) / 4)
73 static const char * const bf52x_mmr_names[] =
75 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IAR0", "SIC_IAR1",
76 "SIC_IAR2", "SIC_IAR3", "SIC_ISR0", "SIC_IWR0",
77 [mmr_idx (bf52x.imask1)] = "SIC_IMASK1", "SIC_IAR4", "SIC_IAR5",
78 "SIC_IAR6", "SIC_IAR7", "SIC_ISR1", "SIC_IWR1",
80 static const char * const bf537_mmr_names[] =
82 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK", "SIC_IAR0", "SIC_IAR1",
83 "SIC_IAR2", "SIC_IAR3", "SIC_ISR", "SIC_IWR",
85 static const char * const bf54x_mmr_names[] =
87 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IMASK1", "SIC_IMASK2",
88 "SIC_ISR0", "SIC_ISR1", "SIC_ISR2", "SIC_IWR0", "SIC_IWR1", "SIC_IWR2",
89 "SIC_IAR0", "SIC_IAR1", "SIC_IAR2", "SIC_IAR3",
90 "SIC_IAR4", "SIC_IAR5", "SIC_IAR6", "SIC_IAR7",
91 "SIC_IAR8", "SIC_IAR9", "SIC_IAR10", "SIC_IAR11",
93 static const char * const bf561_mmr_names[] =
95 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IMASK1",
96 "SIC_IAR0", "SIC_IAR1", "SIC_IAR2", "SIC_IAR3",
97 "SIC_IAR4", "SIC_IAR5", "SIC_IAR6", "SIC_IAR7",
98 "SIC_ISR0", "SIC_ISR1", "SIC_IWR0", "SIC_IWR1",
100 static const char * const *mmr_names;
101 #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
104 bfin_sic_forward_interrupts (struct hw *me, bu32 *isr, bu32 *imask, bu32 *iar)
109 /* Process pending and unmasked interrupts. */
110 ipend = *isr & *imask;
112 /* Usually none are pending unmasked, so avoid bit twiddling. */
116 for (my_port = 0; my_port < 32; ++my_port)
118 bu32 iar_idx, iar_off, iar_val;
119 bu32 bit = (1 << my_port);
121 /* This bit isn't pending, so check next one. */
125 /* The IAR registers map the System input to the Core output.
126 Every 4 bits in the IAR are used to map to IVG{7..15}. */
127 iar_idx = my_port / 8;
128 iar_off = (my_port % 8) * 4;
129 iar_val = (iar[iar_idx] & (0xf << iar_off)) >> iar_off;
130 HW_TRACE ((me, "forwarding int %i to CEC", IVG7 + iar_val));
131 hw_port_event (me, IVG7 + iar_val, 1);
136 bfin_sic_52x_forward_interrupts (struct hw *me, struct bfin_sic *sic)
138 bfin_sic_forward_interrupts (me, &sic->bf52x.isr0, &sic->bf52x.imask0, &sic->bf52x.iar0);
139 bfin_sic_forward_interrupts (me, &sic->bf52x.isr1, &sic->bf52x.imask1, &sic->bf52x.iar4);
143 bfin_sic_52x_io_write_buffer (struct hw *me, const void *source, int space,
144 address_word addr, unsigned nr_bytes)
146 struct bfin_sic *sic = hw_data (me);
154 value = dv_load_4 (source);
156 value = dv_load_2 (source);
158 mmr_off = addr - sic->base;
159 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
165 /* XXX: Discard all SIC writes for now. */
168 case mmr_offset(swrst):
169 /* XXX: This should trigger a software reset ... */
171 case mmr_offset(syscr):
172 /* XXX: what to do ... */
174 case mmr_offset(bf52x.imask0):
175 case mmr_offset(bf52x.imask1):
176 bfin_sic_52x_forward_interrupts (me, sic);
179 case mmr_offset(bf52x.iar0) ... mmr_offset(bf52x.iar3):
180 case mmr_offset(bf52x.iar4) ... mmr_offset(bf52x.iar7):
181 case mmr_offset(bf52x.iwr0):
182 case mmr_offset(bf52x.iwr1):
185 case mmr_offset(bf52x.isr0):
186 case mmr_offset(bf52x.isr1):
187 /* ISR is read-only. */
190 /* XXX: Should discard other writes. */
198 bfin_sic_52x_io_read_buffer (struct hw *me, void *dest, int space,
199 address_word addr, unsigned nr_bytes)
201 struct bfin_sic *sic = hw_data (me);
207 mmr_off = addr - sic->base;
208 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
216 case mmr_offset(swrst):
217 case mmr_offset(syscr):
218 case mmr_offset(rvect):
219 dv_store_2 (dest, *value16p);
221 case mmr_offset(bf52x.imask0):
222 case mmr_offset(bf52x.imask1):
223 case mmr_offset(bf52x.iar0) ... mmr_offset(bf52x.iar3):
224 case mmr_offset(bf52x.iar4) ... mmr_offset(bf52x.iar7):
225 case mmr_offset(bf52x.iwr0):
226 case mmr_offset(bf52x.iwr1):
227 case mmr_offset(bf52x.isr0):
228 case mmr_offset(bf52x.isr1):
229 dv_store_4 (dest, *value32p);
233 dv_store_2 (dest, 0);
235 dv_store_4 (dest, 0);
243 bfin_sic_537_forward_interrupts (struct hw *me, struct bfin_sic *sic)
245 bfin_sic_forward_interrupts (me, &sic->bf537.isr, &sic->bf537.imask, &sic->bf537.iar0);
249 bfin_sic_537_io_write_buffer (struct hw *me, const void *source, int space,
250 address_word addr, unsigned nr_bytes)
252 struct bfin_sic *sic = hw_data (me);
260 value = dv_load_4 (source);
262 value = dv_load_2 (source);
264 mmr_off = addr - sic->base;
265 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
271 /* XXX: Discard all SIC writes for now. */
274 case mmr_offset(swrst):
275 /* XXX: This should trigger a software reset ... */
277 case mmr_offset(syscr):
278 /* XXX: what to do ... */
280 case mmr_offset(bf537.imask):
281 bfin_sic_537_forward_interrupts (me, sic);
284 case mmr_offset(bf537.iar0):
285 case mmr_offset(bf537.iar1):
286 case mmr_offset(bf537.iar2):
287 case mmr_offset(bf537.iar3):
288 case mmr_offset(bf537.iwr):
291 case mmr_offset(bf537.isr):
292 /* ISR is read-only. */
295 /* XXX: Should discard other writes. */
303 bfin_sic_537_io_read_buffer (struct hw *me, void *dest, int space,
304 address_word addr, unsigned nr_bytes)
306 struct bfin_sic *sic = hw_data (me);
312 mmr_off = addr - sic->base;
313 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
321 case mmr_offset(swrst):
322 case mmr_offset(syscr):
323 case mmr_offset(rvect):
324 dv_store_2 (dest, *value16p);
326 case mmr_offset(bf537.imask):
327 case mmr_offset(bf537.iar0):
328 case mmr_offset(bf537.iar1):
329 case mmr_offset(bf537.iar2):
330 case mmr_offset(bf537.iar3):
331 case mmr_offset(bf537.isr):
332 case mmr_offset(bf537.iwr):
333 dv_store_4 (dest, *value32p);
337 dv_store_2 (dest, 0);
339 dv_store_4 (dest, 0);
347 bfin_sic_54x_forward_interrupts (struct hw *me, struct bfin_sic *sic)
349 bfin_sic_forward_interrupts (me, &sic->bf54x.isr0, &sic->bf54x.imask0, &sic->bf54x.iar0);
350 bfin_sic_forward_interrupts (me, &sic->bf54x.isr1, &sic->bf54x.imask1, &sic->bf54x.iar4);
351 bfin_sic_forward_interrupts (me, &sic->bf54x.isr2, &sic->bf54x.imask2, &sic->bf54x.iar8);
355 bfin_sic_54x_io_write_buffer (struct hw *me, const void *source, int space,
356 address_word addr, unsigned nr_bytes)
358 struct bfin_sic *sic = hw_data (me);
366 value = dv_load_4 (source);
368 value = dv_load_2 (source);
370 mmr_off = addr - sic->base;
371 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
377 /* XXX: Discard all SIC writes for now. */
380 case mmr_offset(swrst):
381 /* XXX: This should trigger a software reset ... */
383 case mmr_offset(syscr):
384 /* XXX: what to do ... */
386 case mmr_offset(bf54x.imask0) ... mmr_offset(bf54x.imask2):
387 bfin_sic_54x_forward_interrupts (me, sic);
390 case mmr_offset(bf54x.iar0) ... mmr_offset(bf54x.iar11):
391 case mmr_offset(bf54x.iwr0) ... mmr_offset(bf54x.iwr2):
394 case mmr_offset(bf54x.isr0) ... mmr_offset(bf54x.isr2):
395 /* ISR is read-only. */
398 /* XXX: Should discard other writes. */
406 bfin_sic_54x_io_read_buffer (struct hw *me, void *dest, int space,
407 address_word addr, unsigned nr_bytes)
409 struct bfin_sic *sic = hw_data (me);
415 mmr_off = addr - sic->base;
416 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
424 case mmr_offset(swrst):
425 case mmr_offset(syscr):
426 case mmr_offset(rvect):
427 dv_store_2 (dest, *value16p);
429 case mmr_offset(bf54x.imask0) ... mmr_offset(bf54x.imask2):
430 case mmr_offset(bf54x.iar0) ... mmr_offset(bf54x.iar11):
431 case mmr_offset(bf54x.iwr0) ... mmr_offset(bf54x.iwr2):
432 case mmr_offset(bf54x.isr0) ... mmr_offset(bf54x.isr2):
433 dv_store_4 (dest, *value32p);
437 dv_store_2 (dest, 0);
439 dv_store_4 (dest, 0);
447 bfin_sic_561_forward_interrupts (struct hw *me, struct bfin_sic *sic)
449 bfin_sic_forward_interrupts (me, &sic->bf561.isr0, &sic->bf561.imask0, &sic->bf561.iar0);
450 bfin_sic_forward_interrupts (me, &sic->bf561.isr1, &sic->bf561.imask1, &sic->bf561.iar4);
454 bfin_sic_561_io_write_buffer (struct hw *me, const void *source, int space,
455 address_word addr, unsigned nr_bytes)
457 struct bfin_sic *sic = hw_data (me);
465 value = dv_load_4 (source);
467 value = dv_load_2 (source);
469 mmr_off = addr - sic->base;
470 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
476 /* XXX: Discard all SIC writes for now. */
479 case mmr_offset(swrst):
480 /* XXX: This should trigger a software reset ... */
482 case mmr_offset(syscr):
483 /* XXX: what to do ... */
485 case mmr_offset(bf561.imask0):
486 case mmr_offset(bf561.imask1):
487 bfin_sic_561_forward_interrupts (me, sic);
490 case mmr_offset(bf561.iar0) ... mmr_offset(bf561.iar3):
491 case mmr_offset(bf561.iar4) ... mmr_offset(bf561.iar7):
492 case mmr_offset(bf561.iwr0):
493 case mmr_offset(bf561.iwr1):
496 case mmr_offset(bf561.isr0):
497 case mmr_offset(bf561.isr1):
498 /* ISR is read-only. */
501 /* XXX: Should discard other writes. */
509 bfin_sic_561_io_read_buffer (struct hw *me, void *dest, int space,
510 address_word addr, unsigned nr_bytes)
512 struct bfin_sic *sic = hw_data (me);
518 mmr_off = addr - sic->base;
519 valuep = (void *)((unsigned long)sic + mmr_base() + mmr_off);
527 case mmr_offset(swrst):
528 case mmr_offset(syscr):
529 case mmr_offset(rvect):
530 dv_store_2 (dest, *value16p);
532 case mmr_offset(bf561.imask0):
533 case mmr_offset(bf561.imask1):
534 case mmr_offset(bf561.iar0) ... mmr_offset(bf561.iar3):
535 case mmr_offset(bf561.iar4) ... mmr_offset(bf561.iar7):
536 case mmr_offset(bf561.iwr0):
537 case mmr_offset(bf561.iwr1):
538 case mmr_offset(bf561.isr0):
539 case mmr_offset(bf561.isr1):
540 dv_store_4 (dest, *value32p);
544 dv_store_2 (dest, 0);
546 dv_store_4 (dest, 0);
553 /* Give each SIC its own base to make it easier to extract the pin at
554 runtime. The pin is used as its bit position in the SIC MMRs. */
555 #define ENC(sic, pin) (((sic) << 8) + (pin))
556 #define DEC_PIN(pin) ((pin) % 0x100)
557 #define DEC_SIC(pin) ((pin) >> 8)
559 /* It would be nice to declare just one set of input_ports, and then
560 have the device tree instantiate multiple SICs, but the MMR layout
561 on the BF54x/BF561 makes this pretty hard to pull off since their
562 regs are interwoven in the address space. */
564 #define BFIN_SIC_TO_CEC_PORTS \
565 { "ivg7", IVG7, 0, output_port, }, \
566 { "ivg8", IVG8, 0, output_port, }, \
567 { "ivg9", IVG9, 0, output_port, }, \
568 { "ivg10", IVG10, 0, output_port, }, \
569 { "ivg11", IVG11, 0, output_port, }, \
570 { "ivg12", IVG12, 0, output_port, }, \
571 { "ivg13", IVG13, 0, output_port, }, \
572 { "ivg14", IVG14, 0, output_port, }, \
573 { "ivg15", IVG15, 0, output_port, },
575 #define SIC_PORTS(n) \
576 { "int0@"#n, ENC(n, 0), 0, input_port, }, \
577 { "int1@"#n, ENC(n, 1), 0, input_port, }, \
578 { "int2@"#n, ENC(n, 2), 0, input_port, }, \
579 { "int3@"#n, ENC(n, 3), 0, input_port, }, \
580 { "int4@"#n, ENC(n, 4), 0, input_port, }, \
581 { "int5@"#n, ENC(n, 5), 0, input_port, }, \
582 { "int6@"#n, ENC(n, 6), 0, input_port, }, \
583 { "int7@"#n, ENC(n, 7), 0, input_port, }, \
584 { "int8@"#n, ENC(n, 8), 0, input_port, }, \
585 { "int9@"#n, ENC(n, 9), 0, input_port, }, \
586 { "int10@"#n, ENC(n, 10), 0, input_port, }, \
587 { "int11@"#n, ENC(n, 11), 0, input_port, }, \
588 { "int12@"#n, ENC(n, 12), 0, input_port, }, \
589 { "int13@"#n, ENC(n, 13), 0, input_port, }, \
590 { "int14@"#n, ENC(n, 14), 0, input_port, }, \
591 { "int15@"#n, ENC(n, 15), 0, input_port, }, \
592 { "int16@"#n, ENC(n, 16), 0, input_port, }, \
593 { "int17@"#n, ENC(n, 17), 0, input_port, }, \
594 { "int18@"#n, ENC(n, 18), 0, input_port, }, \
595 { "int19@"#n, ENC(n, 19), 0, input_port, }, \
596 { "int20@"#n, ENC(n, 20), 0, input_port, }, \
597 { "int21@"#n, ENC(n, 21), 0, input_port, }, \
598 { "int22@"#n, ENC(n, 22), 0, input_port, }, \
599 { "int23@"#n, ENC(n, 23), 0, input_port, }, \
600 { "int24@"#n, ENC(n, 24), 0, input_port, }, \
601 { "int25@"#n, ENC(n, 25), 0, input_port, }, \
602 { "int26@"#n, ENC(n, 26), 0, input_port, }, \
603 { "int27@"#n, ENC(n, 27), 0, input_port, }, \
604 { "int28@"#n, ENC(n, 28), 0, input_port, }, \
605 { "int29@"#n, ENC(n, 29), 0, input_port, }, \
606 { "int30@"#n, ENC(n, 30), 0, input_port, }, \
607 { "int31@"#n, ENC(n, 31), 0, input_port, },
609 static const struct hw_port_descriptor bfin_sic1_ports[] =
611 BFIN_SIC_TO_CEC_PORTS
616 static const struct hw_port_descriptor bfin_sic2_ports[] =
618 BFIN_SIC_TO_CEC_PORTS
624 static const struct hw_port_descriptor bfin_sic3_ports[] =
626 BFIN_SIC_TO_CEC_PORTS
633 static const struct hw_port_descriptor bfin_sic_561_ports[] =
635 { "sup_irq@0", 0, 0, output_port, },
636 { "sup_irq@1", 1, 0, output_port, },
637 BFIN_SIC_TO_CEC_PORTS
644 bfin_sic_port_event (struct hw *me, bu32 *isr, bu32 bit, int level)
653 bfin_sic_52x_port_event (struct hw *me, int my_port, struct hw *source,
654 int source_port, int level)
656 struct bfin_sic *sic = hw_data (me);
657 bu32 idx = DEC_SIC (my_port);
658 bu32 pin = DEC_PIN (my_port);
661 HW_TRACE ((me, "processing level %i from port %i (SIC %u pin %u)",
662 level, my_port, idx, pin));
664 /* SIC only exists to forward interrupts from the system to the CEC. */
667 case 0: bfin_sic_port_event (me, &sic->bf52x.isr0, bit, level); break;
668 case 1: bfin_sic_port_event (me, &sic->bf52x.isr1, bit, level); break;
671 /* XXX: Handle SIC wakeup source ?
672 if (sic->bf52x.iwr0 & bit)
674 if (sic->bf52x.iwr1 & bit)
678 bfin_sic_52x_forward_interrupts (me, sic);
682 bfin_sic_537_port_event (struct hw *me, int my_port, struct hw *source,
683 int source_port, int level)
685 struct bfin_sic *sic = hw_data (me);
686 bu32 idx = DEC_SIC (my_port);
687 bu32 pin = DEC_PIN (my_port);
690 HW_TRACE ((me, "processing level %i from port %i (SIC %u pin %u)",
691 level, my_port, idx, pin));
693 /* SIC only exists to forward interrupts from the system to the CEC. */
694 bfin_sic_port_event (me, &sic->bf537.isr, bit, level);
696 /* XXX: Handle SIC wakeup source ?
697 if (sic->bf537.iwr & bit)
701 bfin_sic_537_forward_interrupts (me, sic);
705 bfin_sic_54x_port_event (struct hw *me, int my_port, struct hw *source,
706 int source_port, int level)
708 struct bfin_sic *sic = hw_data (me);
709 bu32 idx = DEC_SIC (my_port);
710 bu32 pin = DEC_PIN (my_port);
713 HW_TRACE ((me, "processing level %i from port %i (SIC %u pin %u)",
714 level, my_port, idx, pin));
716 /* SIC only exists to forward interrupts from the system to the CEC. */
719 case 0: bfin_sic_port_event (me, &sic->bf54x.isr0, bit, level); break;
720 case 1: bfin_sic_port_event (me, &sic->bf54x.isr0, bit, level); break;
721 case 2: bfin_sic_port_event (me, &sic->bf54x.isr0, bit, level); break;
724 /* XXX: Handle SIC wakeup source ?
725 if (sic->bf54x.iwr0 & bit)
727 if (sic->bf54x.iwr1 & bit)
729 if (sic->bf54x.iwr2 & bit)
733 bfin_sic_54x_forward_interrupts (me, sic);
737 bfin_sic_561_port_event (struct hw *me, int my_port, struct hw *source,
738 int source_port, int level)
740 struct bfin_sic *sic = hw_data (me);
741 bu32 idx = DEC_SIC (my_port);
742 bu32 pin = DEC_PIN (my_port);
745 HW_TRACE ((me, "processing level %i from port %i (SIC %u pin %u)",
746 level, my_port, idx, pin));
748 /* SIC only exists to forward interrupts from the system to the CEC. */
751 case 0: bfin_sic_port_event (me, &sic->bf561.isr0, bit, level); break;
752 case 1: bfin_sic_port_event (me, &sic->bf561.isr1, bit, level); break;
755 /* XXX: Handle SIC wakeup source ?
756 if (sic->bf561.iwr0 & bit)
758 if (sic->bf561.iwr1 & bit)
762 bfin_sic_561_forward_interrupts (me, sic);
766 attach_bfin_sic_regs (struct hw *me, struct bfin_sic *sic)
768 address_word attach_address;
770 unsigned attach_size;
771 reg_property_spec reg;
773 if (hw_find_property (me, "reg") == NULL)
774 hw_abort (me, "Missing \"reg\" property");
776 if (!hw_find_reg_array_property (me, "reg", 0, ®))
777 hw_abort (me, "\"reg\" property must contain three addr/size entries");
779 hw_unit_address_to_attach_address (hw_parent (me),
781 &attach_space, &attach_address, me);
782 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
784 if (attach_size != BFIN_MMR_SIC_SIZE)
785 hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_SIC_SIZE);
787 hw_attach_address (hw_parent (me),
788 0, attach_space, attach_address, attach_size, me);
790 sic->base = attach_address;
794 bfin_sic_finish (struct hw *me)
796 struct bfin_sic *sic;
798 sic = HW_ZALLOC (me, struct bfin_sic);
800 set_hw_data (me, sic);
801 attach_bfin_sic_regs (me, sic);
803 switch (hw_find_integer_property (me, "type"))
806 set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
807 set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
808 set_hw_ports (me, bfin_sic2_ports);
809 set_hw_port_event (me, bfin_sic_52x_port_event);
810 mmr_names = bf52x_mmr_names;
812 /* Initialize the SIC. */
813 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
814 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
815 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
816 sic->bf52x.iar0 = 0x00000000;
817 sic->bf52x.iar1 = 0x22111000;
818 sic->bf52x.iar2 = 0x33332222;
819 sic->bf52x.iar3 = 0x44444433;
820 sic->bf52x.iar4 = 0x55555555;
821 sic->bf52x.iar5 = 0x06666655;
822 sic->bf52x.iar6 = 0x33333003;
823 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
826 set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
827 set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
828 set_hw_ports (me, bfin_sic2_ports);
829 set_hw_port_event (me, bfin_sic_52x_port_event);
830 mmr_names = bf52x_mmr_names;
832 /* Initialize the SIC. */
833 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
834 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
835 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
836 sic->bf52x.iar0 = 0x00000000;
837 sic->bf52x.iar1 = 0x11000000;
838 sic->bf52x.iar2 = 0x33332222;
839 sic->bf52x.iar3 = 0x44444433;
840 sic->bf52x.iar4 = 0x55555555;
841 sic->bf52x.iar5 = 0x06666655;
842 sic->bf52x.iar6 = 0x33333000;
843 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
846 set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
847 set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
848 set_hw_ports (me, bfin_sic2_ports);
849 set_hw_port_event (me, bfin_sic_52x_port_event);
850 mmr_names = bf52x_mmr_names;
852 /* Initialize the SIC. */
853 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
854 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
855 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
856 sic->bf52x.iar0 = 0x00000000;
857 sic->bf52x.iar1 = 0x11000000;
858 sic->bf52x.iar2 = 0x33332222;
859 sic->bf52x.iar3 = 0x44444433;
860 sic->bf52x.iar4 = 0x55555555;
861 sic->bf52x.iar5 = 0x06666655;
862 sic->bf52x.iar6 = 0x33333000;
863 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
866 set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
867 set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
868 set_hw_ports (me, bfin_sic1_ports);
869 set_hw_port_event (me, bfin_sic_537_port_event);
870 mmr_names = bf537_mmr_names;
872 /* Initialize the SIC. */
873 sic->bf537.imask = 0;
875 sic->bf537.iwr = 0xFFFFFFFF;
876 sic->bf537.iar0 = 0x10000000;
877 sic->bf537.iar1 = 0x33322221;
878 sic->bf537.iar2 = 0x66655444;
879 sic->bf537.iar3 = 0; /* XXX: fix this */
884 set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
885 set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
886 set_hw_ports (me, bfin_sic1_ports);
887 set_hw_port_event (me, bfin_sic_537_port_event);
888 mmr_names = bf537_mmr_names;
890 /* Initialize the SIC. */
891 sic->bf537.imask = 0;
893 sic->bf537.iwr = 0xFFFFFFFF;
894 sic->bf537.iar0 = 0x22211000;
895 sic->bf537.iar1 = 0x43333332;
896 sic->bf537.iar2 = 0x55555444;
897 sic->bf537.iar3 = 0x66655555;
900 set_hw_io_read_buffer (me, bfin_sic_52x_io_read_buffer);
901 set_hw_io_write_buffer (me, bfin_sic_52x_io_write_buffer);
902 set_hw_ports (me, bfin_sic2_ports);
903 set_hw_port_event (me, bfin_sic_52x_port_event);
904 mmr_names = bf52x_mmr_names;
906 /* Initialize the SIC. */
907 sic->bf52x.imask0 = sic->bf52x.imask1 = 0;
908 sic->bf52x.isr0 = sic->bf52x.isr1 = 0;
909 sic->bf52x.iwr0 = sic->bf52x.iwr1 = 0xFFFFFFFF;
910 sic->bf52x.iar0 = 0x10000000;
911 sic->bf52x.iar1 = 0x33322221;
912 sic->bf52x.iar2 = 0x66655444;
913 sic->bf52x.iar3 = 0x00000000;
914 sic->bf52x.iar4 = 0x32222220;
915 sic->bf52x.iar5 = 0x44433333;
916 sic->bf52x.iar6 = 0x00444664;
917 sic->bf52x.iar7 = 0x00000000; /* XXX: Find and fix */
920 set_hw_io_read_buffer (me, bfin_sic_54x_io_read_buffer);
921 set_hw_io_write_buffer (me, bfin_sic_54x_io_write_buffer);
922 set_hw_ports (me, bfin_sic3_ports);
923 set_hw_port_event (me, bfin_sic_54x_port_event);
924 mmr_names = bf54x_mmr_names;
926 /* Initialize the SIC. */
927 sic->bf54x.imask0 = sic->bf54x.imask1 = sic->bf54x.imask2 = 0;
928 sic->bf54x.isr0 = sic->bf54x.isr1 = sic->bf54x.isr2 = 0;
929 sic->bf54x.iwr0 = sic->bf54x.iwr1 = sic->bf54x.iwr2 = 0xFFFFFFFF;
930 sic->bf54x.iar0 = 0x10000000;
931 sic->bf54x.iar1 = 0x33322221;
932 sic->bf54x.iar2 = 0x66655444;
933 sic->bf54x.iar3 = 0x00000000;
934 sic->bf54x.iar4 = 0x32222220;
935 sic->bf54x.iar5 = 0x44433333;
936 sic->bf54x.iar6 = 0x00444664;
937 sic->bf54x.iar7 = 0x00000000;
938 sic->bf54x.iar8 = 0x44111111;
939 sic->bf54x.iar9 = 0x44444444;
940 sic->bf54x.iar10 = 0x44444444;
941 sic->bf54x.iar11 = 0x55444444;
944 set_hw_io_read_buffer (me, bfin_sic_561_io_read_buffer);
945 set_hw_io_write_buffer (me, bfin_sic_561_io_write_buffer);
946 set_hw_ports (me, bfin_sic_561_ports);
947 set_hw_port_event (me, bfin_sic_561_port_event);
948 mmr_names = bf561_mmr_names;
950 /* Initialize the SIC. */
951 sic->bf561.imask0 = sic->bf561.imask1 = 0;
952 sic->bf561.isr0 = sic->bf561.isr1 = 0;
953 sic->bf561.iwr0 = sic->bf561.iwr1 = 0xFFFFFFFF;
954 sic->bf561.iar0 = 0x00000000;
955 sic->bf561.iar1 = 0x11111000;
956 sic->bf561.iar2 = 0x21111111;
957 sic->bf561.iar3 = 0x22222222;
958 sic->bf561.iar4 = 0x33333222;
959 sic->bf561.iar5 = 0x43333333;
960 sic->bf561.iar6 = 0x21144444;
961 sic->bf561.iar7 = 0x00006552;
964 set_hw_io_read_buffer (me, bfin_sic_537_io_read_buffer);
965 set_hw_io_write_buffer (me, bfin_sic_537_io_write_buffer);
966 set_hw_ports (me, bfin_sic1_ports);
967 set_hw_port_event (me, bfin_sic_537_port_event);
968 mmr_names = bf537_mmr_names;
970 /* Initialize the SIC. */
971 sic->bf537.imask = 0;
973 sic->bf537.iwr = 0xFFFFFFFF;
974 sic->bf537.iar0 = 0x00000000;
975 sic->bf537.iar1 = 0x33322221;
976 sic->bf537.iar2 = 0x55444443;
977 sic->bf537.iar3 = 0x66600005;
980 hw_abort (me, "no support for SIC on this Blackfin model yet");
984 const struct hw_descriptor dv_bfin_sic_descriptor[] =
986 {"bfin_sic", bfin_sic_finish,},