1 /* Blackfin Core Timer model.
3 Copyright (C) 2010-2016 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "dv-bfin_cec.h"
26 #include "dv-bfin_ctimer.h"
31 struct hw_event *handler;
34 /* Order after here is important -- matches hardware MMR layout. */
35 bu32 tcntl, tperiod, tscale, tcount;
37 #define mmr_base() offsetof(struct bfin_ctimer, tcntl)
38 #define mmr_offset(mmr) (offsetof(struct bfin_ctimer, mmr) - mmr_base())
40 static const char * const mmr_names[] =
42 "TCNTL", "TPERIOD", "TSCALE", "TCOUNT",
44 #define mmr_name(off) mmr_names[(off) / 4]
47 bfin_ctimer_enabled (struct bfin_ctimer *ctimer)
49 return (ctimer->tcntl & TMPWR) && (ctimer->tcntl & TMREN);
53 bfin_ctimer_scale (struct bfin_ctimer *ctimer)
55 /* Only low 8 bits are actually checked. */
56 return (ctimer->tscale & 0xff) + 1;
60 bfin_ctimer_schedule (struct hw *me, struct bfin_ctimer *ctimer);
63 bfin_ctimer_expire (struct hw *me, void *data)
65 struct bfin_ctimer *ctimer = data;
67 ctimer->tcntl |= TINT;
68 if (ctimer->tcntl & TAUTORLD)
70 ctimer->tcount = ctimer->tperiod;
71 bfin_ctimer_schedule (me, ctimer);
76 ctimer->handler = NULL;
79 hw_port_event (me, IVG_IVTMR, 1);
83 bfin_ctimer_update_count (struct hw *me, struct bfin_ctimer *ctimer)
88 /* If the timer was enabled w/out autoreload and has expired, then
89 there's nothing to calculate here. */
90 if (ctimer->handler == NULL)
93 scale = bfin_ctimer_scale (ctimer);
94 timeout = hw_event_remain_time (me, ctimer->handler);
95 ticks = ctimer->timeout - timeout;
96 ctimer->tcount -= (scale * ticks);
97 ctimer->timeout = timeout;
101 bfin_ctimer_deschedule (struct hw *me, struct bfin_ctimer *ctimer)
105 hw_event_queue_deschedule (me, ctimer->handler);
106 ctimer->handler = NULL;
111 bfin_ctimer_schedule (struct hw *me, struct bfin_ctimer *ctimer)
113 bu32 scale = bfin_ctimer_scale (ctimer);
114 ctimer->timeout = (ctimer->tcount / scale) + !!(ctimer->tcount % scale);
115 ctimer->handler = hw_event_queue_schedule (me, ctimer->timeout,
121 bfin_ctimer_io_write_buffer (struct hw *me, const void *source,
122 int space, address_word addr, unsigned nr_bytes)
124 struct bfin_ctimer *ctimer = hw_data (me);
130 /* Invalid access mode is higher priority than missing register. */
131 if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
134 value = dv_load_4 (source);
135 mmr_off = addr - ctimer->base;
136 valuep = (void *)((unsigned long)ctimer + mmr_base() + mmr_off);
140 curr_enabled = bfin_ctimer_enabled (ctimer);
143 case mmr_offset(tcntl):
144 /* HRM describes TINT as sticky, but it isn't W1C. */
147 if (bfin_ctimer_enabled (ctimer) == curr_enabled)
151 else if (curr_enabled)
153 bfin_ctimer_update_count (me, ctimer);
154 bfin_ctimer_deschedule (me, ctimer);
157 bfin_ctimer_schedule (me, ctimer);
160 case mmr_offset(tcount):
161 /* HRM says writes are discarded when enabled. */
162 /* XXX: But hardware seems to be writeable all the time ? */
163 /* if (!curr_enabled) */
166 case mmr_offset(tperiod):
167 /* HRM says writes are discarded when enabled. */
168 /* XXX: But hardware seems to be writeable all the time ? */
169 /* if (!curr_enabled) */
171 /* Writes are mirrored into TCOUNT. */
172 ctimer->tcount = value;
176 case mmr_offset(tscale):
179 bfin_ctimer_update_count (me, ctimer);
180 bfin_ctimer_deschedule (me, ctimer);
184 bfin_ctimer_schedule (me, ctimer);
192 bfin_ctimer_io_read_buffer (struct hw *me, void *dest,
193 int space, address_word addr, unsigned nr_bytes)
195 struct bfin_ctimer *ctimer = hw_data (me);
199 /* Invalid access mode is higher priority than missing register. */
200 if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
203 mmr_off = addr - ctimer->base;
204 valuep = (void *)((unsigned long)ctimer + mmr_base() + mmr_off);
210 case mmr_offset(tcount):
211 /* Since we're optimizing events here, we need to calculate
212 the new tcount value. */
213 if (bfin_ctimer_enabled (ctimer))
214 bfin_ctimer_update_count (me, ctimer);
218 dv_store_4 (dest, *valuep);
223 static const struct hw_port_descriptor bfin_ctimer_ports[] =
225 { "ivtmr", IVG_IVTMR, 0, output_port, },
230 attach_bfin_ctimer_regs (struct hw *me, struct bfin_ctimer *ctimer)
232 address_word attach_address;
234 unsigned attach_size;
235 reg_property_spec reg;
237 if (hw_find_property (me, "reg") == NULL)
238 hw_abort (me, "Missing \"reg\" property");
240 if (!hw_find_reg_array_property (me, "reg", 0, ®))
241 hw_abort (me, "\"reg\" property must contain three addr/size entries");
243 hw_unit_address_to_attach_address (hw_parent (me),
245 &attach_space, &attach_address, me);
246 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
248 if (attach_size != BFIN_COREMMR_CTIMER_SIZE)
249 hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_CTIMER_SIZE);
251 hw_attach_address (hw_parent (me),
252 0, attach_space, attach_address, attach_size, me);
254 ctimer->base = attach_address;
258 bfin_ctimer_finish (struct hw *me)
260 struct bfin_ctimer *ctimer;
262 ctimer = HW_ZALLOC (me, struct bfin_ctimer);
264 set_hw_data (me, ctimer);
265 set_hw_io_read_buffer (me, bfin_ctimer_io_read_buffer);
266 set_hw_io_write_buffer (me, bfin_ctimer_io_write_buffer);
267 set_hw_ports (me, bfin_ctimer_ports);
269 attach_bfin_ctimer_regs (me, ctimer);
271 /* Initialize the Core Timer. */
274 const struct hw_descriptor dv_bfin_ctimer_descriptor[] =
276 {"bfin_ctimer", bfin_ctimer_finish,},