1 /* Blackfin Core Event Controller (CEC) model.
3 Copyright (C) 2010-2015 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "dv-bfin_cec.h"
26 #include "dv-bfin_evt.h"
27 #include "dv-bfin_mmu.h"
34 struct hw_event *pending;
36 /* Order after here is important -- matches hardware MMR layout. */
37 bu32 evt_override, imask, ipend, ilat, iprio;
39 #define mmr_base() offsetof(struct bfin_cec, evt_override)
40 #define mmr_offset(mmr) (offsetof(struct bfin_cec, mmr) - mmr_base())
42 static const char * const mmr_names[] =
44 "EVT_OVERRIDE", "IMASK", "IPEND", "ILAT", "IPRIO",
46 #define mmr_name(off) mmr_names[(off) / 4]
48 static void _cec_raise (SIM_CPU *, struct bfin_cec *, int);
51 bfin_cec_hw_event_callback (struct hw *me, void *data)
53 struct bfin_cec *cec = data;
54 hw_event_queue_deschedule (me, cec->pending);
55 _cec_raise (cec->cpu, cec, -1);
59 bfin_cec_check_pending (struct hw *me, struct bfin_cec *cec)
63 cec->pending = hw_event_queue_schedule (me, 0, bfin_cec_hw_event_callback, cec);
66 _cec_check_pending (SIM_CPU *cpu, struct bfin_cec *cec)
68 bfin_cec_check_pending (cec->me, cec);
72 _cec_imask_write (struct bfin_cec *cec, bu32 value)
74 cec->imask = (value & IVG_MASKABLE_B) | (cec->imask & IVG_UNMASKABLE_B);
78 bfin_cec_io_write_buffer (struct hw *me, const void *source,
79 int space, address_word addr, unsigned nr_bytes)
81 struct bfin_cec *cec = hw_data (me);
85 value = dv_load_4 (source);
86 mmr_off = addr - cec->base;
92 case mmr_offset(evt_override):
93 cec->evt_override = value;
95 case mmr_offset(imask):
96 _cec_imask_write (cec, value);
97 bfin_cec_check_pending (me, cec);
99 case mmr_offset(ipend):
100 /* Read-only register. */
102 case mmr_offset(ilat):
103 dv_w1c_4 (&cec->ilat, value, 0xffee);
105 case mmr_offset(iprio):
106 cec->iprio = (value & IVG_UNMASKABLE_B);
114 bfin_cec_io_read_buffer (struct hw *me, void *dest,
115 int space, address_word addr, unsigned nr_bytes)
117 struct bfin_cec *cec = hw_data (me);
121 mmr_off = addr - cec->base;
122 valuep = (void *)((unsigned long)cec + mmr_base() + mmr_off);
126 dv_store_4 (dest, *valuep);
131 static const struct hw_port_descriptor bfin_cec_ports[] =
133 { "emu", IVG_EMU, 0, input_port, },
134 { "rst", IVG_RST, 0, input_port, },
135 { "nmi", IVG_NMI, 0, input_port, },
136 { "evx", IVG_EVX, 0, input_port, },
137 { "ivhw", IVG_IVHW, 0, input_port, },
138 { "ivtmr", IVG_IVTMR, 0, input_port, },
139 { "ivg7", IVG7, 0, input_port, },
140 { "ivg8", IVG8, 0, input_port, },
141 { "ivg9", IVG9, 0, input_port, },
142 { "ivg10", IVG10, 0, input_port, },
143 { "ivg11", IVG11, 0, input_port, },
144 { "ivg12", IVG12, 0, input_port, },
145 { "ivg13", IVG13, 0, input_port, },
146 { "ivg14", IVG14, 0, input_port, },
147 { "ivg15", IVG15, 0, input_port, },
152 bfin_cec_port_event (struct hw *me, int my_port, struct hw *source,
153 int source_port, int level)
155 struct bfin_cec *cec = hw_data (me);
156 _cec_raise (cec->cpu, cec, my_port);
160 attach_bfin_cec_regs (struct hw *me, struct bfin_cec *cec)
162 address_word attach_address;
164 unsigned attach_size;
165 reg_property_spec reg;
167 if (hw_find_property (me, "reg") == NULL)
168 hw_abort (me, "Missing \"reg\" property");
170 if (!hw_find_reg_array_property (me, "reg", 0, ®))
171 hw_abort (me, "\"reg\" property must contain three addr/size entries");
173 hw_unit_address_to_attach_address (hw_parent (me),
175 &attach_space, &attach_address, me);
176 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
178 if (attach_size != BFIN_COREMMR_CEC_SIZE)
179 hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_CEC_SIZE);
181 hw_attach_address (hw_parent (me),
182 0, attach_space, attach_address, attach_size, me);
184 cec->base = attach_address;
185 /* XXX: should take from the device tree. */
186 cec->cpu = STATE_CPU (hw_system (me), 0);
191 bfin_cec_finish (struct hw *me)
193 struct bfin_cec *cec;
195 cec = HW_ZALLOC (me, struct bfin_cec);
197 set_hw_data (me, cec);
198 set_hw_io_read_buffer (me, bfin_cec_io_read_buffer);
199 set_hw_io_write_buffer (me, bfin_cec_io_write_buffer);
200 set_hw_ports (me, bfin_cec_ports);
201 set_hw_port_event (me, bfin_cec_port_event);
203 attach_bfin_cec_regs (me, cec);
205 /* Initialize the CEC. */
206 cec->imask = IVG_UNMASKABLE_B;
207 cec->ipend = IVG_RST_B | IVG_IRPTEN_B;
210 const struct hw_descriptor dv_bfin_cec_descriptor[] =
212 {"bfin_cec", bfin_cec_finish,},
216 static const char * const excp_decoded[] =
218 [VEC_SYS ] = "Custom exception 0 (system call)",
219 [VEC_EXCPT01 ] = "Custom exception 1 (software breakpoint)",
220 [VEC_EXCPT02 ] = "Custom exception 2 (KGDB hook)",
221 [VEC_EXCPT03 ] = "Custom exception 3 (userspace stack overflow)",
222 [VEC_EXCPT04 ] = "Custom exception 4 (dump trace buffer)",
223 [VEC_EXCPT05 ] = "Custom exception 5",
224 [VEC_EXCPT06 ] = "Custom exception 6",
225 [VEC_EXCPT07 ] = "Custom exception 7",
226 [VEC_EXCPT08 ] = "Custom exception 8",
227 [VEC_EXCPT09 ] = "Custom exception 9",
228 [VEC_EXCPT10 ] = "Custom exception 10",
229 [VEC_EXCPT11 ] = "Custom exception 11",
230 [VEC_EXCPT12 ] = "Custom exception 12",
231 [VEC_EXCPT13 ] = "Custom exception 13",
232 [VEC_EXCPT14 ] = "Custom exception 14",
233 [VEC_EXCPT15 ] = "Custom exception 15",
234 [VEC_STEP ] = "Hardware single step",
235 [VEC_OVFLOW ] = "Trace buffer overflow",
236 [VEC_UNDEF_I ] = "Undefined instruction",
237 [VEC_ILGAL_I ] = "Illegal instruction combo (multi-issue)",
238 [VEC_CPLB_VL ] = "DCPLB protection violation",
239 [VEC_MISALI_D ] = "Unaligned data access",
240 [VEC_UNCOV ] = "Unrecoverable event (double fault)",
241 [VEC_CPLB_M ] = "DCPLB miss",
242 [VEC_CPLB_MHIT ] = "Multiple DCPLB hit",
243 [VEC_WATCH ] = "Watchpoint match",
244 [VEC_ISTRU_VL ] = "ADSP-BF535 only",
245 [VEC_MISALI_I ] = "Unaligned instruction access",
246 [VEC_CPLB_I_VL ] = "ICPLB protection violation",
247 [VEC_CPLB_I_M ] = "ICPLB miss",
248 [VEC_CPLB_I_MHIT] = "Multiple ICPLB hit",
249 [VEC_ILL_RES ] = "Illegal supervisor resource",
252 #define CEC_STATE(cpu) DV_STATE_CACHED (cpu, cec)
254 #define __cec_get_ivg(val) (ffs ((val) & ~IVG_IRPTEN_B) - 1)
255 #define _cec_get_ivg(cec) __cec_get_ivg ((cec)->ipend & ~IVG_EMU_B)
258 cec_get_ivg (SIM_CPU *cpu)
260 switch (STATE_ENVIRONMENT (CPU_STATE (cpu)))
262 case OPERATING_ENVIRONMENT:
263 return _cec_get_ivg (CEC_STATE (cpu));
270 _cec_is_supervisor_mode (struct bfin_cec *cec)
272 return (cec->ipend & ~(IVG_EMU_B | IVG_IRPTEN_B));
275 cec_is_supervisor_mode (SIM_CPU *cpu)
277 switch (STATE_ENVIRONMENT (CPU_STATE (cpu)))
279 case OPERATING_ENVIRONMENT:
280 return _cec_is_supervisor_mode (CEC_STATE (cpu));
281 case USER_ENVIRONMENT:
288 _cec_is_user_mode (struct bfin_cec *cec)
290 return !_cec_is_supervisor_mode (cec);
293 cec_is_user_mode (SIM_CPU *cpu)
295 return !cec_is_supervisor_mode (cpu);
298 _cec_require_supervisor (SIM_CPU *cpu, struct bfin_cec *cec)
300 if (_cec_is_user_mode (cec))
301 cec_exception (cpu, VEC_ILL_RES);
304 cec_require_supervisor (SIM_CPU *cpu)
306 /* Do not call _cec_require_supervisor() to avoid CEC_STATE()
307 as that macro requires OS operating mode. */
308 if (cec_is_user_mode (cpu))
309 cec_exception (cpu, VEC_ILL_RES);
312 #define excp_to_sim_halt(reason, sigrc) \
313 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, PCREG, reason, sigrc)
315 cec_exception (SIM_CPU *cpu, int excp)
317 SIM_DESC sd = CPU_STATE (cpu);
320 TRACE_EVENTS (cpu, "processing exception %#x in EVT%i", excp,
323 /* Ideally what would happen here for real hardware exceptions (not
324 fake sim ones) is that:
325 - For service exceptions (excp <= 0x11):
326 RETX is the _next_ PC which can be tricky with jumps/hardware loops/...
327 - For error exceptions (excp > 0x11):
328 RETX is the _current_ PC (i.e. the one causing the exception)
329 - PC is loaded with EVT3 MMR
330 - ILAT/IPEND in CEC is updated depending on current IVG level
331 - the fault address MMRs get updated with data/instruction info
332 - Execution continues on in the EVT3 handler */
334 /* Handle simulator exceptions first. */
338 excp_to_sim_halt (sim_exited, 0);
341 excp_to_sim_halt (sim_exited, 1);
344 /* GDB expects us to step over EMUEXCPT. */
345 /* XXX: What about hwloops and EMUEXCPT at the end?
346 Pretty sure gdb doesn't handle this already... */
347 SET_PCREG (PCREG + 2);
348 /* Only trap when we are running in gdb. */
349 if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG)
350 excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
353 /* If running in gdb, simply trap. */
354 if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG)
355 excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
357 excp_to_sim_halt (sim_exited, 2);
363 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
365 /* ICPLB regs always get updated. */
366 /* XXX: Should optimize this call path ... */
367 if (excp != VEC_MISALI_I && excp != VEC_MISALI_D
368 && excp != VEC_CPLB_I_M && excp != VEC_CPLB_M
369 && excp != VEC_CPLB_I_VL && excp != VEC_CPLB_VL
370 && excp != VEC_CPLB_I_MHIT && excp != VEC_CPLB_MHIT)
371 mmu_log_ifault (cpu);
372 _cec_raise (cpu, CEC_STATE (cpu), IVG_EVX);
373 /* We need to restart the engine so that we don't return
374 and continue processing this bad insn. */
376 sim_engine_restart (sd, cpu, NULL, PCREG);
381 TRACE_EVENTS (cpu, "running virtual exception handler");
389 case VEC_EXCPT01: /* Userspace gdb breakpoint. */
393 case VEC_UNDEF_I: /* Undefined instruction. */
397 case VEC_ILL_RES: /* Illegal supervisor resource. */
398 case VEC_MISALI_I: /* Misaligned instruction. */
408 sim_io_eprintf (sd, "Unhandled exception %#x at 0x%08x (%s)\n",
409 excp, PCREG, excp_decoded[excp]);
415 excp_to_sim_halt (sim_stopped, sigrc);
418 bu32 cec_cli (SIM_CPU *cpu)
420 struct bfin_cec *cec;
423 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
426 cec = CEC_STATE (cpu);
427 _cec_require_supervisor (cpu, cec);
429 /* XXX: what about IPEND[4] ? */
430 old_mask = cec->imask;
431 _cec_imask_write (cec, 0);
433 TRACE_EVENTS (cpu, "CLI changed IMASK from %#x to %#x", old_mask, cec->imask);
438 void cec_sti (SIM_CPU *cpu, bu32 ints)
440 struct bfin_cec *cec;
443 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
446 cec = CEC_STATE (cpu);
447 _cec_require_supervisor (cpu, cec);
449 /* XXX: what about IPEND[4] ? */
450 old_mask = cec->imask;
451 _cec_imask_write (cec, ints);
453 TRACE_EVENTS (cpu, "STI changed IMASK from %#x to %#x", old_mask, cec->imask);
455 /* Check for pending interrupts that are now enabled. */
456 _cec_check_pending (cpu, cec);
460 cec_irpten_enable (SIM_CPU *cpu, struct bfin_cec *cec)
462 /* Globally mask interrupts. */
463 TRACE_EVENTS (cpu, "setting IPEND[4] to globally mask interrupts");
464 cec->ipend |= IVG_IRPTEN_B;
468 cec_irpten_disable (SIM_CPU *cpu, struct bfin_cec *cec)
470 /* Clear global interrupt mask. */
471 TRACE_EVENTS (cpu, "clearing IPEND[4] to not globally mask interrupts");
472 cec->ipend &= ~IVG_IRPTEN_B;
476 _cec_raise (SIM_CPU *cpu, struct bfin_cec *cec, int ivg)
478 SIM_DESC sd = CPU_STATE (cpu);
479 int curr_ivg = _cec_get_ivg (cec);
483 TRACE_EVENTS (cpu, "processing request for EVT%i while at EVT%i",
486 irpten = (cec->ipend & IVG_IRPTEN_B);
487 snen = (SYSCFGREG & SYSCFG_SNEN);
492 /* Just check for higher latched interrupts. */
496 goto done; /* All interrupts are masked anyways. */
498 ivg = __cec_get_ivg (cec->ilat & cec->imask);
500 goto done; /* Nothing latched. */
503 goto done; /* Nothing higher latched. */
505 if (!snen && ivg == curr_ivg)
506 goto done; /* Self nesting disabled. */
508 /* Still here, so fall through to raise to higher pending. */
511 cec->ilat |= (1 << ivg);
515 /* These two are always processed. */
516 if (ivg == IVG_EMU || ivg == IVG_RST)
519 /* Anything lower might trigger a double fault. */
522 /* Double fault ! :( */
523 SET_EXCAUSE (VEC_UNCOV);
524 /* XXX: SET_RETXREG (...); */
525 sim_io_error (sd, "%s: double fault at 0x%08x ! :(", __func__, PCREG);
526 excp_to_sim_halt (sim_stopped, SIM_SIGABRT);
529 /* No double fault -> always process. */
532 else if (irpten && curr_ivg != IVG_USER)
534 /* Interrupts are globally masked. */
536 else if (!(cec->imask & (1 << ivg)))
538 /* This interrupt is masked. */
540 else if (ivg < curr_ivg || (snen && ivg == curr_ivg))
546 cec->ipend |= (1 << ivg);
547 cec->ilat &= ~(1 << ivg);
549 /* Interrupts are processed in between insns which means the return
550 point is the insn-to-be-executed (which is the current PC). But
551 exceptions are handled while executing an insn, so we may have to
552 advance the PC ourselves when setting RETX.
553 XXX: Advancing the PC should only be for "service" exceptions, and
554 handling them after executing the insn should be OK, which
555 means we might be able to use the event interface for it. */
561 /* Signal the JTAG ICE. */
562 /* XXX: what happens with 'raise 0' ? */
564 excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
565 /* XXX: Need an easy way for gdb to signal it isnt here. */
566 cec->ipend &= ~IVG_EMU_B;
569 /* Have the core reset simply exit (i.e. "shutdown"). */
570 excp_to_sim_halt (sim_exited, 0);
573 /* XXX: Should check this. */
577 /* Non-service exceptions point to the excepting instruction. */
582 bu32 nextpc = hwloop_get_next_pc (cpu, oldpc, INSN_LEN);
583 SET_RETXREG (nextpc);
588 /* XXX: what happens with 'raise 4' ? */
589 sim_io_error (sd, "%s: what to do with 'raise 4' ?", __func__);
592 SET_RETIREG (oldpc | (ivg == curr_ivg ? 1 : 0));
596 /* If EVT_OVERRIDE is in effect (IVG7+), use the reset address. */
597 if ((cec->evt_override & 0xff80) & (1 << ivg))
598 SET_PCREG (cec_get_reset_evt (cpu));
600 SET_PCREG (cec_get_evt (cpu, ivg));
602 TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC (to EVT%i):", ivg);
603 BFIN_CPU_STATE.did_jump = true;
605 /* Enable the global interrupt mask upon interrupt entry. */
607 cec_irpten_enable (cpu, cec);
610 /* When moving between states, don't let internal states bleed through. */
613 /* When going from user to super, we set LSB in LB regs to avoid
614 misbehavior and/or malicious code.
615 Also need to load SP alias with KSP. */
616 if (curr_ivg == IVG_USER)
619 for (i = 0; i < 2; ++i)
620 if (!(LBREG (i) & 1))
621 SET_LBREG (i, LBREG (i) | 1);
627 TRACE_EVENTS (cpu, "now at EVT%i", _cec_get_ivg (cec));
631 cec_read_ret_reg (SIM_CPU *cpu, int ivg)
635 case IVG_EMU: return RETEREG;
636 case IVG_NMI: return RETNREG;
637 case IVG_EVX: return RETXREG;
638 default: return RETIREG;
643 cec_latch (SIM_CPU *cpu, int ivg)
645 struct bfin_cec *cec;
647 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
650 SET_PCREG (cec_read_ret_reg (cpu, ivg));
651 TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC");
655 cec = CEC_STATE (cpu);
656 cec->ilat |= (1 << ivg);
657 _cec_check_pending (cpu, cec);
661 cec_hwerr (SIM_CPU *cpu, int hwerr)
663 SET_HWERRCAUSE (hwerr);
664 cec_latch (cpu, IVG_IVHW);
668 cec_return (SIM_CPU *cpu, int ivg)
670 SIM_DESC sd = CPU_STATE (cpu);
671 struct bfin_cec *cec;
678 BFIN_CPU_STATE.did_jump = true;
679 if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
681 SET_PCREG (cec_read_ret_reg (cpu, ivg));
682 TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC");
686 cec = CEC_STATE (cpu);
688 /* XXX: This isn't entirely correct ... */
689 cec->ipend &= ~IVG_EMU_B;
691 curr_ivg = _cec_get_ivg (cec);
697 TRACE_EVENTS (cpu, "returning from EVT%i (should be EVT%i)", curr_ivg, ivg);
699 /* Not allowed to return from usermode. */
700 if (curr_ivg == IVG_USER)
701 cec_exception (cpu, VEC_ILL_RES);
703 if (ivg > IVG15 || ivg < 0)
704 sim_io_error (sd, "%s: ivg %i out of range !", __func__, ivg);
706 _cec_require_supervisor (cpu, cec);
711 /* RTE -- only valid in emulation mode. */
712 /* XXX: What does the hardware do ? */
713 if (curr_ivg != IVG_EMU)
714 cec_exception (cpu, VEC_ILL_RES);
717 /* RTN -- only valid in NMI. */
718 /* XXX: What does the hardware do ? */
719 if (curr_ivg != IVG_NMI)
720 cec_exception (cpu, VEC_ILL_RES);
723 /* RTX -- only valid in exception. */
724 /* XXX: What does the hardware do ? */
725 if (curr_ivg != IVG_EVX)
726 cec_exception (cpu, VEC_ILL_RES);
729 /* RTI -- not valid in emulation, nmi, exception, or user. */
730 /* XXX: What does the hardware do ? */
731 if (curr_ivg == IVG_EMU || curr_ivg == IVG_NMI
732 || curr_ivg == IVG_EVX || curr_ivg == IVG_USER)
733 cec_exception (cpu, VEC_ILL_RES);
736 /* XXX: Is this even possible ? */
737 excp_to_sim_halt (sim_stopped, SIM_SIGABRT);
740 newpc = cec_read_ret_reg (cpu, ivg);
742 /* XXX: Does this nested trick work on EMU/NMI/EVX ? */
744 /* XXX: Delayed clear shows bad PCREG register trace above ? */
745 SET_PCREG (newpc & ~1);
747 TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC (from EVT%i)", ivg);
749 /* Update ipend after the TRACE_BRANCH so dv-bfin_trace
750 knows current CEC state wrt overflow. */
752 cec->ipend &= ~(1 << ivg);
754 /* Disable global interrupt mask to let any interrupt take over, but
755 only when we were already in a RTI level. Only way we could have
756 raised at that point is if it was cleared in the first place. */
757 if (ivg >= IVG_IVHW || ivg == IVG_RST)
758 cec_irpten_disable (cpu, cec);
760 /* When going from super to user, we clear LSB in LB regs in case
761 it was set on the transition up.
762 Also need to load SP alias with USP. */
763 if (_cec_get_ivg (cec) == -1)
766 for (i = 0; i < 2; ++i)
768 SET_LBREG (i, LBREG (i) & ~1);
773 /* Check for pending interrupts before we return to usermode. */
774 _cec_check_pending (cpu, cec);
778 cec_push_reti (SIM_CPU *cpu)
780 /* XXX: Need to check hardware with popped RETI value
781 and bit 1 is set (when handling nested interrupts).
782 Also need to check behavior wrt SNEN in SYSCFG. */
783 struct bfin_cec *cec;
785 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
788 TRACE_EVENTS (cpu, "pushing RETI");
790 cec = CEC_STATE (cpu);
791 cec_irpten_disable (cpu, cec);
792 /* Check for pending interrupts. */
793 _cec_check_pending (cpu, cec);
797 cec_pop_reti (SIM_CPU *cpu)
799 /* XXX: Need to check hardware with popped RETI value
800 and bit 1 is set (when handling nested interrupts).
801 Also need to check behavior wrt SNEN in SYSCFG. */
802 struct bfin_cec *cec;
804 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
807 TRACE_EVENTS (cpu, "popping RETI");
809 cec = CEC_STATE (cpu);
810 cec_irpten_enable (cpu, cec);