1 /* Blackfin Core Event Controller (CEC) model.
3 Copyright (C) 2010-2016 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "dv-bfin_cec.h"
26 #include "dv-bfin_evt.h"
27 #include "dv-bfin_mmu.h"
34 struct hw_event *pending;
36 /* Order after here is important -- matches hardware MMR layout. */
37 bu32 evt_override, imask, ipend, ilat, iprio;
39 #define mmr_base() offsetof(struct bfin_cec, evt_override)
40 #define mmr_offset(mmr) (offsetof(struct bfin_cec, mmr) - mmr_base())
42 static const char * const mmr_names[] =
44 "EVT_OVERRIDE", "IMASK", "IPEND", "ILAT", "IPRIO",
46 #define mmr_name(off) mmr_names[(off) / 4]
48 static void _cec_raise (SIM_CPU *, struct bfin_cec *, int);
51 bfin_cec_hw_event_callback (struct hw *me, void *data)
53 struct bfin_cec *cec = data;
54 hw_event_queue_deschedule (me, cec->pending);
55 _cec_raise (cec->cpu, cec, -1);
59 bfin_cec_check_pending (struct hw *me, struct bfin_cec *cec)
63 cec->pending = hw_event_queue_schedule (me, 0, bfin_cec_hw_event_callback, cec);
66 _cec_check_pending (SIM_CPU *cpu, struct bfin_cec *cec)
68 bfin_cec_check_pending (cec->me, cec);
72 _cec_imask_write (struct bfin_cec *cec, bu32 value)
74 cec->imask = (value & IVG_MASKABLE_B) | (cec->imask & IVG_UNMASKABLE_B);
78 bfin_cec_io_write_buffer (struct hw *me, const void *source,
79 int space, address_word addr, unsigned nr_bytes)
81 struct bfin_cec *cec = hw_data (me);
85 /* Invalid access mode is higher priority than missing register. */
86 if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
89 value = dv_load_4 (source);
90 mmr_off = addr - cec->base;
96 case mmr_offset(evt_override):
97 cec->evt_override = value;
99 case mmr_offset(imask):
100 _cec_imask_write (cec, value);
101 bfin_cec_check_pending (me, cec);
103 case mmr_offset(ipend):
104 /* Read-only register. */
106 case mmr_offset(ilat):
107 dv_w1c_4 (&cec->ilat, value, 0xffee);
109 case mmr_offset(iprio):
110 cec->iprio = (value & IVG_UNMASKABLE_B);
118 bfin_cec_io_read_buffer (struct hw *me, void *dest,
119 int space, address_word addr, unsigned nr_bytes)
121 struct bfin_cec *cec = hw_data (me);
125 /* Invalid access mode is higher priority than missing register. */
126 if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
129 mmr_off = addr - cec->base;
130 valuep = (void *)((unsigned long)cec + mmr_base() + mmr_off);
134 dv_store_4 (dest, *valuep);
139 static const struct hw_port_descriptor bfin_cec_ports[] =
141 { "emu", IVG_EMU, 0, input_port, },
142 { "rst", IVG_RST, 0, input_port, },
143 { "nmi", IVG_NMI, 0, input_port, },
144 { "evx", IVG_EVX, 0, input_port, },
145 { "ivhw", IVG_IVHW, 0, input_port, },
146 { "ivtmr", IVG_IVTMR, 0, input_port, },
147 { "ivg7", IVG7, 0, input_port, },
148 { "ivg8", IVG8, 0, input_port, },
149 { "ivg9", IVG9, 0, input_port, },
150 { "ivg10", IVG10, 0, input_port, },
151 { "ivg11", IVG11, 0, input_port, },
152 { "ivg12", IVG12, 0, input_port, },
153 { "ivg13", IVG13, 0, input_port, },
154 { "ivg14", IVG14, 0, input_port, },
155 { "ivg15", IVG15, 0, input_port, },
160 bfin_cec_port_event (struct hw *me, int my_port, struct hw *source,
161 int source_port, int level)
163 struct bfin_cec *cec = hw_data (me);
164 _cec_raise (cec->cpu, cec, my_port);
168 attach_bfin_cec_regs (struct hw *me, struct bfin_cec *cec)
170 address_word attach_address;
172 unsigned attach_size;
173 reg_property_spec reg;
175 if (hw_find_property (me, "reg") == NULL)
176 hw_abort (me, "Missing \"reg\" property");
178 if (!hw_find_reg_array_property (me, "reg", 0, ®))
179 hw_abort (me, "\"reg\" property must contain three addr/size entries");
181 hw_unit_address_to_attach_address (hw_parent (me),
183 &attach_space, &attach_address, me);
184 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
186 if (attach_size != BFIN_COREMMR_CEC_SIZE)
187 hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_CEC_SIZE);
189 hw_attach_address (hw_parent (me),
190 0, attach_space, attach_address, attach_size, me);
192 cec->base = attach_address;
193 /* XXX: should take from the device tree. */
194 cec->cpu = STATE_CPU (hw_system (me), 0);
199 bfin_cec_finish (struct hw *me)
201 struct bfin_cec *cec;
203 cec = HW_ZALLOC (me, struct bfin_cec);
205 set_hw_data (me, cec);
206 set_hw_io_read_buffer (me, bfin_cec_io_read_buffer);
207 set_hw_io_write_buffer (me, bfin_cec_io_write_buffer);
208 set_hw_ports (me, bfin_cec_ports);
209 set_hw_port_event (me, bfin_cec_port_event);
211 attach_bfin_cec_regs (me, cec);
213 /* Initialize the CEC. */
214 cec->imask = IVG_UNMASKABLE_B;
215 cec->ipend = IVG_RST_B | IVG_IRPTEN_B;
218 const struct hw_descriptor dv_bfin_cec_descriptor[] =
220 {"bfin_cec", bfin_cec_finish,},
224 static const char * const excp_decoded[] =
226 [VEC_SYS ] = "Custom exception 0 (system call)",
227 [VEC_EXCPT01 ] = "Custom exception 1 (software breakpoint)",
228 [VEC_EXCPT02 ] = "Custom exception 2 (KGDB hook)",
229 [VEC_EXCPT03 ] = "Custom exception 3 (userspace stack overflow)",
230 [VEC_EXCPT04 ] = "Custom exception 4 (dump trace buffer)",
231 [VEC_EXCPT05 ] = "Custom exception 5",
232 [VEC_EXCPT06 ] = "Custom exception 6",
233 [VEC_EXCPT07 ] = "Custom exception 7",
234 [VEC_EXCPT08 ] = "Custom exception 8",
235 [VEC_EXCPT09 ] = "Custom exception 9",
236 [VEC_EXCPT10 ] = "Custom exception 10",
237 [VEC_EXCPT11 ] = "Custom exception 11",
238 [VEC_EXCPT12 ] = "Custom exception 12",
239 [VEC_EXCPT13 ] = "Custom exception 13",
240 [VEC_EXCPT14 ] = "Custom exception 14",
241 [VEC_EXCPT15 ] = "Custom exception 15",
242 [VEC_STEP ] = "Hardware single step",
243 [VEC_OVFLOW ] = "Trace buffer overflow",
244 [VEC_UNDEF_I ] = "Undefined instruction",
245 [VEC_ILGAL_I ] = "Illegal instruction combo (multi-issue)",
246 [VEC_CPLB_VL ] = "DCPLB protection violation",
247 [VEC_MISALI_D ] = "Unaligned data access",
248 [VEC_UNCOV ] = "Unrecoverable event (double fault)",
249 [VEC_CPLB_M ] = "DCPLB miss",
250 [VEC_CPLB_MHIT ] = "Multiple DCPLB hit",
251 [VEC_WATCH ] = "Watchpoint match",
252 [VEC_ISTRU_VL ] = "ADSP-BF535 only",
253 [VEC_MISALI_I ] = "Unaligned instruction access",
254 [VEC_CPLB_I_VL ] = "ICPLB protection violation",
255 [VEC_CPLB_I_M ] = "ICPLB miss",
256 [VEC_CPLB_I_MHIT] = "Multiple ICPLB hit",
257 [VEC_ILL_RES ] = "Illegal supervisor resource",
260 #define CEC_STATE(cpu) DV_STATE_CACHED (cpu, cec)
262 #define __cec_get_ivg(val) (ffs ((val) & ~IVG_IRPTEN_B) - 1)
263 #define _cec_get_ivg(cec) __cec_get_ivg ((cec)->ipend & ~IVG_EMU_B)
266 cec_get_ivg (SIM_CPU *cpu)
268 switch (STATE_ENVIRONMENT (CPU_STATE (cpu)))
270 case OPERATING_ENVIRONMENT:
271 return _cec_get_ivg (CEC_STATE (cpu));
278 _cec_is_supervisor_mode (struct bfin_cec *cec)
280 return (cec->ipend & ~(IVG_EMU_B | IVG_IRPTEN_B));
283 cec_is_supervisor_mode (SIM_CPU *cpu)
285 switch (STATE_ENVIRONMENT (CPU_STATE (cpu)))
287 case OPERATING_ENVIRONMENT:
288 return _cec_is_supervisor_mode (CEC_STATE (cpu));
289 case USER_ENVIRONMENT:
296 _cec_is_user_mode (struct bfin_cec *cec)
298 return !_cec_is_supervisor_mode (cec);
301 cec_is_user_mode (SIM_CPU *cpu)
303 return !cec_is_supervisor_mode (cpu);
306 _cec_require_supervisor (SIM_CPU *cpu, struct bfin_cec *cec)
308 if (_cec_is_user_mode (cec))
309 cec_exception (cpu, VEC_ILL_RES);
312 cec_require_supervisor (SIM_CPU *cpu)
314 /* Do not call _cec_require_supervisor() to avoid CEC_STATE()
315 as that macro requires OS operating mode. */
316 if (cec_is_user_mode (cpu))
317 cec_exception (cpu, VEC_ILL_RES);
320 #define excp_to_sim_halt(reason, sigrc) \
321 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, PCREG, reason, sigrc)
323 cec_exception (SIM_CPU *cpu, int excp)
325 SIM_DESC sd = CPU_STATE (cpu);
328 TRACE_EVENTS (cpu, "processing exception %#x in EVT%i", excp,
331 /* Ideally what would happen here for real hardware exceptions (not
332 fake sim ones) is that:
333 - For service exceptions (excp <= 0x11):
334 RETX is the _next_ PC which can be tricky with jumps/hardware loops/...
335 - For error exceptions (excp > 0x11):
336 RETX is the _current_ PC (i.e. the one causing the exception)
337 - PC is loaded with EVT3 MMR
338 - ILAT/IPEND in CEC is updated depending on current IVG level
339 - the fault address MMRs get updated with data/instruction info
340 - Execution continues on in the EVT3 handler */
342 /* Handle simulator exceptions first. */
346 excp_to_sim_halt (sim_exited, 0);
349 excp_to_sim_halt (sim_exited, 1);
352 /* GDB expects us to step over EMUEXCPT. */
353 /* XXX: What about hwloops and EMUEXCPT at the end?
354 Pretty sure gdb doesn't handle this already... */
355 SET_PCREG (PCREG + 2);
356 /* Only trap when we are running in gdb. */
357 if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG)
358 excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
361 /* If running in gdb, simply trap. */
362 if (STATE_OPEN_KIND (sd) == SIM_OPEN_DEBUG)
363 excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
365 excp_to_sim_halt (sim_exited, 2);
371 if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
373 /* ICPLB regs always get updated. */
374 /* XXX: Should optimize this call path ... */
375 if (excp != VEC_MISALI_I && excp != VEC_MISALI_D
376 && excp != VEC_CPLB_I_M && excp != VEC_CPLB_M
377 && excp != VEC_CPLB_I_VL && excp != VEC_CPLB_VL
378 && excp != VEC_CPLB_I_MHIT && excp != VEC_CPLB_MHIT)
379 mmu_log_ifault (cpu);
380 _cec_raise (cpu, CEC_STATE (cpu), IVG_EVX);
381 /* We need to restart the engine so that we don't return
382 and continue processing this bad insn. */
384 sim_engine_restart (sd, cpu, NULL, PCREG);
389 TRACE_EVENTS (cpu, "running virtual exception handler");
397 case VEC_EXCPT01: /* Userspace gdb breakpoint. */
401 case VEC_UNDEF_I: /* Undefined instruction. */
405 case VEC_ILL_RES: /* Illegal supervisor resource. */
406 case VEC_MISALI_I: /* Misaligned instruction. */
416 sim_io_eprintf (sd, "Unhandled exception %#x at 0x%08x (%s)\n",
417 excp, PCREG, excp_decoded[excp]);
423 excp_to_sim_halt (sim_stopped, sigrc);
426 bu32 cec_cli (SIM_CPU *cpu)
428 struct bfin_cec *cec;
431 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
434 cec = CEC_STATE (cpu);
435 _cec_require_supervisor (cpu, cec);
437 /* XXX: what about IPEND[4] ? */
438 old_mask = cec->imask;
439 _cec_imask_write (cec, 0);
441 TRACE_EVENTS (cpu, "CLI changed IMASK from %#x to %#x", old_mask, cec->imask);
446 void cec_sti (SIM_CPU *cpu, bu32 ints)
448 struct bfin_cec *cec;
451 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
454 cec = CEC_STATE (cpu);
455 _cec_require_supervisor (cpu, cec);
457 /* XXX: what about IPEND[4] ? */
458 old_mask = cec->imask;
459 _cec_imask_write (cec, ints);
461 TRACE_EVENTS (cpu, "STI changed IMASK from %#x to %#x", old_mask, cec->imask);
463 /* Check for pending interrupts that are now enabled. */
464 _cec_check_pending (cpu, cec);
468 cec_irpten_enable (SIM_CPU *cpu, struct bfin_cec *cec)
470 /* Globally mask interrupts. */
471 TRACE_EVENTS (cpu, "setting IPEND[4] to globally mask interrupts");
472 cec->ipend |= IVG_IRPTEN_B;
476 cec_irpten_disable (SIM_CPU *cpu, struct bfin_cec *cec)
478 /* Clear global interrupt mask. */
479 TRACE_EVENTS (cpu, "clearing IPEND[4] to not globally mask interrupts");
480 cec->ipend &= ~IVG_IRPTEN_B;
484 _cec_raise (SIM_CPU *cpu, struct bfin_cec *cec, int ivg)
486 SIM_DESC sd = CPU_STATE (cpu);
487 int curr_ivg = _cec_get_ivg (cec);
491 TRACE_EVENTS (cpu, "processing request for EVT%i while at EVT%i",
494 irpten = (cec->ipend & IVG_IRPTEN_B);
495 snen = (SYSCFGREG & SYSCFG_SNEN);
500 /* Just check for higher latched interrupts. */
504 goto done; /* All interrupts are masked anyways. */
506 ivg = __cec_get_ivg (cec->ilat & cec->imask);
508 goto done; /* Nothing latched. */
511 goto done; /* Nothing higher latched. */
513 if (!snen && ivg == curr_ivg)
514 goto done; /* Self nesting disabled. */
516 /* Still here, so fall through to raise to higher pending. */
519 cec->ilat |= (1 << ivg);
523 /* These two are always processed. */
524 if (ivg == IVG_EMU || ivg == IVG_RST)
527 /* Anything lower might trigger a double fault. */
530 /* Double fault ! :( */
531 SET_EXCAUSE (VEC_UNCOV);
532 /* XXX: SET_RETXREG (...); */
533 sim_io_error (sd, "%s: double fault at 0x%08x ! :(", __func__, PCREG);
534 excp_to_sim_halt (sim_stopped, SIM_SIGABRT);
537 /* No double fault -> always process. */
540 else if (irpten && curr_ivg != IVG_USER)
542 /* Interrupts are globally masked. */
544 else if (!(cec->imask & (1 << ivg)))
546 /* This interrupt is masked. */
548 else if (ivg < curr_ivg || (snen && ivg == curr_ivg))
554 cec->ipend |= (1 << ivg);
555 cec->ilat &= ~(1 << ivg);
557 /* Interrupts are processed in between insns which means the return
558 point is the insn-to-be-executed (which is the current PC). But
559 exceptions are handled while executing an insn, so we may have to
560 advance the PC ourselves when setting RETX.
561 XXX: Advancing the PC should only be for "service" exceptions, and
562 handling them after executing the insn should be OK, which
563 means we might be able to use the event interface for it. */
569 /* Signal the JTAG ICE. */
570 /* XXX: what happens with 'raise 0' ? */
572 excp_to_sim_halt (sim_stopped, SIM_SIGTRAP);
573 /* XXX: Need an easy way for gdb to signal it isnt here. */
574 cec->ipend &= ~IVG_EMU_B;
577 /* Have the core reset simply exit (i.e. "shutdown"). */
578 excp_to_sim_halt (sim_exited, 0);
581 /* XXX: Should check this. */
585 /* Non-service exceptions point to the excepting instruction. */
590 bu32 nextpc = hwloop_get_next_pc (cpu, oldpc, INSN_LEN);
591 SET_RETXREG (nextpc);
596 /* XXX: what happens with 'raise 4' ? */
597 sim_io_error (sd, "%s: what to do with 'raise 4' ?", __func__);
600 SET_RETIREG (oldpc | (ivg == curr_ivg ? 1 : 0));
604 /* If EVT_OVERRIDE is in effect (IVG7+), use the reset address. */
605 if ((cec->evt_override & 0xff80) & (1 << ivg))
606 SET_PCREG (cec_get_reset_evt (cpu));
608 SET_PCREG (cec_get_evt (cpu, ivg));
610 BFIN_TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC (to EVT%i):", ivg);
611 BFIN_CPU_STATE.did_jump = true;
613 /* Enable the global interrupt mask upon interrupt entry. */
615 cec_irpten_enable (cpu, cec);
618 /* When moving between states, don't let internal states bleed through. */
621 /* When going from user to super, we set LSB in LB regs to avoid
622 misbehavior and/or malicious code.
623 Also need to load SP alias with KSP. */
624 if (curr_ivg == IVG_USER)
627 for (i = 0; i < 2; ++i)
628 if (!(LBREG (i) & 1))
629 SET_LBREG (i, LBREG (i) | 1);
635 TRACE_EVENTS (cpu, "now at EVT%i", _cec_get_ivg (cec));
639 cec_read_ret_reg (SIM_CPU *cpu, int ivg)
643 case IVG_EMU: return RETEREG;
644 case IVG_NMI: return RETNREG;
645 case IVG_EVX: return RETXREG;
646 default: return RETIREG;
651 cec_latch (SIM_CPU *cpu, int ivg)
653 struct bfin_cec *cec;
655 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
658 SET_PCREG (cec_read_ret_reg (cpu, ivg));
659 BFIN_TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC");
663 cec = CEC_STATE (cpu);
664 cec->ilat |= (1 << ivg);
665 _cec_check_pending (cpu, cec);
669 cec_hwerr (SIM_CPU *cpu, int hwerr)
671 SET_HWERRCAUSE (hwerr);
672 cec_latch (cpu, IVG_IVHW);
676 cec_return (SIM_CPU *cpu, int ivg)
678 SIM_DESC sd = CPU_STATE (cpu);
679 struct bfin_cec *cec;
686 BFIN_CPU_STATE.did_jump = true;
687 if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
689 SET_PCREG (cec_read_ret_reg (cpu, ivg));
690 BFIN_TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC");
694 cec = CEC_STATE (cpu);
696 /* XXX: This isn't entirely correct ... */
697 cec->ipend &= ~IVG_EMU_B;
699 curr_ivg = _cec_get_ivg (cec);
705 TRACE_EVENTS (cpu, "returning from EVT%i (should be EVT%i)", curr_ivg, ivg);
707 /* Not allowed to return from usermode. */
708 if (curr_ivg == IVG_USER)
709 cec_exception (cpu, VEC_ILL_RES);
711 if (ivg > IVG15 || ivg < 0)
712 sim_io_error (sd, "%s: ivg %i out of range !", __func__, ivg);
714 _cec_require_supervisor (cpu, cec);
719 /* RTE -- only valid in emulation mode. */
720 /* XXX: What does the hardware do ? */
721 if (curr_ivg != IVG_EMU)
722 cec_exception (cpu, VEC_ILL_RES);
725 /* RTN -- only valid in NMI. */
726 /* XXX: What does the hardware do ? */
727 if (curr_ivg != IVG_NMI)
728 cec_exception (cpu, VEC_ILL_RES);
731 /* RTX -- only valid in exception. */
732 /* XXX: What does the hardware do ? */
733 if (curr_ivg != IVG_EVX)
734 cec_exception (cpu, VEC_ILL_RES);
737 /* RTI -- not valid in emulation, nmi, exception, or user. */
738 /* XXX: What does the hardware do ? */
739 if (curr_ivg == IVG_EMU || curr_ivg == IVG_NMI
740 || curr_ivg == IVG_EVX || curr_ivg == IVG_USER)
741 cec_exception (cpu, VEC_ILL_RES);
744 /* XXX: Is this even possible ? */
745 excp_to_sim_halt (sim_stopped, SIM_SIGABRT);
748 newpc = cec_read_ret_reg (cpu, ivg);
750 /* XXX: Does this nested trick work on EMU/NMI/EVX ? */
752 /* XXX: Delayed clear shows bad PCREG register trace above ? */
753 SET_PCREG (newpc & ~1);
755 BFIN_TRACE_BRANCH (cpu, oldpc, PCREG, -1, "CEC changed PC (from EVT%i)", ivg);
757 /* Update ipend after the BFIN_TRACE_BRANCH so dv-bfin_trace
758 knows current CEC state wrt overflow. */
760 cec->ipend &= ~(1 << ivg);
762 /* Disable global interrupt mask to let any interrupt take over, but
763 only when we were already in a RTI level. Only way we could have
764 raised at that point is if it was cleared in the first place. */
765 if (ivg >= IVG_IVHW || ivg == IVG_RST)
766 cec_irpten_disable (cpu, cec);
768 /* When going from super to user, we clear LSB in LB regs in case
769 it was set on the transition up.
770 Also need to load SP alias with USP. */
771 if (_cec_get_ivg (cec) == -1)
774 for (i = 0; i < 2; ++i)
776 SET_LBREG (i, LBREG (i) & ~1);
781 /* Check for pending interrupts before we return to usermode. */
782 _cec_check_pending (cpu, cec);
786 cec_push_reti (SIM_CPU *cpu)
788 /* XXX: Need to check hardware with popped RETI value
789 and bit 1 is set (when handling nested interrupts).
790 Also need to check behavior wrt SNEN in SYSCFG. */
791 struct bfin_cec *cec;
793 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
796 TRACE_EVENTS (cpu, "pushing RETI");
798 cec = CEC_STATE (cpu);
799 cec_irpten_disable (cpu, cec);
800 /* Check for pending interrupts. */
801 _cec_check_pending (cpu, cec);
805 cec_pop_reti (SIM_CPU *cpu)
807 /* XXX: Need to check hardware with popped RETI value
808 and bit 1 is set (when handling nested interrupts).
809 Also need to check behavior wrt SNEN in SYSCFG. */
810 struct bfin_cec *cec;
812 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
815 TRACE_EVENTS (cpu, "popping RETI");
817 cec = CEC_STATE (cpu);
818 cec_irpten_enable (cpu, cec);