1 /* Simulator for Atmel's AVR core.
2 Copyright (C) 2009-2015 Free Software Foundation, Inc.
3 Written by Tristan Gingold, AdaCore.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "libiberty.h"
27 #include "gdb/remote-sim.h"
31 #include "sim-options.h"
33 /* As AVR is a 8/16 bits processor, define handy types. */
34 typedef unsigned short int word;
35 typedef signed short int sword;
36 typedef unsigned char byte;
37 typedef signed char sbyte;
39 /* The only real register. */
42 /* We update a cycle counter. */
43 static unsigned int cycles = 0;
45 /* If true, the pc needs more than 2 bytes. */
48 /* Max size of I space (which is always flash on avr). */
49 #define MAX_AVR_FLASH (128 * 1024)
50 #define PC_MASK (MAX_AVR_FLASH - 1)
52 /* Mac size of D space. */
53 #define MAX_AVR_SRAM (64 * 1024)
54 #define SRAM_MASK (MAX_AVR_SRAM - 1)
56 /* D space offset in ELF file. */
57 #define SRAM_VADDR 0x800000
59 /* Simulator specific ports. */
60 #define STDIO_PORT 0x52
61 #define EXIT_PORT 0x4F
62 #define ABORT_PORT 0x49
64 /* GDB defined register numbers. */
65 #define AVR_SREG_REGNUM 32
66 #define AVR_SP_REGNUM 33
67 #define AVR_PC_REGNUM 34
69 /* Memory mapped registers. */
81 /* Sreg (status) bits. */
91 /* In order to speed up emulation we use a simple approach:
92 a code is associated with each instruction. The pre-decoding occurs
93 usually once when the instruction is first seen.
94 This works well because I&D spaces are separated.
96 Missing opcodes: sleep, spm, wdr (as they are mmcu dependent).
100 /* Opcode not yet decoded. */
206 /* 2 words opcodes. */
207 #define OP_2words OP_jmp
216 /* The insn (16 bits). */
219 /* Pre-decoding code. */
220 enum avr_opcode code : 8;
221 /* One byte of additional information. */
226 /* TODO: Should be moved to SIM_CPU. */
227 static struct avr_insn_cell flash[MAX_AVR_FLASH];
228 static byte sram[MAX_AVR_SRAM];
230 /* Sign extend a value. */
231 static int sign_ext (word val, int nb_bits)
233 if (val & (1 << (nb_bits - 1)))
234 return val | (-1 << nb_bits);
238 /* Insn field extractors. */
240 /* Extract xxxx_xxxRx_xxxx_RRRR. */
241 static inline byte get_r (word op)
243 return (op & 0xf) | ((op >> 5) & 0x10);
246 /* Extract xxxx_xxxxx_xxxx_RRRR. */
247 static inline byte get_r16 (word op)
249 return 16 + (op & 0xf);
252 /* Extract xxxx_xxxxx_xxxx_xRRR. */
253 static inline byte get_r16_23 (word op)
255 return 16 + (op & 0x7);
258 /* Extract xxxx_xxxD_DDDD_xxxx. */
259 static inline byte get_d (word op)
261 return (op >> 4) & 0x1f;
264 /* Extract xxxx_xxxx_DDDD_xxxx. */
265 static inline byte get_d16 (word op)
267 return 16 + ((op >> 4) & 0x0f);
270 /* Extract xxxx_xxxx_xDDD_xxxx. */
271 static inline byte get_d16_23 (word op)
273 return 16 + ((op >> 4) & 0x07);
276 /* Extract xxxx_xAAx_xxxx_AAAA. */
277 static inline byte get_A (word op)
279 return (op & 0x0f) | ((op & 0x600) >> 5);
282 /* Extract xxxx_xxxx_AAAA_Axxx. */
283 static inline byte get_biA (word op)
285 return (op >> 3) & 0x1f;
288 /* Extract xxxx_KKKK_xxxx_KKKK. */
289 static inline byte get_K (word op)
291 return (op & 0xf) | ((op & 0xf00) >> 4);
294 /* Extract xxxx_xxKK_KKKK_Kxxx. */
295 static inline int get_k (word op)
297 return sign_ext ((op & 0x3f8) >> 3, 7);
300 /* Extract xxxx_xxxx_xxDD_xxxx. */
301 static inline byte get_d24 (word op)
303 return 24 + ((op >> 3) & 6);
306 /* Extract xxxx_xxxx_KKxx_KKKK. */
307 static inline byte get_k6 (word op)
309 return (op & 0xf) | ((op >> 2) & 0x30);
312 /* Extract xxQx_QQxx_xxxx_xQQQ. */
313 static inline byte get_q (word op)
315 return (op & 7) | ((op >> 7) & 0x18)| ((op >> 8) & 0x20);
318 /* Extract xxxx_xxxx_xxxx_xBBB. */
319 static inline byte get_b (word op)
324 /* AVR is little endian. */
326 read_word (unsigned int addr)
328 return sram[addr] | (sram[addr + 1] << 8);
332 write_word (unsigned int addr, word w)
335 sram[addr + 1] = w >> 8;
339 read_word_post_inc (unsigned int addr)
341 word v = read_word (addr);
342 write_word (addr, v + 1);
347 read_word_pre_dec (unsigned int addr)
349 word v = read_word (addr) - 1;
350 write_word (addr, v);
355 update_flags_logic (byte res)
357 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
359 sram[SREG] |= SREG_Z;
361 sram[SREG] |= SREG_N | SREG_S;
365 update_flags_add (byte r, byte a, byte b)
369 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
371 sram[SREG] |= SREG_N;
372 carry = (a & b) | (a & ~r) | (b & ~r);
374 sram[SREG] |= SREG_H;
376 sram[SREG] |= SREG_C;
377 if (((a & b & ~r) | (~a & ~b & r)) & 0x80)
378 sram[SREG] |= SREG_V;
379 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
380 sram[SREG] |= SREG_S;
382 sram[SREG] |= SREG_Z;
385 static void update_flags_sub (byte r, byte a, byte b)
389 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
391 sram[SREG] |= SREG_N;
392 carry = (~a & b) | (b & r) | (r & ~a);
394 sram[SREG] |= SREG_H;
396 sram[SREG] |= SREG_C;
397 if (((a & ~b & ~r) | (~a & b & r)) & 0x80)
398 sram[SREG] |= SREG_V;
399 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_V))
400 sram[SREG] |= SREG_S;
401 /* Note: Z is not set. */
404 static enum avr_opcode
405 decode (unsigned int pc)
407 word op1 = flash[pc].op;
409 switch ((op1 >> 12) & 0x0f)
412 switch ((op1 >> 10) & 0x3)
415 switch ((op1 >> 8) & 0x3)
445 flash[pc].r = SREG_C;
453 switch ((op1 >> 10) & 0x3)
463 flash[pc].r = SREG_C;
468 switch ((op1 >> 10) & 0x3)
496 flash[pc].r = get_q (op1);
501 flash[pc].r = get_q (op1);
509 flash[pc].r = get_q (op1);
514 flash[pc].r = get_q (op1);
520 switch ((op1 >> 8) & 0xf)
524 switch ((op1 >> 0) & 0xf)
539 return OP_elpm_inc_Z;
556 switch ((op1 >> 0) & 0xf)
598 case 0x8: /* 9[45]x8 */
599 switch ((op1 >> 4) & 0x1f)
633 case 0x9: /* 9[45]x9 */
634 switch ((op1 >> 4) & 0x1f)
652 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
656 flash[pc].r = ((op1 & 0x1f0) >> 3) | (op1 & 1);
680 flash[pc].r = get_A (op1);
681 if (((op1 >> 11) & 1) == 0)
692 switch ((op1 >> 9) & 7)
696 flash[pc].r = 1 << (op1 & 7);
700 flash[pc].r = 1 << (op1 & 7);
705 flash[pc].r = 1 << (op1 & 7);
712 flash[pc].r = 1 << (op1 & 7);
719 flash[pc].r = 1 << (op1 & 7);
726 flash[pc].r = 1 << (op1 & 7);
737 do_call (unsigned int npc)
739 unsigned int sp = read_word (REG_SP);
743 sram[sp--] = pc >> 8;
746 sram[sp--] = pc >> 16;
749 write_word (REG_SP, sp);
755 get_insn_length (unsigned int p)
757 if (flash[p].code == OP_unknown)
758 flash[p].code = decode(p);
759 if (flash[p].code >= OP_2words)
768 return (sram[RAMPZ] << 16) | (sram[REGZ_HI] << 8) | sram[REGZ_LO];
772 get_lpm (unsigned int addr)
776 w = flash[(addr >> 1) & PC_MASK].op;
783 gen_mul (unsigned int res)
786 sram[SREG] &= ~(SREG_Z | SREG_C);
788 sram[SREG] |= SREG_Z;
790 sram[SREG] |= SREG_C;
795 step_once (SIM_CPU *cpu)
805 code = flash[pc].code;
809 if (tracing && code != OP_unknown)
815 sim_cb_eprintf (callback, "R00-07:");
816 for (i = 0; i < 8; i++)
817 sim_cb_eprintf (callback, " %02x", sram[i]);
818 sim_cb_eprintf (callback, " -");
819 for (i = 8; i < 16; i++)
820 sim_cb_eprintf (callback, " %02x", sram[i]);
821 sim_cb_eprintf (callback, " SP: %02x %02x",
822 sram[REG_SP + 1], sram[REG_SP]);
823 sim_cb_eprintf (callback, "\n");
824 sim_cb_eprintf (callback, "R16-31:");
825 for (i = 16; i < 24; i++)
826 sim_cb_eprintf (callback, " %02x", sram[i]);
827 sim_cb_eprintf (callback, " -");
828 for (i = 24; i < 32; i++)
829 sim_cb_eprintf (callback, " %02x", sram[i]);
830 sim_cb_eprintf (callback, " ");
832 for (i = 0; i < 8; i++)
833 sim_cb_eprintf (callback, "%c",
834 flags & (0x80 >> i) ? "ITHSVNZC"[i] : '-');
835 sim_cb_eprintf (callback, "\n");
839 sim_cb_eprintf (callback, "%06x: %04x\n", 2 * pc, flash[pc].op);
842 sim_cb_eprintf (callback, "pc=0x%06x insn=0x%04x code=%d r=%d\n",
843 2 * pc, flash[pc].op, code, flash[pc].r);
844 disassemble_insn (CPU_STATE (cpu), pc);
845 sim_cb_eprintf (callback, "\n");
851 pc = (pc + 1) & PC_MASK;
857 flash[ipc].code = decode(ipc);
866 /* 2 words instruction, but we don't care about the pc. */
867 pc = ((flash[ipc].r << 16) | flash[ipc + 1].op) & PC_MASK;
872 pc = ((sram[EIND] << 16) | read_word (REGZ)) & PC_MASK;
877 pc = read_word (REGZ) & PC_MASK;
882 /* 2 words instruction. */
884 do_call ((flash[ipc].r << 16) | flash[ipc + 1].op);
888 do_call ((sram[EIND] << 16) | read_word (REGZ));
892 do_call (read_word (REGZ));
896 do_call (pc + sign_ext (op & 0xfff, 12));
900 sram[SREG] |= SREG_I;
904 unsigned int sp = read_word (REG_SP);
907 pc = sram[++sp] << 16;
912 pc |= sram[++sp] << 8;
914 write_word (REG_SP, sp);
920 /* Stop on this address. */
921 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
928 if (sram[SREG] & SREG_T)
935 if (sram[get_d (op)] & flash[ipc].r)
936 sram[SREG] |= SREG_T;
938 sram[SREG] &= ~SREG_T;
943 if (((sram[get_d (op)] & flash[ipc].r) == 0) ^ ((op & 0x0200) != 0))
945 int l = get_insn_length(pc);
953 unsigned int sp = read_word (REG_SP);
954 sram[sp--] = sram[get_d (op)];
955 write_word (REG_SP, sp);
962 unsigned int sp = read_word (REG_SP);
963 sram[get_d (op)] = sram[++sp];
964 write_word (REG_SP, sp);
970 sram[SREG] &= ~(1 << ((op >> 4) & 0x7));
974 sram[SREG] |= 1 << ((op >> 4) & 0x7);
978 pc = (pc + sign_ext (op & 0xfff, 12)) & PC_MASK;
984 res = sram[d] ^ sram[get_r (op)];
986 update_flags_logic (res);
991 res = sram[d] & sram[get_r (op)];
993 update_flags_logic (res);
998 res = sram[d] & get_K (op);
1000 update_flags_logic (res);
1005 res = sram[d] | sram[get_r (op)];
1007 update_flags_logic (res);
1012 res = sram[d] | get_K (op);
1014 update_flags_logic (res);
1021 update_flags_logic (res);
1022 sram[SREG] |= SREG_C;
1028 sram[d] = (vd >> 4) | (vd << 4);
1036 sram[SREG] &= ~(SREG_H | SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1038 sram[SREG] |= SREG_Z;
1040 sram[SREG] |= SREG_C;
1042 sram[SREG] |= SREG_V | SREG_N;
1043 else if (res & 0x80)
1044 sram[SREG] |= SREG_N | SREG_S;
1045 if ((res | vd) & 0x08)
1046 sram[SREG] |= SREG_H;
1053 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1055 sram[SREG] |= SREG_V | SREG_N;
1056 else if (res & 0x80)
1057 sram[SREG] |= SREG_N | SREG_S;
1059 sram[SREG] |= SREG_Z;
1066 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z);
1068 sram[SREG] |= SREG_V | SREG_S;
1069 else if (res & 0x80)
1070 sram[SREG] |= SREG_N | SREG_S;
1072 sram[SREG] |= SREG_Z;
1079 res = (vd >> 1) | (vd & flash[ipc].r);
1081 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1083 sram[SREG] |= SREG_C | SREG_S;
1085 sram[SREG] |= SREG_N;
1086 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1087 sram[SREG] |= SREG_V;
1089 sram[SREG] |= SREG_Z;
1095 res = vd >> 1 | (sram[SREG] << 7);
1097 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1099 sram[SREG] |= SREG_C | SREG_S;
1101 sram[SREG] |= SREG_N;
1102 if (!(sram[SREG] & SREG_N) ^ !(sram[SREG] & SREG_C))
1103 sram[SREG] |= SREG_V;
1105 sram[SREG] |= SREG_Z;
1109 gen_mul ((word)sram[get_r (op)] * (word)sram[get_d (op)]);
1113 gen_mul ((sword)(sbyte)sram[get_r16 (op)]
1114 * (sword)(sbyte)sram[get_d16 (op)]);
1118 gen_mul ((sword)(word)sram[get_r16_23 (op)]
1119 * (sword)(sbyte)sram[get_d16_23 (op)]);
1123 gen_mul (((word)sram[get_r16_23 (op)]
1124 * (word)sram[get_d16_23 (op)]) << 1);
1128 gen_mul (((sword)(sbyte)sram[get_r16_23 (op)]
1129 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
1133 gen_mul (((sword)(word)sram[get_r16_23 (op)]
1134 * (sword)(sbyte)sram[get_d16_23 (op)]) << 1);
1139 r = sram[get_r (op)];
1142 res = r + vd + (sram[SREG] & flash[ipc].r);
1144 update_flags_add (res, vd, r);
1150 r = sram[get_r (op)];
1153 update_flags_sub (res, vd, r);
1155 sram[SREG] |= SREG_Z;
1160 byte old = sram[SREG];
1163 r = sram[get_r (op)];
1164 res = vd - r - (old & SREG_C);
1166 update_flags_sub (res, vd, r);
1167 if (res == 0 && (old & SREG_Z))
1168 sram[SREG] |= SREG_Z;
1178 update_flags_sub (res, vd, r);
1180 sram[SREG] |= SREG_Z;
1185 byte old = sram[SREG];
1190 res = vd - r - (old & SREG_C);
1192 update_flags_sub (res, vd, r);
1193 if (res == 0 && (old & SREG_Z))
1194 sram[SREG] |= SREG_Z;
1199 sram[get_d (op)] = sram[get_r (op)];
1203 d = (op & 0xf0) >> 3;
1204 r = (op & 0x0f) << 1;
1206 sram[d + 1] = sram[r + 1];
1210 d = get_A (op) + 0x20;
1211 res = sram[get_d (op)];
1213 if (d == STDIO_PORT)
1215 else if (d == EXIT_PORT)
1216 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, pc, sim_exited, 0);
1217 else if (d == ABORT_PORT)
1218 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, pc, sim_exited, 1);
1222 d = get_A (op) + 0x20;
1223 sram[get_d (op)] = sram[d];
1227 d = get_biA (op) + 0x20;
1228 sram[d] &= ~(1 << get_b(op));
1232 d = get_biA (op) + 0x20;
1233 sram[d] |= 1 << get_b(op);
1237 if (!(sram[get_biA (op) + 0x20] & 1 << get_b(op)))
1239 int l = get_insn_length(pc);
1246 if (sram[get_biA (op) + 0x20] & 1 << get_b(op))
1248 int l = get_insn_length(pc);
1261 sram[get_d (op)] = sram[flash[pc].op];
1267 sram[flash[pc].op] = sram[get_d (op)];
1273 if (sram[get_r (op)] == sram[get_d (op)])
1275 int l = get_insn_length(pc);
1282 r = sram[get_r (op)];
1283 d = sram[get_d (op)];
1285 update_flags_sub (res, d, r);
1287 sram[SREG] |= SREG_Z;
1292 d = sram[get_d16 (op)];
1294 update_flags_sub (res, d, r);
1296 sram[SREG] |= SREG_Z;
1301 byte old = sram[SREG];
1302 d = sram[get_d (op)];
1303 r = sram[get_r (op)];
1304 res = d - r - (old & SREG_C);
1305 update_flags_sub (res, d, r);
1306 if (res == 0 && (old & SREG_Z))
1307 sram[SREG] |= SREG_Z;
1312 if (!(sram[SREG] & flash[ipc].r))
1314 pc = (pc + get_k (op)) & PC_MASK;
1320 if (sram[SREG] & flash[ipc].r)
1322 pc = (pc + get_k (op)) & PC_MASK;
1328 sram[0] = get_lpm (read_word (REGZ));
1333 sram[get_d (op)] = get_lpm (read_word (REGZ));
1338 sram[get_d (op)] = get_lpm (read_word_post_inc (REGZ));
1343 sram[0] = get_lpm (get_z ());
1348 sram[get_d (op)] = get_lpm (get_z ());
1354 unsigned int z = get_z ();
1356 sram[get_d (op)] = get_lpm (z);
1359 sram[REGZ_HI] = z >> 8;
1360 sram[RAMPZ] = z >> 16;
1366 sram[get_d (op)] = sram[read_word_post_inc (REGZ) & SRAM_MASK];
1371 sram[get_d (op)] = sram[read_word_pre_dec (REGZ) & SRAM_MASK];
1376 sram[get_d (op)] = sram[read_word_post_inc (REGX) & SRAM_MASK];
1381 sram[get_d (op)] = sram[read_word_pre_dec (REGX) & SRAM_MASK];
1386 sram[get_d (op)] = sram[read_word_post_inc (REGY) & SRAM_MASK];
1391 sram[get_d (op)] = sram[read_word_pre_dec (REGY) & SRAM_MASK];
1396 sram[read_word (REGX) & SRAM_MASK] = sram[get_d (op)];
1401 sram[read_word_post_inc (REGX) & SRAM_MASK] = sram[get_d (op)];
1406 sram[read_word_pre_dec (REGX) & SRAM_MASK] = sram[get_d (op)];
1411 sram[read_word_post_inc (REGZ) & SRAM_MASK] = sram[get_d (op)];
1416 sram[read_word_pre_dec (REGZ) & SRAM_MASK] = sram[get_d (op)];
1421 sram[read_word_post_inc (REGY) & SRAM_MASK] = sram[get_d (op)];
1426 sram[read_word_pre_dec (REGY) & SRAM_MASK] = sram[get_d (op)];
1431 sram[read_word (REGY) + flash[ipc].r] = sram[get_d (op)];
1436 sram[read_word (REGZ) + flash[ipc].r] = sram[get_d (op)];
1441 sram[get_d (op)] = sram[read_word (REGZ) + flash[ipc].r];
1446 sram[get_d (op)] = sram[read_word (REGY) + flash[ipc].r];
1451 sram[get_d (op)] = sram[read_word (REGX) & SRAM_MASK];
1457 word wk = get_k6 (op);
1465 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1467 sram[SREG] |= SREG_Z;
1469 sram[SREG] |= SREG_N;
1470 if (wres & ~wr & 0x8000)
1471 sram[SREG] |= SREG_C;
1472 if (~wres & wr & 0x8000)
1473 sram[SREG] |= SREG_V;
1474 if (((~wres & wr) ^ wres) & 0x8000)
1475 sram[SREG] |= SREG_S;
1476 write_word (d, wres);
1483 word wk = get_k6 (op);
1491 sram[SREG] &= ~(SREG_S | SREG_V | SREG_N | SREG_Z | SREG_C);
1493 sram[SREG] |= SREG_Z;
1495 sram[SREG] |= SREG_N;
1496 if (~wres & wr & 0x8000)
1497 sram[SREG] |= SREG_C;
1498 if (wres & ~wr & 0x8000)
1499 sram[SREG] |= SREG_V;
1500 if (((wres & ~wr) ^ wres) & 0x8000)
1501 sram[SREG] |= SREG_S;
1502 write_word (d, wres);
1508 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, pc, sim_signalled, SIM_SIGILL);
1511 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, pc, sim_signalled, SIM_SIGILL);
1516 sim_engine_run (SIM_DESC sd,
1517 int next_cpu_nr, /* ignore */
1518 int nr_cpus, /* ignore */
1519 int siggnal) /* ignore */
1523 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1525 cpu = STATE_CPU (sd, 0);
1530 if (sim_events_tick (sd))
1531 sim_events_process (sd);
1536 sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
1540 if (addr >= 0 && addr < SRAM_VADDR)
1542 while (size > 0 && addr < (MAX_AVR_FLASH << 1))
1544 word val = flash[addr >> 1].op;
1547 val = (val & 0xff) | (buffer[0] << 8);
1549 val = (val & 0xff00) | buffer[0];
1551 flash[addr >> 1].op = val;
1552 flash[addr >> 1].code = OP_unknown;
1557 return osize - size;
1559 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1562 if (addr + size > MAX_AVR_SRAM)
1563 size = MAX_AVR_SRAM - addr;
1564 memcpy (sram + addr, buffer, size);
1572 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
1576 if (addr >= 0 && addr < SRAM_VADDR)
1578 while (size > 0 && addr < (MAX_AVR_FLASH << 1))
1580 word val = flash[addr >> 1].op;
1589 return osize - size;
1591 else if (addr >= SRAM_VADDR && addr < SRAM_VADDR + MAX_AVR_SRAM)
1594 if (addr + size > MAX_AVR_SRAM)
1595 size = MAX_AVR_SRAM - addr;
1596 memcpy (buffer, sram + addr, size);
1602 memset (buffer, 0, size);
1608 sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1610 if (rn < 32 && length == 1)
1615 if (rn == AVR_SREG_REGNUM && length == 1)
1617 sram[SREG] = *memory;
1620 if (rn == AVR_SP_REGNUM && length == 2)
1622 sram[REG_SP] = memory[0];
1623 sram[REG_SP + 1] = memory[1];
1626 if (rn == AVR_PC_REGNUM && length == 4)
1628 pc = (memory[0] >> 1) | (memory[1] << 7)
1629 | (memory[2] << 15) | (memory[3] << 23);
1637 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
1639 if (rn < 32 && length == 1)
1644 if (rn == AVR_SREG_REGNUM && length == 1)
1646 *memory = sram[SREG];
1649 if (rn == AVR_SP_REGNUM && length == 2)
1651 memory[0] = sram[REG_SP];
1652 memory[1] = sram[REG_SP + 1];
1655 if (rn == AVR_PC_REGNUM && length == 4)
1657 memory[0] = pc << 1;
1658 memory[1] = pc >> 7;
1659 memory[2] = pc >> 15;
1660 memory[3] = pc >> 23;
1667 free_state (SIM_DESC sd)
1669 if (STATE_MODULES (sd) != NULL)
1670 sim_module_uninstall (sd);
1671 sim_cpu_free_all (sd);
1672 sim_state_free (sd);
1676 sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
1678 SIM_DESC sd = sim_state_alloc (kind, cb);
1679 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1681 /* The cpu data is kept in a separately allocated chunk of memory. */
1682 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
1688 STATE_WATCHPOINTS (sd)->pc = &pc;
1689 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (pc);
1691 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
1697 /* getopt will print the error message so we just have to exit if this fails.
1698 FIXME: Hmmm... in the case of gdb we need getopt to call
1700 if (sim_parse_args (sd, argv) != SIM_RC_OK)
1706 /* Check for/establish the a reference program image. */
1707 if (sim_analyze_program (sd,
1708 (STATE_PROG_ARGV (sd) != NULL
1709 ? *STATE_PROG_ARGV (sd)
1710 : NULL), abfd) != SIM_RC_OK)
1716 /* Configure/verify the target byte order and other runtime
1717 configuration options. */
1718 if (sim_config (sd) != SIM_RC_OK)
1720 sim_module_uninstall (sd);
1724 if (sim_post_argv_init (sd) != SIM_RC_OK)
1726 /* Uninstall the modules to avoid memory leaks,
1727 file descriptor leaks, etc. */
1728 sim_module_uninstall (sd);
1732 /* Clear all the memory. */
1733 memset (sram, 0, sizeof (sram));
1734 memset (flash, 0, sizeof (flash));
1740 sim_close (SIM_DESC sd, int quitting)
1742 sim_module_uninstall (sd);
1746 sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
1750 pc = bfd_get_start_address (abfd);
1755 avr_pc22 = (bfd_get_mach (abfd) >= bfd_mach_avr6);