1 /* run front end support for arm
2 Copyright (C) 1995, 1996, 1997, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of ARM SIM.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with this program; if not, write to the Free
19 Software Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This file provides the interface between the simulator and
23 run.c and gdb (when the simulator is linked with gdb).
24 All simulator interaction should go through this file. */
31 #include "gdb/callback.h"
32 #include "gdb/remote-sim.h"
37 #include "sim-utils.h"
39 #include "gdb/sim-arm.h"
41 host_callback *sim_callback;
43 static struct ARMul_State *state;
45 /* Who is using the simulator. */
46 static SIM_OPEN_KIND sim_kind;
51 /* Memory size in bytes. */
52 static int mem_size = (1 << 21);
54 /* Non-zero to display start up banner, and maybe other things. */
57 /* Non-zero to set big endian mode. */
58 static int big_endian;
62 /* Cirrus DSP registers.
64 We need to define these registers outside of maverick.c because
65 maverick.c might not be linked in unless --target=arm9e-* in which
66 case wrapper.c will not compile because it tries to access Cirrus
67 registers. This should all go away once we get the Cirrus and ARM
68 Coprocessor to coexist in armcopro.c-- aldyh. */
85 union maverick_acc_regs
87 long double ld; /* Acc registers are 72-bits. */
90 struct maverick_regs DSPregs[16];
91 union maverick_acc_regs DSPacc[4];
101 ARMul_EmulateInit ();
102 state = ARMul_NewState ();
103 state->bigendSig = (big_endian ? HIGH : LOW);
104 ARMul_MemoryInit (state, mem_size);
105 ARMul_OSInit (state);
106 state->verbose = verbosity;
111 /* Set verbosity level of simulator.
112 This is not intended to produce detailed tracing or debugging information.
114 /* FIXME: common/run.c doesn't do this yet. */
123 /* Set the memory size to SIZE bytes.
124 Must be called before initializing simulator. */
125 /* FIXME: Rename to sim_set_mem_size. */
135 ARMul_ConsolePrint VPARAMS ((ARMul_State * state,
143 va_start (ap, format);
144 vprintf (format, ap);
150 ARMul_Debug (state, pc, instr)
151 ARMul_State * state ATTRIBUTE_UNUSED;
152 ARMword pc ATTRIBUTE_UNUSED;
153 ARMword instr ATTRIBUTE_UNUSED;
159 sim_write (sd, addr, buffer, size)
160 SIM_DESC sd ATTRIBUTE_UNUSED;
162 unsigned char * buffer;
169 for (i = 0; i < size; i++)
170 ARMul_SafeWriteByte (state, addr + i, buffer[i]);
176 sim_read (sd, addr, buffer, size)
177 SIM_DESC sd ATTRIBUTE_UNUSED;
179 unsigned char * buffer;
186 for (i = 0; i < size; i++)
187 buffer[i] = ARMul_SafeReadByte (state, addr + i);
194 SIM_DESC sd ATTRIBUTE_UNUSED;
196 (*sim_callback->printf_filtered)
198 "This simulator does not support tracing\n");
204 SIM_DESC sd ATTRIBUTE_UNUSED;
206 state->Emulate = STOP;
212 sim_resume (sd, step, siggnal)
213 SIM_DESC sd ATTRIBUTE_UNUSED;
215 int siggnal ATTRIBUTE_UNUSED;
217 state->EndCondition = 0;
222 state->Reg[15] = ARMul_DoInstr (state);
223 if (state->EndCondition == 0)
224 state->EndCondition = RDIError_BreakpointReached;
228 state->NextInstr = RESUME; /* treat as PC change */
229 state->Reg[15] = ARMul_DoProg (state);
236 sim_create_inferior (sd, abfd, argv, env)
237 SIM_DESC sd ATTRIBUTE_UNUSED;
247 ARMul_SetPC (state, bfd_get_start_address (abfd));
249 ARMul_SetPC (state, 0); /* ??? */
251 mach = bfd_get_mach (abfd);
256 (*sim_callback->printf_filtered)
258 "Unknown machine type '%d'; please update sim_create_inferior.\n",
263 /* We wouldn't set the machine type with earlier toolchains, so we
264 explicitly select a processor capable of supporting all ARMs in
266 /* We choose the XScale rather than the iWMMXt, because the iWMMXt
267 removes the FPE emulator, since it conflicts with its coprocessors.
268 For the most generic ARM support, we want the FPE emulator in place. */
269 case bfd_mach_arm_XScale:
270 ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
273 case bfd_mach_arm_iWMMXt:
275 extern int SWI_vector_installed;
278 if (! SWI_vector_installed)
280 /* Intialise the hardware vectors to zero. */
281 if (! SWI_vector_installed)
282 for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
283 ARMul_WriteWord (state, i, 0);
285 /* ARM_WriteWord will have detected the write to the SWI vector,
286 but we want SWI_vector_installed to remain at 0 so that thumb
287 mode breakpoints will work. */
288 SWI_vector_installed = 0;
291 ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
294 case bfd_mach_arm_ep9312:
295 ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
299 if (bfd_family_coff (abfd))
301 /* This is a special case in order to support COFF based ARM toolchains.
302 The COFF header does not have enough room to store all the different
303 kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
304 to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
305 machine type here, we assume it could be any of the above architectures
306 and so select the most feature-full. */
307 ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
310 /* Otherwise drop through. */
312 case bfd_mach_arm_5T:
313 ARMul_SelectProcessor (state, ARM_v5_Prop);
316 case bfd_mach_arm_5TE:
317 ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
321 case bfd_mach_arm_4T:
322 ARMul_SelectProcessor (state, ARM_v4_Prop);
326 case bfd_mach_arm_3M:
327 ARMul_SelectProcessor (state, ARM_Lock_Prop);
331 case bfd_mach_arm_2a:
332 ARMul_SelectProcessor (state, ARM_Fix26_Prop);
336 if ( mach != bfd_mach_arm_3
337 && mach != bfd_mach_arm_3M
338 && mach != bfd_mach_arm_2
339 && mach != bfd_mach_arm_2a)
341 /* Reset mode to ARM. A gdb user may rerun a program that had entered
342 THUMB mode from the start and cause the ARM-mode startup code to be
343 executed in THUMB mode. */
344 ARMul_SetCPSR (state, SVC32MODE);
349 /* Set up the command line by laboriously stringing together
350 the environment carefully picked apart by our caller. */
352 /* Free any old stuff. */
353 if (state->CommandLine != NULL)
355 free (state->CommandLine);
356 state->CommandLine = NULL;
359 /* See how much we need. */
360 for (arg = argv; *arg != NULL; arg++)
361 argvlen += strlen (*arg) + 1;
364 state->CommandLine = malloc (argvlen + 1);
365 if (state->CommandLine != NULL)
368 state->CommandLine[0] = '\0';
370 for (arg = argv; *arg != NULL; arg++)
372 strcat (state->CommandLine, *arg);
373 strcat (state->CommandLine, " ");
380 /* Now see if there's a MEMSIZE spec in the environment. */
383 if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
387 /* Set up memory limit. */
389 strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
399 sim_info (sd, verbose)
400 SIM_DESC sd ATTRIBUTE_UNUSED;
401 int verbose ATTRIBUTE_UNUSED;
406 frommem (state, memory)
407 struct ARMul_State *state;
408 unsigned char *memory;
410 if (state->bigendSig == HIGH)
411 return (memory[0] << 24) | (memory[1] << 16)
412 | (memory[2] << 8) | (memory[3] << 0);
414 return (memory[3] << 24) | (memory[2] << 16)
415 | (memory[1] << 8) | (memory[0] << 0);
419 tomem (state, memory, val)
420 struct ARMul_State *state;
421 unsigned char *memory;
424 if (state->bigendSig == HIGH)
426 memory[0] = val >> 24;
427 memory[1] = val >> 16;
428 memory[2] = val >> 8;
429 memory[3] = val >> 0;
433 memory[3] = val >> 24;
434 memory[2] = val >> 16;
435 memory[1] = val >> 8;
436 memory[0] = val >> 0;
441 sim_store_register (sd, rn, memory, length)
442 SIM_DESC sd ATTRIBUTE_UNUSED;
444 unsigned char *memory;
445 int length ATTRIBUTE_UNUSED;
449 switch ((enum sim_arm_regs) rn)
451 case SIM_ARM_R0_REGNUM:
452 case SIM_ARM_R1_REGNUM:
453 case SIM_ARM_R2_REGNUM:
454 case SIM_ARM_R3_REGNUM:
455 case SIM_ARM_R4_REGNUM:
456 case SIM_ARM_R5_REGNUM:
457 case SIM_ARM_R6_REGNUM:
458 case SIM_ARM_R7_REGNUM:
459 case SIM_ARM_R8_REGNUM:
460 case SIM_ARM_R9_REGNUM:
461 case SIM_ARM_R10_REGNUM:
462 case SIM_ARM_R11_REGNUM:
463 case SIM_ARM_R12_REGNUM:
464 case SIM_ARM_R13_REGNUM:
465 case SIM_ARM_R14_REGNUM:
466 case SIM_ARM_R15_REGNUM: /* PC */
467 case SIM_ARM_FP0_REGNUM:
468 case SIM_ARM_FP1_REGNUM:
469 case SIM_ARM_FP2_REGNUM:
470 case SIM_ARM_FP3_REGNUM:
471 case SIM_ARM_FP4_REGNUM:
472 case SIM_ARM_FP5_REGNUM:
473 case SIM_ARM_FP6_REGNUM:
474 case SIM_ARM_FP7_REGNUM:
475 case SIM_ARM_FPS_REGNUM:
476 ARMul_SetReg (state, state->Mode, rn, frommem (state, memory));
479 case SIM_ARM_PS_REGNUM:
480 state->Cpsr = frommem (state, memory);
481 ARMul_CPSRAltered (state);
484 case SIM_ARM_MAVERIC_COP0R0_REGNUM:
485 case SIM_ARM_MAVERIC_COP0R1_REGNUM:
486 case SIM_ARM_MAVERIC_COP0R2_REGNUM:
487 case SIM_ARM_MAVERIC_COP0R3_REGNUM:
488 case SIM_ARM_MAVERIC_COP0R4_REGNUM:
489 case SIM_ARM_MAVERIC_COP0R5_REGNUM:
490 case SIM_ARM_MAVERIC_COP0R6_REGNUM:
491 case SIM_ARM_MAVERIC_COP0R7_REGNUM:
492 case SIM_ARM_MAVERIC_COP0R8_REGNUM:
493 case SIM_ARM_MAVERIC_COP0R9_REGNUM:
494 case SIM_ARM_MAVERIC_COP0R10_REGNUM:
495 case SIM_ARM_MAVERIC_COP0R11_REGNUM:
496 case SIM_ARM_MAVERIC_COP0R12_REGNUM:
497 case SIM_ARM_MAVERIC_COP0R13_REGNUM:
498 case SIM_ARM_MAVERIC_COP0R14_REGNUM:
499 case SIM_ARM_MAVERIC_COP0R15_REGNUM:
500 memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
501 memory, sizeof (struct maverick_regs));
502 return sizeof (struct maverick_regs);
504 case SIM_ARM_MAVERIC_DSPSC_REGNUM:
505 memcpy (&DSPsc, memory, sizeof DSPsc);
509 case SIM_ARM_IWMMXT_COP0R0_REGNUM:
510 case SIM_ARM_IWMMXT_COP0R1_REGNUM:
511 case SIM_ARM_IWMMXT_COP0R2_REGNUM:
512 case SIM_ARM_IWMMXT_COP0R3_REGNUM:
513 case SIM_ARM_IWMMXT_COP0R4_REGNUM:
514 case SIM_ARM_IWMMXT_COP0R5_REGNUM:
515 case SIM_ARM_IWMMXT_COP0R6_REGNUM:
516 case SIM_ARM_IWMMXT_COP0R7_REGNUM:
517 case SIM_ARM_IWMMXT_COP0R8_REGNUM:
518 case SIM_ARM_IWMMXT_COP0R9_REGNUM:
519 case SIM_ARM_IWMMXT_COP0R10_REGNUM:
520 case SIM_ARM_IWMMXT_COP0R11_REGNUM:
521 case SIM_ARM_IWMMXT_COP0R12_REGNUM:
522 case SIM_ARM_IWMMXT_COP0R13_REGNUM:
523 case SIM_ARM_IWMMXT_COP0R14_REGNUM:
524 case SIM_ARM_IWMMXT_COP0R15_REGNUM:
525 case SIM_ARM_IWMMXT_COP1R0_REGNUM:
526 case SIM_ARM_IWMMXT_COP1R1_REGNUM:
527 case SIM_ARM_IWMMXT_COP1R2_REGNUM:
528 case SIM_ARM_IWMMXT_COP1R3_REGNUM:
529 case SIM_ARM_IWMMXT_COP1R4_REGNUM:
530 case SIM_ARM_IWMMXT_COP1R5_REGNUM:
531 case SIM_ARM_IWMMXT_COP1R6_REGNUM:
532 case SIM_ARM_IWMMXT_COP1R7_REGNUM:
533 case SIM_ARM_IWMMXT_COP1R8_REGNUM:
534 case SIM_ARM_IWMMXT_COP1R9_REGNUM:
535 case SIM_ARM_IWMMXT_COP1R10_REGNUM:
536 case SIM_ARM_IWMMXT_COP1R11_REGNUM:
537 case SIM_ARM_IWMMXT_COP1R12_REGNUM:
538 case SIM_ARM_IWMMXT_COP1R13_REGNUM:
539 case SIM_ARM_IWMMXT_COP1R14_REGNUM:
540 case SIM_ARM_IWMMXT_COP1R15_REGNUM:
541 return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
551 sim_fetch_register (sd, rn, memory, length)
552 SIM_DESC sd ATTRIBUTE_UNUSED;
554 unsigned char *memory;
555 int length ATTRIBUTE_UNUSED;
561 switch ((enum sim_arm_regs) rn)
563 case SIM_ARM_R0_REGNUM:
564 case SIM_ARM_R1_REGNUM:
565 case SIM_ARM_R2_REGNUM:
566 case SIM_ARM_R3_REGNUM:
567 case SIM_ARM_R4_REGNUM:
568 case SIM_ARM_R5_REGNUM:
569 case SIM_ARM_R6_REGNUM:
570 case SIM_ARM_R7_REGNUM:
571 case SIM_ARM_R8_REGNUM:
572 case SIM_ARM_R9_REGNUM:
573 case SIM_ARM_R10_REGNUM:
574 case SIM_ARM_R11_REGNUM:
575 case SIM_ARM_R12_REGNUM:
576 case SIM_ARM_R13_REGNUM:
577 case SIM_ARM_R14_REGNUM:
578 case SIM_ARM_R15_REGNUM: /* PC */
579 regval = ARMul_GetReg (state, state->Mode, rn);
582 case SIM_ARM_FP0_REGNUM:
583 case SIM_ARM_FP1_REGNUM:
584 case SIM_ARM_FP2_REGNUM:
585 case SIM_ARM_FP3_REGNUM:
586 case SIM_ARM_FP4_REGNUM:
587 case SIM_ARM_FP5_REGNUM:
588 case SIM_ARM_FP6_REGNUM:
589 case SIM_ARM_FP7_REGNUM:
590 case SIM_ARM_FPS_REGNUM:
591 memset (memory, 0, length);
594 case SIM_ARM_PS_REGNUM:
595 regval = ARMul_GetCPSR (state);
598 case SIM_ARM_MAVERIC_COP0R0_REGNUM:
599 case SIM_ARM_MAVERIC_COP0R1_REGNUM:
600 case SIM_ARM_MAVERIC_COP0R2_REGNUM:
601 case SIM_ARM_MAVERIC_COP0R3_REGNUM:
602 case SIM_ARM_MAVERIC_COP0R4_REGNUM:
603 case SIM_ARM_MAVERIC_COP0R5_REGNUM:
604 case SIM_ARM_MAVERIC_COP0R6_REGNUM:
605 case SIM_ARM_MAVERIC_COP0R7_REGNUM:
606 case SIM_ARM_MAVERIC_COP0R8_REGNUM:
607 case SIM_ARM_MAVERIC_COP0R9_REGNUM:
608 case SIM_ARM_MAVERIC_COP0R10_REGNUM:
609 case SIM_ARM_MAVERIC_COP0R11_REGNUM:
610 case SIM_ARM_MAVERIC_COP0R12_REGNUM:
611 case SIM_ARM_MAVERIC_COP0R13_REGNUM:
612 case SIM_ARM_MAVERIC_COP0R14_REGNUM:
613 case SIM_ARM_MAVERIC_COP0R15_REGNUM:
614 memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
615 sizeof (struct maverick_regs));
616 return sizeof (struct maverick_regs);
618 case SIM_ARM_MAVERIC_DSPSC_REGNUM:
619 memcpy (memory, & DSPsc, sizeof DSPsc);
623 case SIM_ARM_IWMMXT_COP0R0_REGNUM:
624 case SIM_ARM_IWMMXT_COP0R1_REGNUM:
625 case SIM_ARM_IWMMXT_COP0R2_REGNUM:
626 case SIM_ARM_IWMMXT_COP0R3_REGNUM:
627 case SIM_ARM_IWMMXT_COP0R4_REGNUM:
628 case SIM_ARM_IWMMXT_COP0R5_REGNUM:
629 case SIM_ARM_IWMMXT_COP0R6_REGNUM:
630 case SIM_ARM_IWMMXT_COP0R7_REGNUM:
631 case SIM_ARM_IWMMXT_COP0R8_REGNUM:
632 case SIM_ARM_IWMMXT_COP0R9_REGNUM:
633 case SIM_ARM_IWMMXT_COP0R10_REGNUM:
634 case SIM_ARM_IWMMXT_COP0R11_REGNUM:
635 case SIM_ARM_IWMMXT_COP0R12_REGNUM:
636 case SIM_ARM_IWMMXT_COP0R13_REGNUM:
637 case SIM_ARM_IWMMXT_COP0R14_REGNUM:
638 case SIM_ARM_IWMMXT_COP0R15_REGNUM:
639 case SIM_ARM_IWMMXT_COP1R0_REGNUM:
640 case SIM_ARM_IWMMXT_COP1R1_REGNUM:
641 case SIM_ARM_IWMMXT_COP1R2_REGNUM:
642 case SIM_ARM_IWMMXT_COP1R3_REGNUM:
643 case SIM_ARM_IWMMXT_COP1R4_REGNUM:
644 case SIM_ARM_IWMMXT_COP1R5_REGNUM:
645 case SIM_ARM_IWMMXT_COP1R6_REGNUM:
646 case SIM_ARM_IWMMXT_COP1R7_REGNUM:
647 case SIM_ARM_IWMMXT_COP1R8_REGNUM:
648 case SIM_ARM_IWMMXT_COP1R9_REGNUM:
649 case SIM_ARM_IWMMXT_COP1R10_REGNUM:
650 case SIM_ARM_IWMMXT_COP1R11_REGNUM:
651 case SIM_ARM_IWMMXT_COP1R12_REGNUM:
652 case SIM_ARM_IWMMXT_COP1R13_REGNUM:
653 case SIM_ARM_IWMMXT_COP1R14_REGNUM:
654 case SIM_ARM_IWMMXT_COP1R15_REGNUM:
655 return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
663 tomem (state, memory, regval);
673 #ifdef SIM_TARGET_SWITCHES
675 static void sim_target_parse_arg_array PARAMS ((char **));
680 unsigned int swi_mask;
683 #define SWI_SWITCH "--swi-support"
685 static swi_options options[] =
688 { "demon", SWI_MASK_DEMON },
689 { "angel", SWI_MASK_ANGEL },
690 { "redboot", SWI_MASK_REDBOOT },
693 { "DEMON", SWI_MASK_DEMON },
694 { "ANGEL", SWI_MASK_ANGEL },
695 { "REDBOOT", SWI_MASK_REDBOOT },
701 sim_target_parse_command_line (argc, argv)
707 for (i = 1; i < argc; i++)
709 char * ptr = argv[i];
712 if ((ptr == NULL) || (* ptr != '-'))
715 if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0)
718 if (ptr[sizeof SWI_SWITCH - 1] == 0)
720 /* Remove this option from the argv array. */
721 for (arg = i; arg < argc; arg ++)
722 argv[arg] = argv[arg + 1];
728 ptr += sizeof SWI_SWITCH;
736 for (i = sizeof options / sizeof options[0]; i--;)
737 if (strncmp (ptr, options[i].swi_option,
738 strlen (options[i].swi_option)) == 0)
740 swi_mask |= options[i].swi_mask;
741 ptr += strlen (options[i].swi_option);
754 fprintf (stderr, "Ignoring swi options: %s\n", ptr);
756 /* Remove this option from the argv array. */
757 for (arg = i; arg < argc; arg ++)
758 argv[arg] = argv[arg + 1];
766 sim_target_parse_arg_array (argv)
771 for (i = 0; argv[i]; i++)
774 return (void) sim_target_parse_command_line (i, argv);
778 sim_target_display_usage ()
780 fprintf (stderr, "%s=<list> Comma seperated list of SWI protocols to supoport.\n\
781 This list can contain: NONE, DEMON, ANGEL, REDBOOT and/or ALL.\n",
787 sim_open (kind, ptr, abfd, argv)
794 if (myname) free (myname);
795 myname = (char *) xstrdup (argv[0]);
798 #ifdef SIM_TARGET_SWITCHES
799 sim_target_parse_arg_array (argv);
802 /* Decide upon the endian-ness of the processor.
803 If we can, get the information from the bfd itself.
804 Otherwise look to see if we have been given a command
805 line switch that tells us. Otherwise default to little endian. */
807 big_endian = bfd_big_endian (abfd);
808 else if (argv[1] != NULL)
812 /* Scan for endian-ness and memory-size switches. */
813 for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++)
814 if (argv[i][0] == '-' && argv[i][1] == 'E')
818 if ((c = argv[i][2]) == 0)
827 sim_callback->printf_filtered
828 (sim_callback, "No argument to -E option provided\n");
842 sim_callback->printf_filtered
843 (sim_callback, "Unrecognised argument to -E option\n");
847 else if (argv[i][0] == '-' && argv[i][1] == 'm')
849 if (argv[i][2] != '\0')
850 sim_size (atoi (&argv[i][2]));
851 else if (argv[i + 1] != NULL)
853 sim_size (atoi (argv[i + 1]));
858 sim_callback->printf_filtered (sim_callback,
859 "Missing argument to -m option\n");
870 sim_close (sd, quitting)
871 SIM_DESC sd ATTRIBUTE_UNUSED;
872 int quitting ATTRIBUTE_UNUSED;
880 sim_load (sd, prog, abfd, from_tty)
884 int from_tty ATTRIBUTE_UNUSED;
888 prog_bfd = sim_load_file (sd, myname, sim_callback, prog, abfd,
889 sim_kind == SIM_OPEN_DEBUG, 0, sim_write);
890 if (prog_bfd == NULL)
892 ARMul_SetPC (state, bfd_get_start_address (prog_bfd));
894 bfd_close (prog_bfd);
899 sim_stop_reason (sd, reason, sigrc)
900 SIM_DESC sd ATTRIBUTE_UNUSED;
901 enum sim_stop *reason;
906 *reason = sim_stopped;
909 else if (state->EndCondition == 0)
911 *reason = sim_exited;
912 *sigrc = state->Reg[0] & 255;
916 *reason = sim_stopped;
917 if (state->EndCondition == RDIError_BreakpointReached)
919 else if ( state->EndCondition == RDIError_DataAbort
920 || state->EndCondition == RDIError_AddressException)
928 sim_do_command (sd, cmd)
929 SIM_DESC sd ATTRIBUTE_UNUSED;
930 char *cmd ATTRIBUTE_UNUSED;
932 (*sim_callback->printf_filtered)
934 "This simulator does not accept any commands.\n");
938 sim_set_callbacks (ptr)