1 /* run front end support for arm
2 Copyright (C) 1995-1997, 2000-2002, 2007-2012 Free Software
5 This file is part of ARM SIM.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* This file provides the interface between the simulator and
21 run.c and gdb (when the simulator is linked with gdb).
22 All simulator interaction should go through this file. */
30 #include "gdb/callback.h"
31 #include "gdb/remote-sim.h"
36 #include "sim-utils.h"
38 #include "gdb/sim-arm.h"
39 #include "gdb/signals.h"
40 #include "libiberty.h"
42 host_callback *sim_callback;
44 static struct ARMul_State *state;
46 /* Who is using the simulator. */
47 static SIM_OPEN_KIND sim_kind;
52 /* Memory size in bytes. */
53 static int mem_size = (1 << 21);
55 /* Non-zero to display start up banner, and maybe other things. */
58 /* Non-zero to set big endian mode. */
59 static int big_endian;
63 /* Cirrus DSP registers.
65 We need to define these registers outside of maverick.c because
66 maverick.c might not be linked in unless --target=arm9e-* in which
67 case wrapper.c will not compile because it tries to access Cirrus
68 registers. This should all go away once we get the Cirrus and ARM
69 Coprocessor to coexist in armcopro.c-- aldyh. */
86 union maverick_acc_regs
88 long double ld; /* Acc registers are 72-bits. */
91 struct maverick_regs DSPregs[16];
92 union maverick_acc_regs DSPacc[4];
102 ARMul_EmulateInit ();
103 state = ARMul_NewState ();
104 state->bigendSig = (big_endian ? HIGH : LOW);
105 ARMul_MemoryInit (state, mem_size);
106 ARMul_OSInit (state);
107 state->verbose = verbosity;
112 /* Set verbosity level of simulator.
113 This is not intended to produce detailed tracing or debugging information.
115 /* FIXME: common/run.c doesn't do this yet. */
124 /* Set the memory size to SIZE bytes.
125 Must be called before initializing simulator. */
126 /* FIXME: Rename to sim_set_mem_size. */
136 ARMul_ConsolePrint VPARAMS ((ARMul_State * state,
144 va_start (ap, format);
145 vprintf (format, ap);
151 ARMul_Debug (state, pc, instr)
152 ARMul_State * state ATTRIBUTE_UNUSED;
153 ARMword pc ATTRIBUTE_UNUSED;
154 ARMword instr ATTRIBUTE_UNUSED;
160 sim_write (sd, addr, buffer, size)
161 SIM_DESC sd ATTRIBUTE_UNUSED;
163 const unsigned char * buffer;
170 for (i = 0; i < size; i++)
171 ARMul_SafeWriteByte (state, addr + i, buffer[i]);
177 sim_read (sd, addr, buffer, size)
178 SIM_DESC sd ATTRIBUTE_UNUSED;
180 unsigned char * buffer;
187 for (i = 0; i < size; i++)
188 buffer[i] = ARMul_SafeReadByte (state, addr + i);
195 SIM_DESC sd ATTRIBUTE_UNUSED;
197 (*sim_callback->printf_filtered)
199 "This simulator does not support tracing\n");
205 SIM_DESC sd ATTRIBUTE_UNUSED;
207 state->Emulate = STOP;
213 sim_resume (sd, step, siggnal)
214 SIM_DESC sd ATTRIBUTE_UNUSED;
216 int siggnal ATTRIBUTE_UNUSED;
218 state->EndCondition = 0;
223 state->Reg[15] = ARMul_DoInstr (state);
224 if (state->EndCondition == 0)
225 state->EndCondition = RDIError_BreakpointReached;
229 state->NextInstr = RESUME; /* treat as PC change */
230 state->Reg[15] = ARMul_DoProg (state);
237 sim_create_inferior (sd, abfd, argv, env)
238 SIM_DESC sd ATTRIBUTE_UNUSED;
248 ARMul_SetPC (state, bfd_get_start_address (abfd));
250 ARMul_SetPC (state, 0); /* ??? */
252 mach = bfd_get_mach (abfd);
257 (*sim_callback->printf_filtered)
259 "Unknown machine type '%d'; please update sim_create_inferior.\n",
264 /* We wouldn't set the machine type with earlier toolchains, so we
265 explicitly select a processor capable of supporting all ARMs in
267 /* We choose the XScale rather than the iWMMXt, because the iWMMXt
268 removes the FPE emulator, since it conflicts with its coprocessors.
269 For the most generic ARM support, we want the FPE emulator in place. */
270 case bfd_mach_arm_XScale:
271 ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
274 case bfd_mach_arm_iWMMXt2:
275 case bfd_mach_arm_iWMMXt:
277 extern int SWI_vector_installed;
280 if (! SWI_vector_installed)
282 /* Intialise the hardware vectors to zero. */
283 if (! SWI_vector_installed)
284 for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
285 ARMul_WriteWord (state, i, 0);
287 /* ARM_WriteWord will have detected the write to the SWI vector,
288 but we want SWI_vector_installed to remain at 0 so that thumb
289 mode breakpoints will work. */
290 SWI_vector_installed = 0;
293 ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
296 case bfd_mach_arm_ep9312:
297 ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
301 if (bfd_family_coff (abfd))
303 /* This is a special case in order to support COFF based ARM toolchains.
304 The COFF header does not have enough room to store all the different
305 kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
306 to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
307 machine type here, we assume it could be any of the above architectures
308 and so select the most feature-full. */
309 ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
312 /* Otherwise drop through. */
314 case bfd_mach_arm_5T:
315 ARMul_SelectProcessor (state, ARM_v5_Prop);
318 case bfd_mach_arm_5TE:
319 ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
323 case bfd_mach_arm_4T:
324 ARMul_SelectProcessor (state, ARM_v4_Prop);
328 case bfd_mach_arm_3M:
329 ARMul_SelectProcessor (state, ARM_Lock_Prop);
333 case bfd_mach_arm_2a:
334 ARMul_SelectProcessor (state, ARM_Fix26_Prop);
338 if ( mach != bfd_mach_arm_3
339 && mach != bfd_mach_arm_3M
340 && mach != bfd_mach_arm_2
341 && mach != bfd_mach_arm_2a)
343 /* Reset mode to ARM. A gdb user may rerun a program that had entered
344 THUMB mode from the start and cause the ARM-mode startup code to be
345 executed in THUMB mode. */
346 ARMul_SetCPSR (state, SVC32MODE);
351 /* Set up the command line by laboriously stringing together
352 the environment carefully picked apart by our caller. */
354 /* Free any old stuff. */
355 if (state->CommandLine != NULL)
357 free (state->CommandLine);
358 state->CommandLine = NULL;
361 /* See how much we need. */
362 for (arg = argv; *arg != NULL; arg++)
363 argvlen += strlen (*arg) + 1;
366 state->CommandLine = malloc (argvlen + 1);
367 if (state->CommandLine != NULL)
370 state->CommandLine[0] = '\0';
372 for (arg = argv; *arg != NULL; arg++)
374 strcat (state->CommandLine, *arg);
375 strcat (state->CommandLine, " ");
382 /* Now see if there's a MEMSIZE spec in the environment. */
385 if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
389 /* Set up memory limit. */
391 strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
401 sim_info (sd, verbose)
402 SIM_DESC sd ATTRIBUTE_UNUSED;
403 int verbose ATTRIBUTE_UNUSED;
408 frommem (state, memory)
409 struct ARMul_State *state;
410 unsigned char *memory;
412 if (state->bigendSig == HIGH)
413 return (memory[0] << 24) | (memory[1] << 16)
414 | (memory[2] << 8) | (memory[3] << 0);
416 return (memory[3] << 24) | (memory[2] << 16)
417 | (memory[1] << 8) | (memory[0] << 0);
421 tomem (state, memory, val)
422 struct ARMul_State *state;
423 unsigned char *memory;
426 if (state->bigendSig == HIGH)
428 memory[0] = val >> 24;
429 memory[1] = val >> 16;
430 memory[2] = val >> 8;
431 memory[3] = val >> 0;
435 memory[3] = val >> 24;
436 memory[2] = val >> 16;
437 memory[1] = val >> 8;
438 memory[0] = val >> 0;
443 sim_store_register (sd, rn, memory, length)
444 SIM_DESC sd ATTRIBUTE_UNUSED;
446 unsigned char *memory;
451 switch ((enum sim_arm_regs) rn)
453 case SIM_ARM_R0_REGNUM:
454 case SIM_ARM_R1_REGNUM:
455 case SIM_ARM_R2_REGNUM:
456 case SIM_ARM_R3_REGNUM:
457 case SIM_ARM_R4_REGNUM:
458 case SIM_ARM_R5_REGNUM:
459 case SIM_ARM_R6_REGNUM:
460 case SIM_ARM_R7_REGNUM:
461 case SIM_ARM_R8_REGNUM:
462 case SIM_ARM_R9_REGNUM:
463 case SIM_ARM_R10_REGNUM:
464 case SIM_ARM_R11_REGNUM:
465 case SIM_ARM_R12_REGNUM:
466 case SIM_ARM_R13_REGNUM:
467 case SIM_ARM_R14_REGNUM:
468 case SIM_ARM_R15_REGNUM: /* PC */
469 case SIM_ARM_FP0_REGNUM:
470 case SIM_ARM_FP1_REGNUM:
471 case SIM_ARM_FP2_REGNUM:
472 case SIM_ARM_FP3_REGNUM:
473 case SIM_ARM_FP4_REGNUM:
474 case SIM_ARM_FP5_REGNUM:
475 case SIM_ARM_FP6_REGNUM:
476 case SIM_ARM_FP7_REGNUM:
477 case SIM_ARM_FPS_REGNUM:
478 ARMul_SetReg (state, state->Mode, rn, frommem (state, memory));
481 case SIM_ARM_PS_REGNUM:
482 state->Cpsr = frommem (state, memory);
483 ARMul_CPSRAltered (state);
486 case SIM_ARM_MAVERIC_COP0R0_REGNUM:
487 case SIM_ARM_MAVERIC_COP0R1_REGNUM:
488 case SIM_ARM_MAVERIC_COP0R2_REGNUM:
489 case SIM_ARM_MAVERIC_COP0R3_REGNUM:
490 case SIM_ARM_MAVERIC_COP0R4_REGNUM:
491 case SIM_ARM_MAVERIC_COP0R5_REGNUM:
492 case SIM_ARM_MAVERIC_COP0R6_REGNUM:
493 case SIM_ARM_MAVERIC_COP0R7_REGNUM:
494 case SIM_ARM_MAVERIC_COP0R8_REGNUM:
495 case SIM_ARM_MAVERIC_COP0R9_REGNUM:
496 case SIM_ARM_MAVERIC_COP0R10_REGNUM:
497 case SIM_ARM_MAVERIC_COP0R11_REGNUM:
498 case SIM_ARM_MAVERIC_COP0R12_REGNUM:
499 case SIM_ARM_MAVERIC_COP0R13_REGNUM:
500 case SIM_ARM_MAVERIC_COP0R14_REGNUM:
501 case SIM_ARM_MAVERIC_COP0R15_REGNUM:
502 memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
503 memory, sizeof (struct maverick_regs));
504 return sizeof (struct maverick_regs);
506 case SIM_ARM_MAVERIC_DSPSC_REGNUM:
507 memcpy (&DSPsc, memory, sizeof DSPsc);
510 case SIM_ARM_IWMMXT_COP0R0_REGNUM:
511 case SIM_ARM_IWMMXT_COP0R1_REGNUM:
512 case SIM_ARM_IWMMXT_COP0R2_REGNUM:
513 case SIM_ARM_IWMMXT_COP0R3_REGNUM:
514 case SIM_ARM_IWMMXT_COP0R4_REGNUM:
515 case SIM_ARM_IWMMXT_COP0R5_REGNUM:
516 case SIM_ARM_IWMMXT_COP0R6_REGNUM:
517 case SIM_ARM_IWMMXT_COP0R7_REGNUM:
518 case SIM_ARM_IWMMXT_COP0R8_REGNUM:
519 case SIM_ARM_IWMMXT_COP0R9_REGNUM:
520 case SIM_ARM_IWMMXT_COP0R10_REGNUM:
521 case SIM_ARM_IWMMXT_COP0R11_REGNUM:
522 case SIM_ARM_IWMMXT_COP0R12_REGNUM:
523 case SIM_ARM_IWMMXT_COP0R13_REGNUM:
524 case SIM_ARM_IWMMXT_COP0R14_REGNUM:
525 case SIM_ARM_IWMMXT_COP0R15_REGNUM:
526 case SIM_ARM_IWMMXT_COP1R0_REGNUM:
527 case SIM_ARM_IWMMXT_COP1R1_REGNUM:
528 case SIM_ARM_IWMMXT_COP1R2_REGNUM:
529 case SIM_ARM_IWMMXT_COP1R3_REGNUM:
530 case SIM_ARM_IWMMXT_COP1R4_REGNUM:
531 case SIM_ARM_IWMMXT_COP1R5_REGNUM:
532 case SIM_ARM_IWMMXT_COP1R6_REGNUM:
533 case SIM_ARM_IWMMXT_COP1R7_REGNUM:
534 case SIM_ARM_IWMMXT_COP1R8_REGNUM:
535 case SIM_ARM_IWMMXT_COP1R9_REGNUM:
536 case SIM_ARM_IWMMXT_COP1R10_REGNUM:
537 case SIM_ARM_IWMMXT_COP1R11_REGNUM:
538 case SIM_ARM_IWMMXT_COP1R12_REGNUM:
539 case SIM_ARM_IWMMXT_COP1R13_REGNUM:
540 case SIM_ARM_IWMMXT_COP1R14_REGNUM:
541 case SIM_ARM_IWMMXT_COP1R15_REGNUM:
542 return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
552 sim_fetch_register (sd, rn, memory, length)
553 SIM_DESC sd ATTRIBUTE_UNUSED;
555 unsigned char *memory;
563 switch ((enum sim_arm_regs) rn)
565 case SIM_ARM_R0_REGNUM:
566 case SIM_ARM_R1_REGNUM:
567 case SIM_ARM_R2_REGNUM:
568 case SIM_ARM_R3_REGNUM:
569 case SIM_ARM_R4_REGNUM:
570 case SIM_ARM_R5_REGNUM:
571 case SIM_ARM_R6_REGNUM:
572 case SIM_ARM_R7_REGNUM:
573 case SIM_ARM_R8_REGNUM:
574 case SIM_ARM_R9_REGNUM:
575 case SIM_ARM_R10_REGNUM:
576 case SIM_ARM_R11_REGNUM:
577 case SIM_ARM_R12_REGNUM:
578 case SIM_ARM_R13_REGNUM:
579 case SIM_ARM_R14_REGNUM:
580 case SIM_ARM_R15_REGNUM: /* PC */
581 regval = ARMul_GetReg (state, state->Mode, rn);
584 case SIM_ARM_FP0_REGNUM:
585 case SIM_ARM_FP1_REGNUM:
586 case SIM_ARM_FP2_REGNUM:
587 case SIM_ARM_FP3_REGNUM:
588 case SIM_ARM_FP4_REGNUM:
589 case SIM_ARM_FP5_REGNUM:
590 case SIM_ARM_FP6_REGNUM:
591 case SIM_ARM_FP7_REGNUM:
592 case SIM_ARM_FPS_REGNUM:
593 memset (memory, 0, length);
596 case SIM_ARM_PS_REGNUM:
597 regval = ARMul_GetCPSR (state);
600 case SIM_ARM_MAVERIC_COP0R0_REGNUM:
601 case SIM_ARM_MAVERIC_COP0R1_REGNUM:
602 case SIM_ARM_MAVERIC_COP0R2_REGNUM:
603 case SIM_ARM_MAVERIC_COP0R3_REGNUM:
604 case SIM_ARM_MAVERIC_COP0R4_REGNUM:
605 case SIM_ARM_MAVERIC_COP0R5_REGNUM:
606 case SIM_ARM_MAVERIC_COP0R6_REGNUM:
607 case SIM_ARM_MAVERIC_COP0R7_REGNUM:
608 case SIM_ARM_MAVERIC_COP0R8_REGNUM:
609 case SIM_ARM_MAVERIC_COP0R9_REGNUM:
610 case SIM_ARM_MAVERIC_COP0R10_REGNUM:
611 case SIM_ARM_MAVERIC_COP0R11_REGNUM:
612 case SIM_ARM_MAVERIC_COP0R12_REGNUM:
613 case SIM_ARM_MAVERIC_COP0R13_REGNUM:
614 case SIM_ARM_MAVERIC_COP0R14_REGNUM:
615 case SIM_ARM_MAVERIC_COP0R15_REGNUM:
616 memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
617 sizeof (struct maverick_regs));
618 return sizeof (struct maverick_regs);
620 case SIM_ARM_MAVERIC_DSPSC_REGNUM:
621 memcpy (memory, & DSPsc, sizeof DSPsc);
624 case SIM_ARM_IWMMXT_COP0R0_REGNUM:
625 case SIM_ARM_IWMMXT_COP0R1_REGNUM:
626 case SIM_ARM_IWMMXT_COP0R2_REGNUM:
627 case SIM_ARM_IWMMXT_COP0R3_REGNUM:
628 case SIM_ARM_IWMMXT_COP0R4_REGNUM:
629 case SIM_ARM_IWMMXT_COP0R5_REGNUM:
630 case SIM_ARM_IWMMXT_COP0R6_REGNUM:
631 case SIM_ARM_IWMMXT_COP0R7_REGNUM:
632 case SIM_ARM_IWMMXT_COP0R8_REGNUM:
633 case SIM_ARM_IWMMXT_COP0R9_REGNUM:
634 case SIM_ARM_IWMMXT_COP0R10_REGNUM:
635 case SIM_ARM_IWMMXT_COP0R11_REGNUM:
636 case SIM_ARM_IWMMXT_COP0R12_REGNUM:
637 case SIM_ARM_IWMMXT_COP0R13_REGNUM:
638 case SIM_ARM_IWMMXT_COP0R14_REGNUM:
639 case SIM_ARM_IWMMXT_COP0R15_REGNUM:
640 case SIM_ARM_IWMMXT_COP1R0_REGNUM:
641 case SIM_ARM_IWMMXT_COP1R1_REGNUM:
642 case SIM_ARM_IWMMXT_COP1R2_REGNUM:
643 case SIM_ARM_IWMMXT_COP1R3_REGNUM:
644 case SIM_ARM_IWMMXT_COP1R4_REGNUM:
645 case SIM_ARM_IWMMXT_COP1R5_REGNUM:
646 case SIM_ARM_IWMMXT_COP1R6_REGNUM:
647 case SIM_ARM_IWMMXT_COP1R7_REGNUM:
648 case SIM_ARM_IWMMXT_COP1R8_REGNUM:
649 case SIM_ARM_IWMMXT_COP1R9_REGNUM:
650 case SIM_ARM_IWMMXT_COP1R10_REGNUM:
651 case SIM_ARM_IWMMXT_COP1R11_REGNUM:
652 case SIM_ARM_IWMMXT_COP1R12_REGNUM:
653 case SIM_ARM_IWMMXT_COP1R13_REGNUM:
654 case SIM_ARM_IWMMXT_COP1R14_REGNUM:
655 case SIM_ARM_IWMMXT_COP1R15_REGNUM:
656 return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
664 tomem (state, memory, regval);
674 #ifdef SIM_TARGET_SWITCHES
676 static void sim_target_parse_arg_array PARAMS ((char **));
681 unsigned int swi_mask;
684 #define SWI_SWITCH "--swi-support"
686 static swi_options options[] =
689 { "demon", SWI_MASK_DEMON },
690 { "angel", SWI_MASK_ANGEL },
691 { "redboot", SWI_MASK_REDBOOT },
694 { "DEMON", SWI_MASK_DEMON },
695 { "ANGEL", SWI_MASK_ANGEL },
696 { "REDBOOT", SWI_MASK_REDBOOT },
702 sim_target_parse_command_line (argc, argv)
708 for (i = 1; i < argc; i++)
710 char * ptr = argv[i];
713 if ((ptr == NULL) || (* ptr != '-'))
716 if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0)
719 if (ptr[sizeof SWI_SWITCH - 1] == 0)
721 /* Remove this option from the argv array. */
722 for (arg = i; arg < argc; arg ++)
723 argv[arg] = argv[arg + 1];
729 ptr += sizeof SWI_SWITCH;
737 for (i = sizeof options / sizeof options[0]; i--;)
738 if (strncmp (ptr, options[i].swi_option,
739 strlen (options[i].swi_option)) == 0)
741 swi_mask |= options[i].swi_mask;
742 ptr += strlen (options[i].swi_option);
755 fprintf (stderr, "Ignoring swi options: %s\n", ptr);
757 /* Remove this option from the argv array. */
758 for (arg = i; arg < argc; arg ++)
759 argv[arg] = argv[arg + 1];
767 sim_target_parse_arg_array (argv)
772 for (i = 0; argv[i]; i++)
775 sim_target_parse_command_line (i, argv);
779 sim_target_display_usage (help)
782 FILE *stream = help ? stdout : stderr;
784 fprintf (stream, "%s=<list> Comma seperated list of SWI protocols to supoport.\n\
785 This list can contain: NONE, DEMON, ANGEL, REDBOOT and/or ALL.\n",
791 sim_open (kind, ptr, abfd, argv)
798 if (myname) free (myname);
799 myname = (char *) xstrdup (argv[0]);
802 #ifdef SIM_TARGET_SWITCHES
803 sim_target_parse_arg_array (argv);
806 /* Decide upon the endian-ness of the processor.
807 If we can, get the information from the bfd itself.
808 Otherwise look to see if we have been given a command
809 line switch that tells us. Otherwise default to little endian. */
811 big_endian = bfd_big_endian (abfd);
812 else if (argv[1] != NULL)
816 /* Scan for endian-ness and memory-size switches. */
817 for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++)
818 if (argv[i][0] == '-' && argv[i][1] == 'E')
822 if ((c = argv[i][2]) == 0)
831 sim_callback->printf_filtered
832 (sim_callback, "No argument to -E option provided\n");
846 sim_callback->printf_filtered
847 (sim_callback, "Unrecognised argument to -E option\n");
851 else if (argv[i][0] == '-' && argv[i][1] == 'm')
853 if (argv[i][2] != '\0')
854 sim_size (atoi (&argv[i][2]));
855 else if (argv[i + 1] != NULL)
857 sim_size (atoi (argv[i + 1]));
862 sim_callback->printf_filtered (sim_callback,
863 "Missing argument to -m option\n");
874 sim_close (sd, quitting)
875 SIM_DESC sd ATTRIBUTE_UNUSED;
876 int quitting ATTRIBUTE_UNUSED;
884 sim_load (sd, prog, abfd, from_tty)
888 int from_tty ATTRIBUTE_UNUSED;
892 prog_bfd = sim_load_file (sd, myname, sim_callback, prog, abfd,
893 sim_kind == SIM_OPEN_DEBUG, 0, sim_write);
894 if (prog_bfd == NULL)
896 ARMul_SetPC (state, bfd_get_start_address (prog_bfd));
898 bfd_close (prog_bfd);
903 sim_stop_reason (sd, reason, sigrc)
904 SIM_DESC sd ATTRIBUTE_UNUSED;
905 enum sim_stop *reason;
910 *reason = sim_stopped;
911 *sigrc = GDB_SIGNAL_INT;
913 else if (state->EndCondition == 0)
915 *reason = sim_exited;
916 *sigrc = state->Reg[0] & 255;
920 *reason = sim_stopped;
921 if (state->EndCondition == RDIError_BreakpointReached)
922 *sigrc = GDB_SIGNAL_TRAP;
923 else if ( state->EndCondition == RDIError_DataAbort
924 || state->EndCondition == RDIError_AddressException)
925 *sigrc = GDB_SIGNAL_BUS;
932 sim_do_command (sd, cmd)
933 SIM_DESC sd ATTRIBUTE_UNUSED;
934 char *cmd ATTRIBUTE_UNUSED;
936 (*sim_callback->printf_filtered)
938 "This simulator does not accept any commands.\n");
942 sim_set_callbacks (ptr)
949 sim_complete_command (SIM_DESC sd, char *text, char *word)