1 /* iwmmxt.c -- Intel(r) Wireless MMX(tm) technology co-processor interface.
2 Copyright (C) 2002, 2007 Free Software Foundation, Inc.
3 Contributed by matthew green (mrg@redhat.com).
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 /* Intel(r) Wireless MMX(tm) technology co-processor.
27 It uses co-processor numbers (0 and 1). There are 16 vector registers wRx
28 and 16 control registers wCx. Co-processors 0 and 1 are used in MCR/MRC
29 to access wRx and wCx respectively. */
31 static ARMdword wR[16];
32 static ARMword wC[16] = { 0x69051010 };
34 #define SUBSTR(w,t,m,n) ((t)(w << ((sizeof (t) * 8 - 1) - (n))) \
35 >> (((sizeof (t) * 8 - 1) - (n)) + (m)))
36 #define wCBITS(w,x,y) SUBSTR (wC[w], ARMword, x, y)
37 #define wRBITS(w,x,y) SUBSTR (wR[w], ARMdword, x, y)
47 /* Bits in the wCon register. */
48 #define WCON_CUP (1 << 0)
49 #define WCON_MUP (1 << 1)
51 /* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */
52 #define SIMD8_SET(x, v, n, b) (x) |= ((v != 0) << ((((b) + 1) * 4) + (n)))
53 #define SIMD16_SET(x, v, n, h) (x) |= ((v != 0) << ((((h) + 1) * 8) + (n)))
54 #define SIMD32_SET(x, v, n, w) (x) |= ((v != 0) << ((((w) + 1) * 16) + (n)))
55 #define SIMD64_SET(x, v, n) (x) |= ((v != 0) << (32 + (n)))
57 /* Flags to pass as "n" above. */
63 /* Various status bit macros. */
64 #define NBIT8(x) ((x) & 0x80)
65 #define NBIT16(x) ((x) & 0x8000)
66 #define NBIT32(x) ((x) & 0x80000000)
67 #define NBIT64(x) ((x) & 0x8000000000000000ULL)
68 #define ZBIT8(x) (((x) & 0xff) == 0)
69 #define ZBIT16(x) (((x) & 0xffff) == 0)
70 #define ZBIT32(x) (((x) & 0xffffffff) == 0)
71 #define ZBIT64(x) (x == 0)
73 /* Access byte/half/word "n" of register "x". */
74 #define wRBYTE(x,n) wRBITS ((x), (n) * 8, (n) * 8 + 7)
75 #define wRHALF(x,n) wRBITS ((x), (n) * 16, (n) * 16 + 15)
76 #define wRWORD(x,n) wRBITS ((x), (n) * 32, (n) * 32 + 31)
78 /* Macro to handle how the G bit selects wCGR registers. */
79 #define DECODE_G_BIT(state, instr, shift) \
85 if (BIT (8)) /* G */ \
87 if (reg < wCGR0 || reg > wCGR3) \
89 ARMul_UndefInstr (state, instr); \
100 /* Index calculations for the satrv[] array. */
101 #define BITIDX8(x) (x)
102 #define BITIDX16(x) (((x) + 1) * 2 - 1)
103 #define BITIDX32(x) (((x) + 1) * 4 - 1)
105 /* Sign extension macros. */
106 #define EXTEND8(a) ((a) & 0x80 ? ((a) | 0xffffff00) : (a))
107 #define EXTEND16(a) ((a) & 0x8000 ? ((a) | 0xffff0000) : (a))
108 #define EXTEND32(a) ((a) & 0x80000000ULL ? ((a) | 0xffffffff00000000ULL) : (a))
110 /* Set the wCSSF from 8 values. */
111 #define SET_wCSSF(a,b,c,d,e,f,g,h) \
112 wC[wCSSF] = (((h) != 0) << 7) | (((g) != 0) << 6) \
113 | (((f) != 0) << 5) | (((e) != 0) << 4) \
114 | (((d) != 0) << 3) | (((c) != 0) << 2) \
115 | (((b) != 0) << 1) | (((a) != 0) << 0);
117 /* Set the wCSSR from an array with 8 values. */
118 #define SET_wCSSFvec(v) \
119 SET_wCSSF((v)[0],(v)[1],(v)[2],(v)[3],(v)[4],(v)[5],(v)[6],(v)[7])
121 /* Size qualifiers for vector operations. */
127 /* Saturation qualifiers for vector operations. */
128 #define NoSaturation 0
129 #define UnsignedSaturation 1
130 #define SignedSaturation 3
134 static ARMword Add32 (ARMword, ARMword, int *, int *, ARMword);
135 static ARMdword AddS32 (ARMdword, ARMdword, int *, int *);
136 static ARMdword AddU32 (ARMdword, ARMdword, int *, int *);
137 static ARMword AddS16 (ARMword, ARMword, int *, int *);
138 static ARMword AddU16 (ARMword, ARMword, int *, int *);
139 static ARMword AddS8 (ARMword, ARMword, int *, int *);
140 static ARMword AddU8 (ARMword, ARMword, int *, int *);
141 static ARMword Sub32 (ARMword, ARMword, int *, int *, ARMword);
142 static ARMdword SubS32 (ARMdword, ARMdword, int *, int *);
143 static ARMdword SubU32 (ARMdword, ARMdword, int *, int *);
144 static ARMword SubS16 (ARMword, ARMword, int *, int *);
145 static ARMword SubS8 (ARMword, ARMword, int *, int *);
146 static ARMword SubU16 (ARMword, ARMword, int *, int *);
147 static ARMword SubU8 (ARMword, ARMword, int *, int *);
148 static unsigned char IwmmxtSaturateU8 (signed short, int *);
149 static signed char IwmmxtSaturateS8 (signed short, int *);
150 static unsigned short IwmmxtSaturateU16 (signed int, int *);
151 static signed short IwmmxtSaturateS16 (signed int, int *);
152 static unsigned long IwmmxtSaturateU32 (signed long long, int *);
153 static signed long IwmmxtSaturateS32 (signed long long, int *);
154 static ARMword Compute_Iwmmxt_Address (ARMul_State *, ARMword, int *);
155 static ARMdword Iwmmxt_Load_Double_Word (ARMul_State *, ARMword);
156 static ARMword Iwmmxt_Load_Word (ARMul_State *, ARMword);
157 static ARMword Iwmmxt_Load_Half_Word (ARMul_State *, ARMword);
158 static ARMword Iwmmxt_Load_Byte (ARMul_State *, ARMword);
159 static void Iwmmxt_Store_Double_Word (ARMul_State *, ARMword, ARMdword);
160 static void Iwmmxt_Store_Word (ARMul_State *, ARMword, ARMword);
161 static void Iwmmxt_Store_Half_Word (ARMul_State *, ARMword, ARMword);
162 static void Iwmmxt_Store_Byte (ARMul_State *, ARMword, ARMword);
163 static int Process_Instruction (ARMul_State *, ARMword);
165 static int TANDC (ARMul_State *, ARMword);
166 static int TBCST (ARMul_State *, ARMword);
167 static int TEXTRC (ARMul_State *, ARMword);
168 static int TEXTRM (ARMul_State *, ARMword);
169 static int TINSR (ARMul_State *, ARMword);
170 static int TMCR (ARMul_State *, ARMword);
171 static int TMCRR (ARMul_State *, ARMword);
172 static int TMIA (ARMul_State *, ARMword);
173 static int TMIAPH (ARMul_State *, ARMword);
174 static int TMIAxy (ARMul_State *, ARMword);
175 static int TMOVMSK (ARMul_State *, ARMword);
176 static int TMRC (ARMul_State *, ARMword);
177 static int TMRRC (ARMul_State *, ARMword);
178 static int TORC (ARMul_State *, ARMword);
179 static int WACC (ARMul_State *, ARMword);
180 static int WADD (ARMul_State *, ARMword);
181 static int WALIGNI (ARMword);
182 static int WALIGNR (ARMul_State *, ARMword);
183 static int WAND (ARMword);
184 static int WANDN (ARMword);
185 static int WAVG2 (ARMword);
186 static int WCMPEQ (ARMul_State *, ARMword);
187 static int WCMPGT (ARMul_State *, ARMword);
188 static int WLDR (ARMul_State *, ARMword);
189 static int WMAC (ARMword);
190 static int WMADD (ARMword);
191 static int WMAX (ARMul_State *, ARMword);
192 static int WMIN (ARMul_State *, ARMword);
193 static int WMUL (ARMword);
194 static int WOR (ARMword);
195 static int WPACK (ARMul_State *, ARMword);
196 static int WROR (ARMul_State *, ARMword);
197 static int WSAD (ARMword);
198 static int WSHUFH (ARMword);
199 static int WSLL (ARMul_State *, ARMword);
200 static int WSRA (ARMul_State *, ARMword);
201 static int WSRL (ARMul_State *, ARMword);
202 static int WSTR (ARMul_State *, ARMword);
203 static int WSUB (ARMul_State *, ARMword);
204 static int WUNPCKEH (ARMul_State *, ARMword);
205 static int WUNPCKEL (ARMul_State *, ARMword);
206 static int WUNPCKIH (ARMul_State *, ARMword);
207 static int WUNPCKIL (ARMul_State *, ARMword);
208 static int WXOR (ARMword);
210 /* This function does the work of adding two 32bit values
211 together, and calculating if a carry has occurred. */
220 ARMword result = (a1 + a2);
221 unsigned int uresult = (unsigned int) result;
222 unsigned int ua1 = (unsigned int) a1;
224 /* If (result == a1) and (a2 == 0),
225 or (result > a2) then we have no carry. */
226 * carry_ptr = ((uresult == ua1) ? (a2 != 0) : (uresult < ua1));
228 /* Overflow occurs when both arguments are the
229 same sign, but the result is a different sign. */
230 * overflow_ptr = ( ( (result & sign_mask) && !(a1 & sign_mask) && !(a2 & sign_mask))
231 || (!(result & sign_mask) && (a1 & sign_mask) && (a2 & sign_mask)));
237 AddS32 (ARMdword a1, ARMdword a2, int * carry_ptr, int * overflow_ptr)
240 unsigned int uresult;
247 uresult = (unsigned int) result;
248 ua1 = (unsigned int) a1;
250 * carry_ptr = ((uresult == a1) ? (a2 != 0) : (uresult < ua1));
252 * overflow_ptr = ( ( (result & 0x80000000ULL) && !(a1 & 0x80000000ULL) && !(a2 & 0x80000000ULL))
253 || (!(result & 0x80000000ULL) && (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL)));
259 AddU32 (ARMdword a1, ARMdword a2, int * carry_ptr, int * overflow_ptr)
262 unsigned int uresult;
269 uresult = (unsigned int) result;
270 ua1 = (unsigned int) a1;
272 * carry_ptr = ((uresult == a1) ? (a2 != 0) : (uresult < ua1));
274 * overflow_ptr = ( ( (result & 0x80000000ULL) && !(a1 & 0x80000000ULL) && !(a2 & 0x80000000ULL))
275 || (!(result & 0x80000000ULL) && (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL)));
281 AddS16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
286 return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x8000);
290 AddU16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
295 return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x8000);
299 AddS8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
304 return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x80);
308 AddU8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
313 return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x80);
323 ARMword result = (a1 - a2);
324 unsigned int ua1 = (unsigned int) a1;
325 unsigned int ua2 = (unsigned int) a2;
327 /* A borrow occurs if a2 is (unsigned) larger than a1.
328 However the carry flag is *cleared* if a borrow occurs. */
329 * borrow_ptr = ! (ua2 > ua1);
331 /* Overflow occurs when a negative number is subtracted from a
332 positive number and the result is negative or a positive
333 number is subtracted from a negative number and the result is
335 * overflow_ptr = ( (! (a1 & sign_mask) && (a2 & sign_mask) && (result & sign_mask))
336 || ((a1 & sign_mask) && ! (a2 & sign_mask) && ! (result & sign_mask)));
342 SubS32 (ARMdword a1, ARMdword a2, int * borrow_ptr, int * overflow_ptr)
352 ua1 = (unsigned int) a1;
353 ua2 = (unsigned int) a2;
355 * borrow_ptr = ! (ua2 > ua1);
357 * overflow_ptr = ( (! (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL) && (result & 0x80000000ULL))
358 || ((a1 & 0x80000000ULL) && ! (a2 & 0x80000000ULL) && ! (result & 0x80000000ULL)));
364 SubS16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
369 return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x8000);
373 SubS8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
378 return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x80);
382 SubU16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
387 return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x8000);
391 SubU8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
396 return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x80);
400 SubU32 (ARMdword a1, ARMdword a2, int * borrow_ptr, int * overflow_ptr)
410 ua1 = (unsigned int) a1;
411 ua2 = (unsigned int) a2;
413 * borrow_ptr = ! (ua2 > ua1);
415 * overflow_ptr = ( (! (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL) && (result & 0x80000000ULL))
416 || ((a1 & 0x80000000ULL) && ! (a2 & 0x80000000ULL) && ! (result & 0x80000000ULL)));
421 /* For the saturation. */
424 IwmmxtSaturateU8 (signed short val, int * sat)
447 IwmmxtSaturateS8 (signed short val, int * sat)
469 static unsigned short
470 IwmmxtSaturateU16 (signed int val, int * sat)
479 else if (val > 0xffff)
493 IwmmxtSaturateS16 (signed int val, int * sat)
502 else if (val > 0x7fff)
516 IwmmxtSaturateU32 (signed long long val, int * sat)
525 else if (val > 0xffffffff)
532 rv = val & 0xffffffff;
539 IwmmxtSaturateS32 (signed long long val, int * sat)
543 if (val < -0x80000000LL)
548 else if (val > 0x7fffffff)
555 rv = val & 0xffffffff;
561 /* Intel(r) Wireless MMX(tm) technology Acessor functions. */
564 IwmmxtLDC (ARMul_State * state ATTRIBUTE_UNUSED,
565 unsigned type ATTRIBUTE_UNUSED,
573 IwmmxtSTC (ARMul_State * state ATTRIBUTE_UNUSED,
574 unsigned type ATTRIBUTE_UNUSED,
582 IwmmxtMRC (ARMul_State * state ATTRIBUTE_UNUSED,
583 unsigned type ATTRIBUTE_UNUSED,
591 IwmmxtMCR (ARMul_State * state ATTRIBUTE_UNUSED,
592 unsigned type ATTRIBUTE_UNUSED,
600 IwmmxtCDP (ARMul_State * state, unsigned type, ARMword instr)
605 /* Intel(r) Wireless MMX(tm) technology instruction implementations. */
608 TANDC (ARMul_State * state, ARMword instr)
612 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
616 fprintf (stderr, "tandc\n");
619 /* The Rd field must be r15. */
620 if (BITS (12, 15) != 15)
623 /* The CRn field must be r3. */
624 if (BITS (16, 19) != 3)
627 /* The CRm field must be r0. */
628 if (BITS (0, 3) != 0)
631 cpsr = ARMul_GetCPSR (state) & 0x0fffffff;
633 switch (BITS (22, 23))
636 cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 24, 27)
637 & wCBITS (wCASF, 20, 23) & wCBITS (wCASF, 16, 19)
638 & wCBITS (wCASF, 12, 15) & wCBITS (wCASF, 8, 11)
639 & wCBITS (wCASF, 4, 7) & wCBITS (wCASF, 0, 3)) << 28);
643 cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 20, 23)
644 & wCBITS (wCASF, 12, 15) & wCBITS (wCASF, 4, 7)) << 28);
648 cpsr |= ((wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 12, 15)) << 28);
652 ARMul_UndefInstr (state, instr);
656 ARMul_SetCPSR (state, cpsr);
662 TBCST (ARMul_State * state, ARMword instr)
667 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
671 fprintf (stderr, "tbcst\n");
674 Rn = state->Reg [BITS (12, 15)];
675 if (BITS (12, 15) == 15)
684 wR [wRd] = (Rn << 56) | (Rn << 48) | (Rn << 40) | (Rn << 32)
685 | (Rn << 24) | (Rn << 16) | (Rn << 8) | Rn;
690 wR [wRd] = (Rn << 48) | (Rn << 32) | (Rn << 16) | Rn;
695 wR [wRd] = (Rn << 32) | Rn;
699 ARMul_UndefInstr (state, instr);
703 wC [wCon] |= WCON_MUP;
708 TEXTRC (ARMul_State * state, ARMword instr)
713 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
717 fprintf (stderr, "textrc\n");
720 /* The Rd field must be r15. */
721 if (BITS (12, 15) != 15)
724 /* The CRn field must be r3. */
725 if (BITS (16, 19) != 3)
728 /* The CRm field must be 0xxx. */
732 selector = BITS (0, 2);
733 cpsr = ARMul_GetCPSR (state) & 0x0fffffff;
735 switch (BITS (22, 23))
737 case Bqual: selector *= 4; break;
738 case Hqual: selector = ((selector & 3) * 8) + 4; break;
739 case Wqual: selector = ((selector & 1) * 16) + 12; break;
742 ARMul_UndefInstr (state, instr);
746 cpsr |= wCBITS (wCASF, selector, selector + 3) << 28;
747 ARMul_SetCPSR (state, cpsr);
753 TEXTRM (ARMul_State * state, ARMword instr)
760 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
764 fprintf (stderr, "textrm\n");
769 offset = BITS (0, 2);
771 switch (BITS (22, 23))
775 Rd = wRBITS (wRn, offset, offset + 7);
781 offset = (offset & 3) * 16;
782 Rd = wRBITS (wRn, offset, offset + 15);
788 offset = (offset & 1) * 32;
789 Rd = wRBITS (wRn, offset, offset + 31);
793 ARMul_UndefInstr (state, instr);
797 if (BITS (12, 15) == 15)
798 ARMul_UndefInstr (state, instr);
800 state->Reg [BITS (12, 15)] = Rd;
806 TINSR (ARMul_State * state, ARMword instr)
812 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
816 fprintf (stderr, "tinsr\n");
820 data = state->Reg [BITS (12, 15)];
821 offset = BITS (0, 2);
829 case 0: wR [wRd] = data | (wRBITS (wRd, 8, 63) << 8); break;
830 case 1: wR [wRd] = wRBITS (wRd, 0, 7) | (data << 8) | (wRBITS (wRd, 16, 63) << 16); break;
831 case 2: wR [wRd] = wRBITS (wRd, 0, 15) | (data << 16) | (wRBITS (wRd, 24, 63) << 24); break;
832 case 3: wR [wRd] = wRBITS (wRd, 0, 23) | (data << 24) | (wRBITS (wRd, 32, 63) << 32); break;
833 case 4: wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32) | (wRBITS (wRd, 40, 63) << 40); break;
834 case 5: wR [wRd] = wRBITS (wRd, 0, 39) | (data << 40) | (wRBITS (wRd, 48, 63) << 48); break;
835 case 6: wR [wRd] = wRBITS (wRd, 0, 47) | (data << 48) | (wRBITS (wRd, 56, 63) << 56); break;
836 case 7: wR [wRd] = wRBITS (wRd, 0, 55) | (data << 56); break;
845 case 0: wR [wRd] = data | (wRBITS (wRd, 16, 63) << 16); break;
846 case 1: wR [wRd] = wRBITS (wRd, 0, 15) | (data << 16) | (wRBITS (wRd, 32, 63) << 32); break;
847 case 2: wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32) | (wRBITS (wRd, 48, 63) << 48); break;
848 case 3: wR [wRd] = wRBITS (wRd, 0, 47) | (data << 48); break;
854 wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32);
856 wR [wRd] = (wRBITS (wRd, 32, 63) << 32) | data;
860 ARMul_UndefInstr (state, instr);
864 wC [wCon] |= WCON_MUP;
869 TMCR (ARMul_State * state, ARMword instr)
874 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
878 fprintf (stderr, "tmcr\n");
881 if (BITS (0, 3) != 0)
884 val = state->Reg [BITS (12, 15)];
885 if (BITS (12, 15) == 15)
888 wCreg = BITS (16, 19);
893 /* The wCID register is read only. */
897 /* Writing to the MUP or CUP bits clears them. */
898 wC [wCon] &= ~ (val & 0x3);
902 /* Only the bottom 8 bits can be written to.
903 The higher bits write as zero. */
904 wC [wCSSF] = (val & 0xff);
905 wC [wCon] |= WCON_CUP;
910 wC [wCon] |= WCON_CUP;
918 TMCRR (ARMul_State * state, ARMword instr)
920 ARMdword RdHi = state->Reg [BITS (16, 19)];
921 ARMword RdLo = state->Reg [BITS (12, 15)];
923 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
927 fprintf (stderr, "tmcrr\n");
930 if ((BITS (16, 19) == 15) || (BITS (12, 15) == 15))
933 wR [BITS (0, 3)] = (RdHi << 32) | RdLo;
935 wC [wCon] |= WCON_MUP;
941 TMIA (ARMul_State * state, ARMword instr)
943 signed long long a, b;
945 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
949 fprintf (stderr, "tmia\n");
952 if ((BITS (0, 3) == 15) || (BITS (12, 15) == 15))
954 ARMul_UndefInstr (state, instr);
958 a = state->Reg [BITS (0, 3)];
959 b = state->Reg [BITS (12, 15)];
964 wR [BITS (5, 8)] += a * b;
965 wC [wCon] |= WCON_MUP;
971 TMIAPH (ARMul_State * state, ARMword instr)
973 signed long a, b, result;
975 ARMword Rm = state->Reg [BITS (0, 3)];
976 ARMword Rs = state->Reg [BITS (12, 15)];
978 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
982 fprintf (stderr, "tmiaph\n");
985 if (BITS (0, 3) == 15 || BITS (12, 15) == 15)
987 ARMul_UndefInstr (state, instr);
991 a = SUBSTR (Rs, ARMword, 16, 31);
992 b = SUBSTR (Rm, ARMword, 16, 31);
1002 wR [BITS (5, 8)] += r;
1004 a = SUBSTR (Rs, ARMword, 0, 15);
1005 b = SUBSTR (Rm, ARMword, 0, 15);
1015 wR [BITS (5, 8)] += r;
1016 wC [wCon] |= WCON_MUP;
1022 TMIAxy (ARMul_State * state, ARMword instr)
1028 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1032 fprintf (stderr, "tmiaxy\n");
1035 if (BITS (0, 3) == 15 || BITS (12, 15) == 15)
1037 ARMul_UndefInstr (state, instr);
1041 Rm = state->Reg [BITS (0, 3)];
1047 Rs = state->Reg [BITS (12, 15)];
1062 if (temp & (1 << 31))
1065 wR [BITS (5, 8)] += temp;
1066 wC [wCon] |= WCON_MUP;
1072 TMOVMSK (ARMul_State * state, ARMword instr)
1077 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1081 fprintf (stderr, "tmovmsk\n");
1084 /* The CRm field must be r0. */
1085 if (BITS (0, 3) != 0)
1088 wRn = BITS (16, 19);
1090 switch (BITS (22, 23))
1093 result = ( (wRBITS (wRn, 63, 63) << 7)
1094 | (wRBITS (wRn, 55, 55) << 6)
1095 | (wRBITS (wRn, 47, 47) << 5)
1096 | (wRBITS (wRn, 39, 39) << 4)
1097 | (wRBITS (wRn, 31, 31) << 3)
1098 | (wRBITS (wRn, 23, 23) << 2)
1099 | (wRBITS (wRn, 15, 15) << 1)
1100 | (wRBITS (wRn, 7, 7) << 0));
1104 result = ( (wRBITS (wRn, 63, 63) << 3)
1105 | (wRBITS (wRn, 47, 47) << 2)
1106 | (wRBITS (wRn, 31, 31) << 1)
1107 | (wRBITS (wRn, 15, 15) << 0));
1111 result = (wRBITS (wRn, 63, 63) << 1) | wRBITS (wRn, 31, 31);
1115 ARMul_UndefInstr (state, instr);
1119 state->Reg [BITS (12, 15)] = result;
1125 TMRC (ARMul_State * state, ARMword instr)
1127 int reg = BITS (12, 15);
1129 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1133 fprintf (stderr, "tmrc\n");
1136 if (BITS (0, 3) != 0)
1140 ARMul_UndefInstr (state, instr);
1142 state->Reg [reg] = wC [BITS (16, 19)];
1148 TMRRC (ARMul_State * state, ARMword instr)
1150 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1154 fprintf (stderr, "tmrrc\n");
1157 if ((BITS (16, 19) == 15) || (BITS (12, 15) == 15) || (BITS (4, 11) != 0))
1158 ARMul_UndefInstr (state, instr);
1161 state->Reg [BITS (16, 19)] = wRBITS (BITS (0, 3), 32, 63);
1162 state->Reg [BITS (12, 15)] = wRBITS (BITS (0, 3), 0, 31);
1169 TORC (ARMul_State * state, ARMword instr)
1171 ARMword cpsr = ARMul_GetCPSR (state);
1173 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1177 fprintf (stderr, "torc\n");
1180 /* The Rd field must be r15. */
1181 if (BITS (12, 15) != 15)
1184 /* The CRn field must be r3. */
1185 if (BITS (16, 19) != 3)
1188 /* The CRm field must be r0. */
1189 if (BITS (0, 3) != 0)
1194 switch (BITS (22, 23))
1197 cpsr |= ( (wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 24, 27)
1198 | wCBITS (wCASF, 20, 23) | wCBITS (wCASF, 16, 19)
1199 | wCBITS (wCASF, 12, 15) | wCBITS (wCASF, 8, 11)
1200 | wCBITS (wCASF, 4, 7) | wCBITS (wCASF, 0, 3)) << 28);
1204 cpsr |= ( (wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 20, 23)
1205 | wCBITS (wCASF, 12, 15) | wCBITS (wCASF, 4, 7)) << 28);
1209 cpsr |= ((wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 12, 15)) << 28);
1213 ARMul_UndefInstr (state, instr);
1217 ARMul_SetCPSR (state, cpsr);
1223 WACC (ARMul_State * state, ARMword instr)
1227 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1231 fprintf (stderr, "wacc\n");
1234 wRn = BITS (16, 19);
1236 switch (BITS (22, 23))
1239 wR [BITS (12, 15)] =
1240 wRBITS (wRn, 56, 63) + wRBITS (wRn, 48, 55)
1241 + wRBITS (wRn, 40, 47) + wRBITS (wRn, 32, 39)
1242 + wRBITS (wRn, 24, 31) + wRBITS (wRn, 16, 23)
1243 + wRBITS (wRn, 8, 15) + wRBITS (wRn, 0, 7);
1247 wR [BITS (12, 15)] =
1248 wRBITS (wRn, 48, 63) + wRBITS (wRn, 32, 47)
1249 + wRBITS (wRn, 16, 31) + wRBITS (wRn, 0, 15);
1253 wR [BITS (12, 15)] = wRBITS (wRn, 32, 63) + wRBITS (wRn, 0, 31);
1257 ARMul_UndefInstr (state, instr);
1261 wC [wCon] |= WCON_MUP;
1266 WADD (ARMul_State * state, ARMword instr)
1277 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1281 fprintf (stderr, "wadd\n");
1284 /* Add two numbers using the specified function,
1285 leaving setting the carry bit as required. */
1286 #define ADDx(x, y, m, f) \
1287 (*f) (wRBITS (BITS (16, 19), (x), (y)) & (m), \
1288 wRBITS (BITS ( 0, 3), (x), (y)) & (m), \
1289 & carry, & overflow)
1291 switch (BITS (22, 23))
1294 for (i = 0; i < 8; i++)
1296 switch (BITS (20, 21))
1299 s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddS8);
1300 satrv [BITIDX8 (i)] = 0;
1301 r |= (s & 0xff) << (i * 8);
1302 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
1303 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
1304 SIMD8_SET (psr, carry, SIMD_CBIT, i);
1305 SIMD8_SET (psr, overflow, SIMD_VBIT, i);
1308 case UnsignedSaturation:
1309 s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddU8);
1310 x = IwmmxtSaturateU8 (s, satrv + BITIDX8 (i));
1311 r |= (x & 0xff) << (i * 8);
1312 SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i);
1313 SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i);
1314 if (! satrv [BITIDX8 (i)])
1316 SIMD8_SET (psr, carry, SIMD_CBIT, i);
1317 SIMD8_SET (psr, overflow, SIMD_VBIT, i);
1321 case SignedSaturation:
1322 s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddS8);
1323 x = IwmmxtSaturateS8 (s, satrv + BITIDX8 (i));
1324 r |= (x & 0xff) << (i * 8);
1325 SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i);
1326 SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i);
1327 if (! satrv [BITIDX8 (i)])
1329 SIMD8_SET (psr, carry, SIMD_CBIT, i);
1330 SIMD8_SET (psr, overflow, SIMD_VBIT, i);
1335 ARMul_UndefInstr (state, instr);
1342 satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0;
1344 for (i = 0; i < 4; i++)
1346 switch (BITS (20, 21))
1349 s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddS16);
1350 satrv [BITIDX16 (i)] = 0;
1351 r |= (s & 0xffff) << (i * 16);
1352 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
1353 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
1354 SIMD16_SET (psr, carry, SIMD_CBIT, i);
1355 SIMD16_SET (psr, overflow, SIMD_VBIT, i);
1358 case UnsignedSaturation:
1359 s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddU16);
1360 x = IwmmxtSaturateU16 (s, satrv + BITIDX16 (i));
1361 r |= (x & 0xffff) << (i * 16);
1362 SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i);
1363 SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i);
1364 if (! satrv [BITIDX16 (i)])
1366 SIMD16_SET (psr, carry, SIMD_CBIT, i);
1367 SIMD16_SET (psr, overflow, SIMD_VBIT, i);
1371 case SignedSaturation:
1372 s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddS16);
1373 x = IwmmxtSaturateS16 (s, satrv + BITIDX16 (i));
1374 r |= (x & 0xffff) << (i * 16);
1375 SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i);
1376 SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i);
1377 if (! satrv [BITIDX16 (i)])
1379 SIMD16_SET (psr, carry, SIMD_CBIT, i);
1380 SIMD16_SET (psr, overflow, SIMD_VBIT, i);
1385 ARMul_UndefInstr (state, instr);
1392 satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0;
1394 for (i = 0; i < 2; i++)
1396 switch (BITS (20, 21))
1399 s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddS32);
1400 satrv [BITIDX32 (i)] = 0;
1401 r |= (s & 0xffffffff) << (i * 32);
1402 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
1403 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
1404 SIMD32_SET (psr, carry, SIMD_CBIT, i);
1405 SIMD32_SET (psr, overflow, SIMD_VBIT, i);
1408 case UnsignedSaturation:
1409 s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddU32);
1410 x = IwmmxtSaturateU32 (s, satrv + BITIDX32 (i));
1411 r |= (x & 0xffffffff) << (i * 32);
1412 SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i);
1413 SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i);
1414 if (! satrv [BITIDX32 (i)])
1416 SIMD32_SET (psr, carry, SIMD_CBIT, i);
1417 SIMD32_SET (psr, overflow, SIMD_VBIT, i);
1421 case SignedSaturation:
1422 s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddS32);
1423 x = IwmmxtSaturateS32 (s, satrv + BITIDX32 (i));
1424 r |= (x & 0xffffffff) << (i * 32);
1425 SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i);
1426 SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i);
1427 if (! satrv [BITIDX32 (i)])
1429 SIMD32_SET (psr, carry, SIMD_CBIT, i);
1430 SIMD32_SET (psr, overflow, SIMD_VBIT, i);
1435 ARMul_UndefInstr (state, instr);
1442 ARMul_UndefInstr (state, instr);
1447 wR [BITS (12, 15)] = r;
1448 wC [wCon] |= (WCON_MUP | WCON_CUP);
1450 SET_wCSSFvec (satrv);
1458 WALIGNI (ARMword instr)
1460 int shift = BITS (20, 22) * 8;
1462 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1466 fprintf (stderr, "waligni\n");
1470 wR [BITS (12, 15)] =
1471 wRBITS (BITS (16, 19), shift, 63)
1472 | (wRBITS (BITS (0, 3), 0, shift) << ((64 - shift)));
1474 wR [BITS (12, 15)] = wR [BITS (16, 19)];
1476 wC [wCon] |= WCON_MUP;
1481 WALIGNR (ARMul_State * state, ARMword instr)
1483 int shift = (wC [BITS (20, 21) + 8] & 0x7) * 8;
1485 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1489 fprintf (stderr, "walignr\n");
1493 wR [BITS (12, 15)] =
1494 wRBITS (BITS (16, 19), shift, 63)
1495 | (wRBITS (BITS (0, 3), 0, shift) << ((64 - shift)));
1497 wR [BITS (12, 15)] = wR [BITS (16, 19)];
1499 wC [wCon] |= WCON_MUP;
1504 WAND (ARMword instr)
1509 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1513 fprintf (stderr, "wand\n");
1516 result = wR [BITS (16, 19)] & wR [BITS (0, 3)];
1517 wR [BITS (12, 15)] = result;
1519 SIMD64_SET (psr, (result == 0), SIMD_ZBIT);
1520 SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT);
1523 wC [wCon] |= (WCON_CUP | WCON_MUP);
1529 WANDN (ARMword instr)
1534 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1538 fprintf (stderr, "wandn\n");
1541 result = wR [BITS (16, 19)] & ~ wR [BITS (0, 3)];
1542 wR [BITS (12, 15)] = result;
1544 SIMD64_SET (psr, (result == 0), SIMD_ZBIT);
1545 SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT);
1548 wC [wCon] |= (WCON_CUP | WCON_MUP);
1554 WAVG2 (ARMword instr)
1560 int round = BIT (20) ? 1 : 0;
1562 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1566 fprintf (stderr, "wavg2\n");
1569 #define AVG2x(x, y, m) (((wRBITS (BITS (16, 19), (x), (y)) & (m)) \
1570 + (wRBITS (BITS ( 0, 3), (x), (y)) & (m)) \
1575 for (i = 0; i < 4; i++)
1577 s = AVG2x ((i * 16), (i * 16) + 15, 0xffff) & 0xffff;
1578 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
1584 for (i = 0; i < 8; i++)
1586 s = AVG2x ((i * 8), (i * 8) + 7, 0xff) & 0xff;
1587 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
1592 wR [BITS (12, 15)] = r;
1594 wC [wCon] |= (WCON_CUP | WCON_MUP);
1600 WCMPEQ (ARMul_State * state, ARMword instr)
1607 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1611 fprintf (stderr, "wcmpeq\n");
1614 switch (BITS (22, 23))
1617 for (i = 0; i < 8; i++)
1619 s = wRBYTE (BITS (16, 19), i) == wRBYTE (BITS (0, 3), i) ? 0xff : 0;
1621 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
1622 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
1627 for (i = 0; i < 4; i++)
1629 s = wRHALF (BITS (16, 19), i) == wRHALF (BITS (0, 3), i) ? 0xffff : 0;
1631 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
1632 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
1637 for (i = 0; i < 2; i++)
1639 s = wRWORD (BITS (16, 19), i) == wRWORD (BITS (0, 3), i) ? 0xffffffff : 0;
1641 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
1642 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
1647 ARMul_UndefInstr (state, instr);
1652 wR [BITS (12, 15)] = r;
1653 wC [wCon] |= (WCON_CUP | WCON_MUP);
1659 WCMPGT (ARMul_State * state, ARMword instr)
1666 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1670 fprintf (stderr, "wcmpgt\n");
1673 switch (BITS (22, 23))
1678 /* Use a signed comparison. */
1679 for (i = 0; i < 8; i++)
1683 a = wRBYTE (BITS (16, 19), i);
1684 b = wRBYTE (BITS (0, 3), i);
1686 s = (a > b) ? 0xff : 0;
1688 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
1689 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
1694 for (i = 0; i < 8; i++)
1696 s = (wRBYTE (BITS (16, 19), i) > wRBYTE (BITS (0, 3), i))
1699 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
1700 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
1708 for (i = 0; i < 4; i++)
1712 a = wRHALF (BITS (16, 19), i);
1715 b = wRHALF (BITS (0, 3), i);
1718 s = (a > b) ? 0xffff : 0;
1720 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
1721 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
1726 for (i = 0; i < 4; i++)
1728 s = (wRHALF (BITS (16, 19), i) > wRHALF (BITS (0, 3), i))
1731 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
1732 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
1740 for (i = 0; i < 2; i++)
1744 a = wRWORD (BITS (16, 19), i);
1745 b = wRWORD (BITS (0, 3), i);
1747 s = (a > b) ? 0xffffffff : 0;
1749 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
1750 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
1755 for (i = 0; i < 2; i++)
1757 s = (wRWORD (BITS (16, 19), i) > wRWORD (BITS (0, 3), i))
1760 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
1761 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
1767 ARMul_UndefInstr (state, instr);
1772 wR [BITS (12, 15)] = r;
1773 wC [wCon] |= (WCON_CUP | WCON_MUP);
1779 Compute_Iwmmxt_Address (ARMul_State * state, ARMword instr, int * pFailed)
1788 addr = state->Reg [Rn];
1789 offset = BITS (0, 7);
1790 multiplier = BIT (8) ? 4 : 1;
1792 if (BIT (24)) /* P */
1794 /* Pre Indexed Addressing. */
1796 addr += offset * multiplier;
1798 addr -= offset * multiplier;
1800 /* Immediate Pre-Indexed. */
1801 if (BIT (21)) /* W */
1805 /* Writeback into R15 is UNPREDICTABLE. */
1807 fprintf (stderr, "iWMMXt: writeback into r15\n");
1812 state->Reg [Rn] = addr;
1817 /* Post Indexed Addressing. */
1818 if (BIT (21)) /* W */
1820 /* Handle the write back of the final address. */
1823 /* Writeback into R15 is UNPREDICTABLE. */
1825 fprintf (stderr, "iWMMXt: writeback into r15\n");
1834 increment = offset * multiplier;
1836 increment = - (offset * multiplier);
1838 state->Reg [Rn] = addr + increment;
1843 /* P == 0, W == 0, U == 0 is UNPREDICTABLE. */
1847 fprintf (stderr, "iWMMXt: undefined addressing mode\n");
1858 Iwmmxt_Load_Double_Word (ARMul_State * state, ARMword address)
1862 /* The address must be aligned on a 8 byte boundary. */
1865 fprintf (stderr, "iWMMXt: At addr 0x%x: Unaligned double word load from 0x%x\n",
1866 (state->Reg[15] - 8) & ~0x3, address);
1869 /* No need to check for alignment traps. An unaligned
1870 double word load with alignment trapping disabled is
1872 ARMul_Abort (state, ARMul_DataAbortV);
1875 /* Load the words. */
1876 if (! state->bigendSig)
1878 value = ARMul_LoadWordN (state, address + 4);
1880 value |= ARMul_LoadWordN (state, address);
1884 value = ARMul_LoadWordN (state, address);
1886 value |= ARMul_LoadWordN (state, address + 4);
1889 /* Check for data aborts. */
1891 ARMul_Abort (state, ARMul_DataAbortV);
1893 ARMul_Icycles (state, 2, 0L);
1899 Iwmmxt_Load_Word (ARMul_State * state, ARMword address)
1903 /* Check for a misaligned address. */
1906 if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN))
1907 ARMul_Abort (state, ARMul_DataAbortV);
1912 value = ARMul_LoadWordN (state, address);
1915 ARMul_Abort (state, ARMul_DataAbortV);
1917 ARMul_Icycles (state, 1, 0L);
1923 Iwmmxt_Load_Half_Word (ARMul_State * state, ARMword address)
1927 /* Check for a misaligned address. */
1930 if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN))
1931 ARMul_Abort (state, ARMul_DataAbortV);
1936 value = ARMul_LoadHalfWord (state, address);
1939 ARMul_Abort (state, ARMul_DataAbortV);
1941 ARMul_Icycles (state, 1, 0L);
1947 Iwmmxt_Load_Byte (ARMul_State * state, ARMword address)
1951 value = ARMul_LoadByte (state, address);
1954 ARMul_Abort (state, ARMul_DataAbortV);
1956 ARMul_Icycles (state, 1, 0L);
1962 Iwmmxt_Store_Double_Word (ARMul_State * state, ARMword address, ARMdword value)
1964 /* The address must be aligned on a 8 byte boundary. */
1967 fprintf (stderr, "iWMMXt: At addr 0x%x: Unaligned double word store to 0x%x\n",
1968 (state->Reg[15] - 8) & ~0x3, address);
1971 /* No need to check for alignment traps. An unaligned
1972 double word store with alignment trapping disabled is
1974 ARMul_Abort (state, ARMul_DataAbortV);
1977 /* Store the words. */
1978 if (! state->bigendSig)
1980 ARMul_StoreWordN (state, address, value);
1981 ARMul_StoreWordN (state, address + 4, value >> 32);
1985 ARMul_StoreWordN (state, address + 4, value);
1986 ARMul_StoreWordN (state, address, value >> 32);
1989 /* Check for data aborts. */
1991 ARMul_Abort (state, ARMul_DataAbortV);
1993 ARMul_Icycles (state, 2, 0L);
1997 Iwmmxt_Store_Word (ARMul_State * state, ARMword address, ARMword value)
1999 /* Check for a misaligned address. */
2002 if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN))
2003 ARMul_Abort (state, ARMul_DataAbortV);
2008 ARMul_StoreWordN (state, address, value);
2011 ARMul_Abort (state, ARMul_DataAbortV);
2015 Iwmmxt_Store_Half_Word (ARMul_State * state, ARMword address, ARMword value)
2017 /* Check for a misaligned address. */
2020 if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN))
2021 ARMul_Abort (state, ARMul_DataAbortV);
2026 ARMul_StoreHalfWord (state, address, value);
2029 ARMul_Abort (state, ARMul_DataAbortV);
2033 Iwmmxt_Store_Byte (ARMul_State * state, ARMword address, ARMword value)
2035 ARMul_StoreByte (state, address, value);
2038 ARMul_Abort (state, ARMul_DataAbortV);
2042 WLDR (ARMul_State * state, ARMword instr)
2047 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2051 fprintf (stderr, "wldr\n");
2054 address = Compute_Iwmmxt_Address (state, instr, & failed);
2058 if (BITS (28, 31) == 0xf)
2061 wC [BITS (12, 15)] = Iwmmxt_Load_Word (state, address);
2063 else if (BIT (8) == 0)
2067 wR [BITS (12, 15)] = Iwmmxt_Load_Byte (state, address);
2070 wR [BITS (12, 15)] = Iwmmxt_Load_Half_Word (state, address);
2076 wR [BITS (12, 15)] = Iwmmxt_Load_Word (state, address);
2079 wR [BITS (12, 15)] = Iwmmxt_Load_Double_Word (state, address);
2082 wC [wCon] |= WCON_MUP;
2088 WMAC (ARMword instr)
2094 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2098 fprintf (stderr, "wmac\n");
2101 for (i = 0; i < 4; i++)
2108 a = wRHALF (BITS (16, 19), i);
2111 b = wRHALF (BITS (0, 3), i);
2114 s = (signed long) a * (signed long) b;
2116 t = t + (ARMdword) s;
2121 a = wRHALF (BITS (16, 19), i);
2122 b = wRHALF (BITS ( 0, 3), i);
2129 wR [BITS (12, 15)] = 0;
2131 if (BIT (21)) /* Signed. */
2132 wR[BITS (12, 15)] += t;
2134 wR [BITS (12, 15)] += t;
2136 wC [wCon] |= WCON_MUP;
2142 WMADD (ARMword instr)
2147 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2151 fprintf (stderr, "wmadd\n");
2154 for (i = 0; i < 2; i++)
2158 if (BIT (21)) /* Signed. */
2162 a = wRHALF (BITS (16, 19), i * 2);
2165 b = wRHALF (BITS (0, 3), i * 2);
2168 s1 = (ARMdword) (a * b);
2170 a = wRHALF (BITS (16, 19), i * 2 + 1);
2173 b = wRHALF (BITS (0, 3), i * 2 + 1);
2176 s2 = (ARMdword) (a * b);
2178 else /* Unsigned. */
2182 a = wRHALF (BITS (16, 19), i * 2);
2183 b = wRHALF (BITS ( 0, 3), i * 2);
2185 s1 = (ARMdword) (a * b);
2187 a = wRHALF (BITS (16, 19), i * 2 + 1);
2188 b = wRHALF (BITS ( 0, 3), i * 2 + 1);
2190 s2 = (ARMdword) a * b;
2193 r |= (ARMdword) ((s1 + s2) & 0xffffffff) << (i ? 32 : 0);
2196 wR [BITS (12, 15)] = r;
2197 wC [wCon] |= WCON_MUP;
2203 WMAX (ARMul_State * state, ARMword instr)
2209 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2213 fprintf (stderr, "wmax\n");
2216 switch (BITS (22, 23))
2219 for (i = 0; i < 8; i++)
2220 if (BIT (21)) /* Signed. */
2224 a = wRBYTE (BITS (16, 19), i);
2227 b = wRBYTE (BITS (0, 3), i);
2235 r |= (s & 0xff) << (i * 8);
2237 else /* Unsigned. */
2241 a = wRBYTE (BITS (16, 19), i);
2242 b = wRBYTE (BITS (0, 3), i);
2249 r |= (s & 0xff) << (i * 8);
2254 for (i = 0; i < 4; i++)
2255 if (BIT (21)) /* Signed. */
2259 a = wRHALF (BITS (16, 19), i);
2262 b = wRHALF (BITS (0, 3), i);
2270 r |= (s & 0xffff) << (i * 16);
2272 else /* Unsigned. */
2276 a = wRHALF (BITS (16, 19), i);
2277 b = wRHALF (BITS (0, 3), i);
2284 r |= (s & 0xffff) << (i * 16);
2289 for (i = 0; i < 2; i++)
2290 if (BIT (21)) /* Signed. */
2294 a = wRWORD (BITS (16, 19), i);
2295 b = wRWORD (BITS (0, 3), i);
2302 r |= (s & 0xffffffff) << (i * 32);
2308 a = wRWORD (BITS (16, 19), i);
2309 b = wRWORD (BITS (0, 3), i);
2316 r |= (s & 0xffffffff) << (i * 32);
2321 ARMul_UndefInstr (state, instr);
2325 wR [BITS (12, 15)] = r;
2326 wC [wCon] |= WCON_MUP;
2332 WMIN (ARMul_State * state, ARMword instr)
2338 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2342 fprintf (stderr, "wmin\n");
2345 switch (BITS (22, 23))
2348 for (i = 0; i < 8; i++)
2349 if (BIT (21)) /* Signed. */
2353 a = wRBYTE (BITS (16, 19), i);
2356 b = wRBYTE (BITS (0, 3), i);
2364 r |= (s & 0xff) << (i * 8);
2366 else /* Unsigned. */
2370 a = wRBYTE (BITS (16, 19), i);
2371 b = wRBYTE (BITS (0, 3), i);
2378 r |= (s & 0xff) << (i * 8);
2383 for (i = 0; i < 4; i++)
2384 if (BIT (21)) /* Signed. */
2388 a = wRHALF (BITS (16, 19), i);
2391 b = wRHALF (BITS (0, 3), i);
2399 r |= (s & 0xffff) << (i * 16);
2406 a = wRHALF (BITS (16, 19), i);
2407 b = wRHALF (BITS ( 0, 3), i);
2414 r |= (s & 0xffff) << (i * 16);
2419 for (i = 0; i < 2; i++)
2420 if (BIT (21)) /* Signed. */
2424 a = wRWORD (BITS (16, 19), i);
2425 b = wRWORD (BITS ( 0, 3), i);
2432 r |= (s & 0xffffffff) << (i * 32);
2438 a = wRWORD (BITS (16, 19), i);
2439 b = wRWORD (BITS (0, 3), i);
2446 r |= (s & 0xffffffff) << (i * 32);
2451 ARMul_UndefInstr (state, instr);
2455 wR [BITS (12, 15)] = r;
2456 wC [wCon] |= WCON_MUP;
2462 WMUL (ARMword instr)
2468 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2472 fprintf (stderr, "wmul\n");
2475 for (i = 0; i < 4; i++)
2476 if (BIT (21)) /* Signed. */
2480 a = wRHALF (BITS (16, 19), i);
2483 b = wRHALF (BITS (0, 3), i);
2489 r |= ((s >> 16) & 0xffff) << (i * 16);
2491 r |= (s & 0xffff) << (i * 16);
2493 else /* Unsigned. */
2497 a = wRHALF (BITS (16, 19), i);
2498 b = wRHALF (BITS (0, 3), i);
2503 r |= ((s >> 16) & 0xffff) << (i * 16);
2505 r |= (s & 0xffff) << (i * 16);
2508 wR [BITS (12, 15)] = r;
2509 wC [wCon] |= WCON_MUP;
2520 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2524 fprintf (stderr, "wor\n");
2527 result = wR [BITS (16, 19)] | wR [BITS (0, 3)];
2528 wR [BITS (12, 15)] = result;
2530 SIMD64_SET (psr, (result == 0), SIMD_ZBIT);
2531 SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT);
2534 wC [wCon] |= (WCON_CUP | WCON_MUP);
2540 WPACK (ARMul_State * state, ARMword instr)
2549 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2553 fprintf (stderr, "wpack\n");
2556 switch (BITS (22, 23))
2559 for (i = 0; i < 8; i++)
2561 x = wRHALF (i < 4 ? BITS (16, 19) : BITS (0, 3), i & 3);
2563 switch (BITS (20, 21))
2565 case UnsignedSaturation:
2566 s = IwmmxtSaturateU8 (x, satrv + BITIDX8 (i));
2569 case SignedSaturation:
2570 s = IwmmxtSaturateS8 (x, satrv + BITIDX8 (i));
2574 ARMul_UndefInstr (state, instr);
2578 r |= (s & 0xff) << (i * 8);
2579 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
2580 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
2585 satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0;
2587 for (i = 0; i < 4; i++)
2589 x = wRWORD (i < 2 ? BITS (16, 19) : BITS (0, 3), i & 1);
2591 switch (BITS (20, 21))
2593 case UnsignedSaturation:
2594 s = IwmmxtSaturateU16 (x, satrv + BITIDX16 (i));
2597 case SignedSaturation:
2598 s = IwmmxtSaturateS16 (x, satrv + BITIDX16 (i));
2602 ARMul_UndefInstr (state, instr);
2606 r |= (s & 0xffff) << (i * 16);
2607 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
2608 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
2613 satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0;
2615 for (i = 0; i < 2; i++)
2617 x = wR [i ? BITS (0, 3) : BITS (16, 19)];
2619 switch (BITS (20, 21))
2621 case UnsignedSaturation:
2622 s = IwmmxtSaturateU32 (x, satrv + BITIDX32 (i));
2625 case SignedSaturation:
2626 s = IwmmxtSaturateS32 (x, satrv + BITIDX32 (i));
2630 ARMul_UndefInstr (state, instr);
2634 r |= (s & 0xffffffff) << (i * 32);
2635 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
2636 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
2641 ARMul_UndefInstr (state, instr);
2646 wR [BITS (12, 15)] = r;
2647 SET_wCSSFvec (satrv);
2648 wC [wCon] |= (WCON_CUP | WCON_MUP);
2654 WROR (ARMul_State * state, ARMword instr)
2662 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2666 fprintf (stderr, "wror\n");
2669 DECODE_G_BIT (state, instr, shift);
2671 switch (BITS (22, 23))
2675 for (i = 0; i < 4; i++)
2677 s = ((wRHALF (BITS (16, 19), i) & 0xffff) << (16 - shift))
2678 | ((wRHALF (BITS (16, 19), i) & 0xffff) >> shift);
2679 r |= (s & 0xffff) << (i * 16);
2680 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
2681 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
2687 for (i = 0; i < 2; i++)
2689 s = ((wRWORD (BITS (16, 19), i) & 0xffffffff) << (32 - shift))
2690 | ((wRWORD (BITS (16, 19), i) & 0xffffffff) >> shift);
2691 r |= (s & 0xffffffff) << (i * 32);
2692 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
2693 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
2699 r = (wR [BITS (16, 19)] >> shift)
2700 | (wR [BITS (16, 19)] << (64 - shift));
2702 SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
2703 SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
2707 ARMul_UndefInstr (state, instr);
2712 wR [BITS (12, 15)] = r;
2713 wC [wCon] |= (WCON_CUP | WCON_MUP);
2719 WSAD (ARMword instr)
2725 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2729 fprintf (stderr, "wsad\n");
2733 r = BIT (20) ? 0 : (wR [BITS (12, 15)] & 0xffffffff);
2737 for (i = 0; i < 4; i++)
2739 s = (wRHALF (BITS (16, 19), i) - wRHALF (BITS (0, 3), i));
2744 for (i = 0; i < 8; i++)
2746 s = (wRBYTE (BITS (16, 19), i) - wRBYTE (BITS (0, 3), i));
2750 wR [BITS (12, 15)] = r;
2751 wC [wCon] |= WCON_MUP;
2757 WSHUFH (ARMword instr)
2765 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2769 fprintf (stderr, "wshufh\n");
2772 imm8 = (BITS (20, 23) << 4) | BITS (0, 3);
2774 for (i = 0; i < 4; i++)
2776 s = wRHALF (BITS (16, 19), ((imm8 >> (i * 2) & 3)) & 0xff);
2777 r |= (s & 0xffff) << (i * 16);
2778 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
2779 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
2783 wR [BITS (12, 15)] = r;
2784 wC [wCon] |= (WCON_CUP | WCON_MUP);
2790 WSLL (ARMul_State * state, ARMword instr)
2798 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2802 fprintf (stderr, "wsll\n");
2805 DECODE_G_BIT (state, instr, shift);
2807 switch (BITS (22, 23))
2810 for (i = 0; i < 4; i++)
2815 s = ((wRHALF (BITS (16, 19), i) & 0xffff) << shift);
2816 r |= (s & 0xffff) << (i * 16);
2817 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
2818 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
2823 for (i = 0; i < 2; i++)
2828 s = ((wRWORD (BITS (16, 19), i) & 0xffffffff) << shift);
2829 r |= (s & 0xffffffff) << (i * 32);
2830 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
2831 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
2839 r = ((wR[BITS (16, 19)] & 0xffffffffffffffffULL) << shift);
2841 SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
2842 SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
2846 ARMul_UndefInstr (state, instr);
2851 wR [BITS (12, 15)] = r;
2852 wC [wCon] |= (WCON_CUP | WCON_MUP);
2858 WSRA (ARMul_State * state, ARMword instr)
2867 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2871 fprintf (stderr, "wsra\n");
2874 DECODE_G_BIT (state, instr, shift);
2876 switch (BITS (22, 23))
2879 for (i = 0; i < 4; i++)
2882 t = (wRHALF (BITS (16, 19), i) & 0x8000) ? 0xffff : 0;
2885 t = wRHALF (BITS (16, 19), i);
2891 r |= (s & 0xffff) << (i * 16);
2892 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
2893 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
2898 for (i = 0; i < 2; i++)
2901 t = (wRWORD (BITS (16, 19), i) & 0x80000000) ? 0xffffffff : 0;
2904 t = wRWORD (BITS (16, 19), i);
2908 r |= (s & 0xffffffff) << (i * 32);
2909 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
2910 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
2916 r = (wR [BITS (16, 19)] & 0x8000000000000000ULL) ? 0xffffffffffffffffULL : 0;
2918 r = ((signed long long) (wR[BITS (16, 19)] & 0xffffffffffffffffULL) >> shift);
2919 SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
2920 SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
2924 ARMul_UndefInstr (state, instr);
2929 wR [BITS (12, 15)] = r;
2930 wC [wCon] |= (WCON_CUP | WCON_MUP);
2936 WSRL (ARMul_State * state, ARMword instr)
2944 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2948 fprintf (stderr, "wsrl\n");
2951 DECODE_G_BIT (state, instr, shift);
2953 switch (BITS (22, 23))
2956 for (i = 0; i < 4; i++)
2961 s = ((unsigned) (wRHALF (BITS (16, 19), i) & 0xffff) >> shift);
2963 r |= (s & 0xffff) << (i * 16);
2964 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
2965 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
2970 for (i = 0; i < 2; i++)
2975 s = ((unsigned long) (wRWORD (BITS (16, 19), i) & 0xffffffff) >> shift);
2977 r |= (s & 0xffffffff) << (i * 32);
2978 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
2979 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
2987 r = (wR [BITS (16, 19)] & 0xffffffffffffffffULL) >> shift;
2989 SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
2990 SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
2994 ARMul_UndefInstr (state, instr);
2999 wR [BITS (12, 15)] = r;
3000 wC [wCon] |= (WCON_CUP | WCON_MUP);
3006 WSTR (ARMul_State * state, ARMword instr)
3012 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3016 fprintf (stderr, "wstr\n");
3019 address = Compute_Iwmmxt_Address (state, instr, & failed);
3023 if (BITS (28, 31) == 0xf)
3026 Iwmmxt_Store_Word (state, address, wC [BITS (12, 15)]);
3028 else if (BIT (8) == 0)
3032 Iwmmxt_Store_Byte (state, address, wR [BITS (12, 15)]);
3035 Iwmmxt_Store_Half_Word (state, address, wR [BITS (12, 15)]);
3041 Iwmmxt_Store_Word (state, address, wR [BITS (12, 15)]);
3044 Iwmmxt_Store_Double_Word (state, address, wR [BITS (12, 15)]);
3051 WSUB (ARMul_State * state, ARMword instr)
3062 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3066 fprintf (stderr, "wsub\n");
3069 /* Subtract two numbers using the specified function,
3070 leaving setting the carry bit as required. */
3071 #define SUBx(x, y, m, f) \
3072 (*f) (wRBITS (BITS (16, 19), (x), (y)) & (m), \
3073 wRBITS (BITS ( 0, 3), (x), (y)) & (m), & carry, & overflow)
3075 switch (BITS (22, 23))
3078 for (i = 0; i < 8; i++)
3080 switch (BITS (20, 21))
3083 s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubS8);
3084 satrv [BITIDX8 (i)] = 0;
3085 r |= (s & 0xff) << (i * 8);
3086 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
3087 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
3088 SIMD8_SET (psr, carry, SIMD_CBIT, i);
3089 SIMD8_SET (psr, overflow, SIMD_VBIT, i);
3092 case UnsignedSaturation:
3093 s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubU8);
3094 x = IwmmxtSaturateU8 (s, satrv + BITIDX8 (i));
3095 r |= (x & 0xff) << (i * 8);
3096 SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i);
3097 SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i);
3098 if (! satrv [BITIDX8 (i)])
3100 SIMD8_SET (psr, carry, SIMD_CBIT, i);
3101 SIMD8_SET (psr, overflow, SIMD_VBIT, i);
3105 case SignedSaturation:
3106 s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubS8);
3107 x = IwmmxtSaturateS8 (s, satrv + BITIDX8 (i));
3108 r |= (x & 0xff) << (i * 8);
3109 SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i);
3110 SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i);
3111 if (! satrv [BITIDX8 (i)])
3113 SIMD8_SET (psr, carry, SIMD_CBIT, i);
3114 SIMD8_SET (psr, overflow, SIMD_VBIT, i);
3119 ARMul_UndefInstr (state, instr);
3126 satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0;
3128 for (i = 0; i < 4; i++)
3130 switch (BITS (20, 21))
3133 s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubU16);
3134 satrv [BITIDX16 (i)] = 0;
3135 r |= (s & 0xffff) << (i * 16);
3136 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
3137 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
3138 SIMD16_SET (psr, carry, SIMD_CBIT, i);
3139 SIMD16_SET (psr, overflow, SIMD_VBIT, i);
3142 case UnsignedSaturation:
3143 s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubU16);
3144 x = IwmmxtSaturateU16 (s, satrv + BITIDX16 (i));
3145 r |= (x & 0xffff) << (i * 16);
3146 SIMD16_SET (psr, NBIT16 (x & 0xffff), SIMD_NBIT, i);
3147 SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i);
3148 if (! satrv [BITIDX16 (i)])
3150 SIMD16_SET (psr, carry, SIMD_CBIT, i);
3151 SIMD16_SET (psr, overflow, SIMD_VBIT, i);
3155 case SignedSaturation:
3156 s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubS16);
3157 x = IwmmxtSaturateS16 (s, satrv + BITIDX16 (i));
3158 r |= (x & 0xffff) << (i * 16);
3159 SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i);
3160 SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i);
3161 if (! satrv [BITIDX16 (i)])
3163 SIMD16_SET (psr, carry, SIMD_CBIT, i);
3164 SIMD16_SET (psr, overflow, SIMD_VBIT, i);
3169 ARMul_UndefInstr (state, instr);
3176 satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0;
3178 for (i = 0; i < 2; i++)
3180 switch (BITS (20, 21))
3183 s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubU32);
3184 satrv[BITIDX32 (i)] = 0;
3185 r |= (s & 0xffffffff) << (i * 32);
3186 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
3187 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
3188 SIMD32_SET (psr, carry, SIMD_CBIT, i);
3189 SIMD32_SET (psr, overflow, SIMD_VBIT, i);
3192 case UnsignedSaturation:
3193 s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubU32);
3194 x = IwmmxtSaturateU32 (s, satrv + BITIDX32 (i));
3195 r |= (x & 0xffffffff) << (i * 32);
3196 SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i);
3197 SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i);
3198 if (! satrv [BITIDX32 (i)])
3200 SIMD32_SET (psr, carry, SIMD_CBIT, i);
3201 SIMD32_SET (psr, overflow, SIMD_VBIT, i);
3205 case SignedSaturation:
3206 s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubS32);
3207 x = IwmmxtSaturateS32 (s, satrv + BITIDX32 (i));
3208 r |= (x & 0xffffffff) << (i * 32);
3209 SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i);
3210 SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i);
3211 if (! satrv [BITIDX32 (i)])
3213 SIMD32_SET (psr, carry, SIMD_CBIT, i);
3214 SIMD32_SET (psr, overflow, SIMD_VBIT, i);
3219 ARMul_UndefInstr (state, instr);
3226 ARMul_UndefInstr (state, instr);
3230 wR [BITS (12, 15)] = r;
3232 SET_wCSSFvec (satrv);
3233 wC [wCon] |= (WCON_CUP | WCON_MUP);
3241 WUNPCKEH (ARMul_State * state, ARMword instr)
3248 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3252 fprintf (stderr, "wunpckeh\n");
3255 switch (BITS (22, 23))
3258 for (i = 0; i < 4; i++)
3260 s = wRBYTE (BITS (16, 19), i + 4);
3262 if (BIT (21) && NBIT8 (s))
3265 r |= (s & 0xffff) << (i * 16);
3266 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
3267 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
3272 for (i = 0; i < 2; i++)
3274 s = wRHALF (BITS (16, 19), i + 2);
3276 if (BIT (21) && NBIT16 (s))
3279 r |= (s & 0xffffffff) << (i * 32);
3280 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
3281 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
3286 r = wRWORD (BITS (16, 19), 1);
3288 if (BIT (21) && NBIT32 (r))
3289 r |= 0xffffffff00000000ULL;
3291 SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
3292 SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
3296 ARMul_UndefInstr (state, instr);
3301 wR [BITS (12, 15)] = r;
3302 wC [wCon] |= (WCON_CUP | WCON_MUP);
3308 WUNPCKEL (ARMul_State * state, ARMword instr)
3315 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3319 fprintf (stderr, "wunpckel\n");
3322 switch (BITS (22, 23))
3325 for (i = 0; i < 4; i++)
3327 s = wRBYTE (BITS (16, 19), i);
3329 if (BIT (21) && NBIT8 (s))
3332 r |= (s & 0xffff) << (i * 16);
3333 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
3334 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
3339 for (i = 0; i < 2; i++)
3341 s = wRHALF (BITS (16, 19), i);
3343 if (BIT (21) && NBIT16 (s))
3346 r |= (s & 0xffffffff) << (i * 32);
3347 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
3348 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
3353 r = wRWORD (BITS (16, 19), 0);
3355 if (BIT (21) && NBIT32 (r))
3356 r |= 0xffffffff00000000ULL;
3358 SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
3359 SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
3363 ARMul_UndefInstr (state, instr);
3368 wR [BITS (12, 15)] = r;
3369 wC [wCon] |= (WCON_CUP | WCON_MUP);
3375 WUNPCKIH (ARMul_State * state, ARMword instr)
3383 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3387 fprintf (stderr, "wunpckih\n");
3390 switch (BITS (22, 23))
3393 for (i = 0; i < 4; i++)
3395 a = wRBYTE (BITS (16, 19), i + 4);
3396 b = wRBYTE (BITS ( 0, 3), i + 4);
3398 r |= (s & 0xffff) << (i * 16);
3399 SIMD8_SET (psr, NBIT8 (a), SIMD_NBIT, i * 2);
3400 SIMD8_SET (psr, ZBIT8 (a), SIMD_ZBIT, i * 2);
3401 SIMD8_SET (psr, NBIT8 (b), SIMD_NBIT, (i * 2) + 1);
3402 SIMD8_SET (psr, ZBIT8 (b), SIMD_ZBIT, (i * 2) + 1);
3407 for (i = 0; i < 2; i++)
3409 a = wRHALF (BITS (16, 19), i + 2);
3410 b = wRHALF (BITS ( 0, 3), i + 2);
3412 r |= (s & 0xffffffff) << (i * 32);
3413 SIMD16_SET (psr, NBIT16 (a), SIMD_NBIT, (i * 2));
3414 SIMD16_SET (psr, ZBIT16 (a), SIMD_ZBIT, (i * 2));
3415 SIMD16_SET (psr, NBIT16 (b), SIMD_NBIT, (i * 2) + 1);
3416 SIMD16_SET (psr, ZBIT16 (b), SIMD_ZBIT, (i * 2) + 1);
3421 a = wRWORD (BITS (16, 19), 1);
3422 s = wRWORD (BITS ( 0, 3), 1);
3425 SIMD32_SET (psr, NBIT32 (a), SIMD_NBIT, 0);
3426 SIMD32_SET (psr, ZBIT32 (a), SIMD_ZBIT, 0);
3427 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, 1);
3428 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, 1);
3432 ARMul_UndefInstr (state, instr);
3437 wR [BITS (12, 15)] = r;
3438 wC [wCon] |= (WCON_CUP | WCON_MUP);
3444 WUNPCKIL (ARMul_State * state, ARMword instr)
3452 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3456 fprintf (stderr, "wunpckil\n");
3459 switch (BITS (22, 23))
3462 for (i = 0; i < 4; i++)
3464 a = wRBYTE (BITS (16, 19), i);
3465 b = wRBYTE (BITS ( 0, 3), i);
3467 r |= (s & 0xffff) << (i * 16);
3468 SIMD8_SET (psr, NBIT8 (a), SIMD_NBIT, i * 2);
3469 SIMD8_SET (psr, ZBIT8 (a), SIMD_ZBIT, i * 2);
3470 SIMD8_SET (psr, NBIT8 (b), SIMD_NBIT, (i * 2) + 1);
3471 SIMD8_SET (psr, ZBIT8 (b), SIMD_ZBIT, (i * 2) + 1);
3476 for (i = 0; i < 2; i++)
3478 a = wRHALF (BITS (16, 19), i);
3479 b = wRHALF (BITS ( 0, 3), i);
3481 r |= (s & 0xffffffff) << (i * 32);
3482 SIMD16_SET (psr, NBIT16 (a), SIMD_NBIT, (i * 2));
3483 SIMD16_SET (psr, ZBIT16 (a), SIMD_ZBIT, (i * 2));
3484 SIMD16_SET (psr, NBIT16 (b), SIMD_NBIT, (i * 2) + 1);
3485 SIMD16_SET (psr, ZBIT16 (b), SIMD_ZBIT, (i * 2) + 1);
3490 a = wRWORD (BITS (16, 19), 0);
3491 s = wRWORD (BITS ( 0, 3), 0);
3494 SIMD32_SET (psr, NBIT32 (a), SIMD_NBIT, 0);
3495 SIMD32_SET (psr, ZBIT32 (a), SIMD_ZBIT, 0);
3496 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, 1);
3497 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, 1);
3501 ARMul_UndefInstr (state, instr);
3506 wR [BITS (12, 15)] = r;
3507 wC [wCon] |= (WCON_CUP | WCON_MUP);
3513 WXOR (ARMword instr)
3518 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3522 fprintf (stderr, "wxor\n");
3525 result = wR [BITS (16, 19)] ^ wR [BITS (0, 3)];
3526 wR [BITS (12, 15)] = result;
3528 SIMD64_SET (psr, (result == 0), SIMD_ZBIT);
3529 SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT);
3532 wC [wCon] |= (WCON_CUP | WCON_MUP);
3537 /* This switch table is moved to a seperate function in order
3538 to work around a compiler bug in the host compiler... */
3541 Process_Instruction (ARMul_State * state, ARMword instr)
3543 int status = ARMul_BUSY;
3545 switch ((BITS (20, 23) << 8) | BITS (4, 11))
3547 case 0x000: status = WOR (instr); break;
3548 case 0x011: status = TMCR (state, instr); break;
3549 case 0x100: status = WXOR (instr); break;
3550 case 0x111: status = TMRC (state, instr); break;
3551 case 0x300: status = WANDN (instr); break;
3552 case 0x200: status = WAND (instr); break;
3554 case 0x810: case 0xa10:
3555 status = WMADD (instr); break;
3557 case 0x10e: case 0x50e: case 0x90e: case 0xd0e:
3558 status = WUNPCKIL (state, instr); break;
3559 case 0x10c: case 0x50c: case 0x90c: case 0xd0c:
3560 status = WUNPCKIH (state, instr); break;
3561 case 0x012: case 0x112: case 0x412: case 0x512:
3562 status = WSAD (instr); break;
3563 case 0x010: case 0x110: case 0x210: case 0x310:
3564 status = WMUL (instr); break;
3565 case 0x410: case 0x510: case 0x610: case 0x710:
3566 status = WMAC (instr); break;
3567 case 0x006: case 0x406: case 0x806: case 0xc06:
3568 status = WCMPEQ (state, instr); break;
3569 case 0x800: case 0x900: case 0xc00: case 0xd00:
3570 status = WAVG2 (instr); break;
3571 case 0x802: case 0x902: case 0xa02: case 0xb02:
3572 status = WALIGNR (state, instr); break;
3573 case 0x601: case 0x605: case 0x609: case 0x60d:
3574 status = TINSR (state, instr); break;
3575 case 0x107: case 0x507: case 0x907: case 0xd07:
3576 status = TEXTRM (state, instr); break;
3577 case 0x117: case 0x517: case 0x917: case 0xd17:
3578 status = TEXTRC (state, instr); break;
3579 case 0x401: case 0x405: case 0x409: case 0x40d:
3580 status = TBCST (state, instr); break;
3581 case 0x113: case 0x513: case 0x913: case 0xd13:
3582 status = TANDC (state, instr); break;
3583 case 0x01c: case 0x41c: case 0x81c: case 0xc1c:
3584 status = WACC (state, instr); break;
3585 case 0x115: case 0x515: case 0x915: case 0xd15:
3586 status = TORC (state, instr); break;
3587 case 0x103: case 0x503: case 0x903: case 0xd03:
3588 status = TMOVMSK (state, instr); break;
3589 case 0x106: case 0x306: case 0x506: case 0x706:
3590 case 0x906: case 0xb06: case 0xd06: case 0xf06:
3591 status = WCMPGT (state, instr); break;
3592 case 0x00e: case 0x20e: case 0x40e: case 0x60e:
3593 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
3594 status = WUNPCKEL (state, instr); break;
3595 case 0x00c: case 0x20c: case 0x40c: case 0x60c:
3596 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
3597 status = WUNPCKEH (state, instr); break;
3598 case 0x204: case 0x604: case 0xa04: case 0xe04:
3599 case 0x214: case 0x614: case 0xa14: case 0xe14:
3600 status = WSRL (state, instr); break;
3601 case 0x004: case 0x404: case 0x804: case 0xc04:
3602 case 0x014: case 0x414: case 0x814: case 0xc14:
3603 status = WSRA (state, instr); break;
3604 case 0x104: case 0x504: case 0x904: case 0xd04:
3605 case 0x114: case 0x514: case 0x914: case 0xd14:
3606 status = WSLL (state, instr); break;
3607 case 0x304: case 0x704: case 0xb04: case 0xf04:
3608 case 0x314: case 0x714: case 0xb14: case 0xf14:
3609 status = WROR (state, instr); break;
3610 case 0x116: case 0x316: case 0x516: case 0x716:
3611 case 0x916: case 0xb16: case 0xd16: case 0xf16:
3612 status = WMIN (state, instr); break;
3613 case 0x016: case 0x216: case 0x416: case 0x616:
3614 case 0x816: case 0xa16: case 0xc16: case 0xe16:
3615 status = WMAX (state, instr); break;
3616 case 0x002: case 0x102: case 0x202: case 0x302:
3617 case 0x402: case 0x502: case 0x602: case 0x702:
3618 status = WALIGNI (instr); break;
3619 case 0x01a: case 0x11a: case 0x21a: case 0x31a:
3620 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
3621 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
3622 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
3623 status = WSUB (state, instr); break;
3624 case 0x01e: case 0x11e: case 0x21e: case 0x31e:
3625 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
3626 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
3627 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
3628 status = WSHUFH (instr); break;
3629 case 0x018: case 0x118: case 0x218: case 0x318:
3630 case 0x418: case 0x518: case 0x618: case 0x718:
3631 case 0x818: case 0x918: case 0xa18: case 0xb18:
3632 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
3633 status = WADD (state, instr); break;
3634 case 0x008: case 0x108: case 0x208: case 0x308:
3635 case 0x408: case 0x508: case 0x608: case 0x708:
3636 case 0x808: case 0x908: case 0xa08: case 0xb08:
3637 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
3638 status = WPACK (state, instr); break;
3639 case 0x201: case 0x203: case 0x205: case 0x207:
3640 case 0x209: case 0x20b: case 0x20d: case 0x20f:
3641 case 0x211: case 0x213: case 0x215: case 0x217:
3642 case 0x219: case 0x21b: case 0x21d: case 0x21f:
3643 switch (BITS (16, 19))
3645 case 0x0: status = TMIA (state, instr); break;
3646 case 0x8: status = TMIAPH (state, instr); break;
3650 case 0xf: status = TMIAxy (state, instr); break;
3660 /* Process a possibly Intel(r) Wireless MMX(tm) technology instruction.
3661 Return true if the instruction was handled. */
3664 ARMul_HandleIwmmxt (ARMul_State * state, ARMword instr)
3666 int status = ARMul_BUSY;
3668 if (BITS (24, 27) == 0xe)
3670 status = Process_Instruction (state, instr);
3672 else if (BITS (25, 27) == 0x6)
3674 if (BITS (4, 11) == 0x0 && BITS (20, 24) == 0x4)
3675 status = TMCRR (state, instr);
3676 else if (BITS (9, 11) == 0x0)
3678 if (BIT (20) == 0x0)
3679 status = WSTR (state, instr);
3680 else if (BITS (20, 24) == 0x5)
3681 status = TMRRC (state, instr);
3683 status = WLDR (state, instr);
3687 if (status == ARMul_CANT)
3689 /* If the instruction was a recognised but illegal,
3690 perform the abort here rather than returning false.
3691 If we return false then ARMul_MRC may be called which
3692 will still abort, but which also perform the register
3694 ARMul_Abort (state, ARMul_UndefinedInstrV);
3695 status = ARMul_DONE;
3698 return status == ARMul_DONE;
3702 Fetch_Iwmmxt_Register (unsigned int regnum, unsigned char * memory)
3706 memcpy (memory, wC + (regnum - 16), sizeof wC [0]);
3707 return sizeof wC [0];
3711 memcpy (memory, wR + regnum, sizeof wR [0]);
3712 return sizeof wR [0];
3717 Store_Iwmmxt_Register (unsigned int regnum, unsigned char * memory)
3721 memcpy (wC + (regnum - 16), memory, sizeof wC [0]);
3722 return sizeof wC [0];
3726 memcpy (wR + regnum, memory, sizeof wR [0]);
3727 return sizeof wR [0];