1 /* iwmmxt.c -- Intel(r) Wireless MMX(tm) technology co-processor interface.
2 Copyright (C) 2002-2015 Free Software Foundation, Inc.
3 Contributed by matthew green (mrg@redhat.com).
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program. If not, see <http://www.gnu.org/licenses/>. */
28 /* Intel(r) Wireless MMX(tm) technology co-processor.
29 It uses co-processor numbers (0 and 1). There are 16 vector registers wRx
30 and 16 control registers wCx. Co-processors 0 and 1 are used in MCR/MRC
31 to access wRx and wCx respectively. */
33 static ARMdword wR[16];
34 static ARMword wC[16] = { 0x69051010 };
36 #define SUBSTR(w,t,m,n) ((t)(w << ((sizeof (t) * 8 - 1) - (n))) \
37 >> (((sizeof (t) * 8 - 1) - (n)) + (m)))
38 #define wCBITS(w,x,y) SUBSTR (wC[w], ARMword, x, y)
39 #define wRBITS(w,x,y) SUBSTR (wR[w], ARMdword, x, y)
49 /* Bits in the wCon register. */
50 #define WCON_CUP (1 << 0)
51 #define WCON_MUP (1 << 1)
53 /* Set the SIMD wCASF flags for 8, 16, 32 or 64-bit operations. */
54 #define SIMD8_SET(x, v, n, b) (x) |= ((v != 0) << ((((b) + 1) * 4) + (n)))
55 #define SIMD16_SET(x, v, n, h) (x) |= ((v != 0) << ((((h) + 1) * 8) + (n)))
56 #define SIMD32_SET(x, v, n, w) (x) |= ((v != 0) << ((((w) + 1) * 16) + (n)))
57 #define SIMD64_SET(x, v, n) (x) |= ((v != 0) << (32 + (n)))
59 /* Flags to pass as "n" above. */
65 /* Various status bit macros. */
66 #define NBIT8(x) ((x) & 0x80)
67 #define NBIT16(x) ((x) & 0x8000)
68 #define NBIT32(x) ((x) & 0x80000000)
69 #define NBIT64(x) ((x) & 0x8000000000000000ULL)
70 #define ZBIT8(x) (((x) & 0xff) == 0)
71 #define ZBIT16(x) (((x) & 0xffff) == 0)
72 #define ZBIT32(x) (((x) & 0xffffffff) == 0)
73 #define ZBIT64(x) (x == 0)
75 /* Access byte/half/word "n" of register "x". */
76 #define wRBYTE(x,n) wRBITS ((x), (n) * 8, (n) * 8 + 7)
77 #define wRHALF(x,n) wRBITS ((x), (n) * 16, (n) * 16 + 15)
78 #define wRWORD(x,n) wRBITS ((x), (n) * 32, (n) * 32 + 31)
80 /* Macro to handle how the G bit selects wCGR registers. */
81 #define DECODE_G_BIT(state, instr, shift) \
87 if (BIT (8)) /* G */ \
89 if (reg < wCGR0 || reg > wCGR3) \
91 ARMul_UndefInstr (state, instr); \
102 /* Index calculations for the satrv[] array. */
103 #define BITIDX8(x) (x)
104 #define BITIDX16(x) (((x) + 1) * 2 - 1)
105 #define BITIDX32(x) (((x) + 1) * 4 - 1)
107 /* Sign extension macros. */
108 #define EXTEND8(a) ((a) & 0x80 ? ((a) | 0xffffff00) : (a))
109 #define EXTEND16(a) ((a) & 0x8000 ? ((a) | 0xffff0000) : (a))
110 #define EXTEND32(a) ((a) & 0x80000000ULL ? ((a) | 0xffffffff00000000ULL) : (a))
112 /* Set the wCSSF from 8 values. */
113 #define SET_wCSSF(a,b,c,d,e,f,g,h) \
114 wC[wCSSF] = (((h) != 0) << 7) | (((g) != 0) << 6) \
115 | (((f) != 0) << 5) | (((e) != 0) << 4) \
116 | (((d) != 0) << 3) | (((c) != 0) << 2) \
117 | (((b) != 0) << 1) | (((a) != 0) << 0);
119 /* Set the wCSSR from an array with 8 values. */
120 #define SET_wCSSFvec(v) \
121 SET_wCSSF((v)[0],(v)[1],(v)[2],(v)[3],(v)[4],(v)[5],(v)[6],(v)[7])
123 /* Size qualifiers for vector operations. */
129 /* Saturation qualifiers for vector operations. */
130 #define NoSaturation 0
131 #define UnsignedSaturation 1
132 #define SignedSaturation 3
136 static ARMword Add32 (ARMword, ARMword, int *, int *, ARMword);
137 static ARMdword AddS32 (ARMdword, ARMdword, int *, int *);
138 static ARMdword AddU32 (ARMdword, ARMdword, int *, int *);
139 static ARMword AddS16 (ARMword, ARMword, int *, int *);
140 static ARMword AddU16 (ARMword, ARMword, int *, int *);
141 static ARMword AddS8 (ARMword, ARMword, int *, int *);
142 static ARMword AddU8 (ARMword, ARMword, int *, int *);
143 static ARMword Sub32 (ARMword, ARMword, int *, int *, ARMword);
144 static ARMdword SubS32 (ARMdword, ARMdword, int *, int *);
145 static ARMdword SubU32 (ARMdword, ARMdword, int *, int *);
146 static ARMword SubS16 (ARMword, ARMword, int *, int *);
147 static ARMword SubS8 (ARMword, ARMword, int *, int *);
148 static ARMword SubU16 (ARMword, ARMword, int *, int *);
149 static ARMword SubU8 (ARMword, ARMword, int *, int *);
150 static unsigned char IwmmxtSaturateU8 (signed short, int *);
151 static signed char IwmmxtSaturateS8 (signed short, int *);
152 static unsigned short IwmmxtSaturateU16 (signed int, int *);
153 static signed short IwmmxtSaturateS16 (signed int, int *);
154 static unsigned long IwmmxtSaturateU32 (signed long long, int *);
155 static signed long IwmmxtSaturateS32 (signed long long, int *);
156 static ARMword Compute_Iwmmxt_Address (ARMul_State *, ARMword, int *);
157 static ARMdword Iwmmxt_Load_Double_Word (ARMul_State *, ARMword);
158 static ARMword Iwmmxt_Load_Word (ARMul_State *, ARMword);
159 static ARMword Iwmmxt_Load_Half_Word (ARMul_State *, ARMword);
160 static ARMword Iwmmxt_Load_Byte (ARMul_State *, ARMword);
161 static void Iwmmxt_Store_Double_Word (ARMul_State *, ARMword, ARMdword);
162 static void Iwmmxt_Store_Word (ARMul_State *, ARMword, ARMword);
163 static void Iwmmxt_Store_Half_Word (ARMul_State *, ARMword, ARMword);
164 static void Iwmmxt_Store_Byte (ARMul_State *, ARMword, ARMword);
165 static int Process_Instruction (ARMul_State *, ARMword);
167 static int TANDC (ARMul_State *, ARMword);
168 static int TBCST (ARMul_State *, ARMword);
169 static int TEXTRC (ARMul_State *, ARMword);
170 static int TEXTRM (ARMul_State *, ARMword);
171 static int TINSR (ARMul_State *, ARMword);
172 static int TMCR (ARMul_State *, ARMword);
173 static int TMCRR (ARMul_State *, ARMword);
174 static int TMIA (ARMul_State *, ARMword);
175 static int TMIAPH (ARMul_State *, ARMword);
176 static int TMIAxy (ARMul_State *, ARMword);
177 static int TMOVMSK (ARMul_State *, ARMword);
178 static int TMRC (ARMul_State *, ARMword);
179 static int TMRRC (ARMul_State *, ARMword);
180 static int TORC (ARMul_State *, ARMword);
181 static int WACC (ARMul_State *, ARMword);
182 static int WADD (ARMul_State *, ARMword);
183 static int WALIGNI (ARMword);
184 static int WALIGNR (ARMul_State *, ARMword);
185 static int WAND (ARMword);
186 static int WANDN (ARMword);
187 static int WAVG2 (ARMword);
188 static int WCMPEQ (ARMul_State *, ARMword);
189 static int WCMPGT (ARMul_State *, ARMword);
190 static int WLDR (ARMul_State *, ARMword);
191 static int WMAC (ARMword);
192 static int WMADD (ARMword);
193 static int WMAX (ARMul_State *, ARMword);
194 static int WMIN (ARMul_State *, ARMword);
195 static int WMUL (ARMword);
196 static int WOR (ARMword);
197 static int WPACK (ARMul_State *, ARMword);
198 static int WROR (ARMul_State *, ARMword);
199 static int WSAD (ARMword);
200 static int WSHUFH (ARMword);
201 static int WSLL (ARMul_State *, ARMword);
202 static int WSRA (ARMul_State *, ARMword);
203 static int WSRL (ARMul_State *, ARMword);
204 static int WSTR (ARMul_State *, ARMword);
205 static int WSUB (ARMul_State *, ARMword);
206 static int WUNPCKEH (ARMul_State *, ARMword);
207 static int WUNPCKEL (ARMul_State *, ARMword);
208 static int WUNPCKIH (ARMul_State *, ARMword);
209 static int WUNPCKIL (ARMul_State *, ARMword);
210 static int WXOR (ARMword);
212 /* This function does the work of adding two 32bit values
213 together, and calculating if a carry has occurred. */
222 ARMword result = (a1 + a2);
223 unsigned int uresult = (unsigned int) result;
224 unsigned int ua1 = (unsigned int) a1;
226 /* If (result == a1) and (a2 == 0),
227 or (result > a2) then we have no carry. */
228 * carry_ptr = ((uresult == ua1) ? (a2 != 0) : (uresult < ua1));
230 /* Overflow occurs when both arguments are the
231 same sign, but the result is a different sign. */
232 * overflow_ptr = ( ( (result & sign_mask) && !(a1 & sign_mask) && !(a2 & sign_mask))
233 || (!(result & sign_mask) && (a1 & sign_mask) && (a2 & sign_mask)));
239 AddS32 (ARMdword a1, ARMdword a2, int * carry_ptr, int * overflow_ptr)
242 unsigned int uresult;
249 uresult = (unsigned int) result;
250 ua1 = (unsigned int) a1;
252 * carry_ptr = ((uresult == a1) ? (a2 != 0) : (uresult < ua1));
254 * overflow_ptr = ( ( (result & 0x80000000ULL) && !(a1 & 0x80000000ULL) && !(a2 & 0x80000000ULL))
255 || (!(result & 0x80000000ULL) && (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL)));
261 AddU32 (ARMdword a1, ARMdword a2, int * carry_ptr, int * overflow_ptr)
264 unsigned int uresult;
271 uresult = (unsigned int) result;
272 ua1 = (unsigned int) a1;
274 * carry_ptr = ((uresult == a1) ? (a2 != 0) : (uresult < ua1));
276 * overflow_ptr = ( ( (result & 0x80000000ULL) && !(a1 & 0x80000000ULL) && !(a2 & 0x80000000ULL))
277 || (!(result & 0x80000000ULL) && (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL)));
283 AddS16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
288 return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x8000);
292 AddU16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
297 return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x8000);
301 AddS8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
306 return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x80);
310 AddU8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
315 return Add32 (a1, a2, carry_ptr, overflow_ptr, 0x80);
325 ARMword result = (a1 - a2);
326 unsigned int ua1 = (unsigned int) a1;
327 unsigned int ua2 = (unsigned int) a2;
329 /* A borrow occurs if a2 is (unsigned) larger than a1.
330 However the carry flag is *cleared* if a borrow occurs. */
331 * borrow_ptr = ! (ua2 > ua1);
333 /* Overflow occurs when a negative number is subtracted from a
334 positive number and the result is negative or a positive
335 number is subtracted from a negative number and the result is
337 * overflow_ptr = ( (! (a1 & sign_mask) && (a2 & sign_mask) && (result & sign_mask))
338 || ((a1 & sign_mask) && ! (a2 & sign_mask) && ! (result & sign_mask)));
344 SubS32 (ARMdword a1, ARMdword a2, int * borrow_ptr, int * overflow_ptr)
354 ua1 = (unsigned int) a1;
355 ua2 = (unsigned int) a2;
357 * borrow_ptr = ! (ua2 > ua1);
359 * overflow_ptr = ( (! (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL) && (result & 0x80000000ULL))
360 || ((a1 & 0x80000000ULL) && ! (a2 & 0x80000000ULL) && ! (result & 0x80000000ULL)));
366 SubS16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
371 return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x8000);
375 SubS8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
380 return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x80);
384 SubU16 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
389 return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x8000);
393 SubU8 (ARMword a1, ARMword a2, int * carry_ptr, int * overflow_ptr)
398 return Sub32 (a1, a2, carry_ptr, overflow_ptr, 0x80);
402 SubU32 (ARMdword a1, ARMdword a2, int * borrow_ptr, int * overflow_ptr)
412 ua1 = (unsigned int) a1;
413 ua2 = (unsigned int) a2;
415 * borrow_ptr = ! (ua2 > ua1);
417 * overflow_ptr = ( (! (a1 & 0x80000000ULL) && (a2 & 0x80000000ULL) && (result & 0x80000000ULL))
418 || ((a1 & 0x80000000ULL) && ! (a2 & 0x80000000ULL) && ! (result & 0x80000000ULL)));
423 /* For the saturation. */
426 IwmmxtSaturateU8 (signed short val, int * sat)
449 IwmmxtSaturateS8 (signed short val, int * sat)
471 static unsigned short
472 IwmmxtSaturateU16 (signed int val, int * sat)
481 else if (val > 0xffff)
495 IwmmxtSaturateS16 (signed int val, int * sat)
504 else if (val > 0x7fff)
518 IwmmxtSaturateU32 (signed long long val, int * sat)
527 else if (val > 0xffffffff)
534 rv = val & 0xffffffff;
541 IwmmxtSaturateS32 (signed long long val, int * sat)
545 if (val < -0x80000000LL)
550 else if (val > 0x7fffffff)
557 rv = val & 0xffffffff;
563 /* Intel(r) Wireless MMX(tm) technology Acessor functions. */
566 IwmmxtLDC (ARMul_State * state ATTRIBUTE_UNUSED,
567 unsigned type ATTRIBUTE_UNUSED,
575 IwmmxtSTC (ARMul_State * state ATTRIBUTE_UNUSED,
576 unsigned type ATTRIBUTE_UNUSED,
584 IwmmxtMRC (ARMul_State * state ATTRIBUTE_UNUSED,
585 unsigned type ATTRIBUTE_UNUSED,
593 IwmmxtMCR (ARMul_State * state ATTRIBUTE_UNUSED,
594 unsigned type ATTRIBUTE_UNUSED,
602 IwmmxtCDP (ARMul_State * state, unsigned type, ARMword instr)
607 /* Intel(r) Wireless MMX(tm) technology instruction implementations. */
610 TANDC (ARMul_State * state, ARMword instr)
614 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
618 fprintf (stderr, "tandc\n");
621 /* The Rd field must be r15. */
622 if (BITS (12, 15) != 15)
625 /* The CRn field must be r3. */
626 if (BITS (16, 19) != 3)
629 /* The CRm field must be r0. */
630 if (BITS (0, 3) != 0)
633 cpsr = ARMul_GetCPSR (state) & 0x0fffffff;
635 switch (BITS (22, 23))
638 cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 24, 27)
639 & wCBITS (wCASF, 20, 23) & wCBITS (wCASF, 16, 19)
640 & wCBITS (wCASF, 12, 15) & wCBITS (wCASF, 8, 11)
641 & wCBITS (wCASF, 4, 7) & wCBITS (wCASF, 0, 3)) << 28);
645 cpsr |= ( (wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 20, 23)
646 & wCBITS (wCASF, 12, 15) & wCBITS (wCASF, 4, 7)) << 28);
650 cpsr |= ((wCBITS (wCASF, 28, 31) & wCBITS (wCASF, 12, 15)) << 28);
654 ARMul_UndefInstr (state, instr);
658 ARMul_SetCPSR (state, cpsr);
664 TBCST (ARMul_State * state, ARMword instr)
669 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
673 fprintf (stderr, "tbcst\n");
676 Rn = state->Reg [BITS (12, 15)];
677 if (BITS (12, 15) == 15)
686 wR [wRd] = (Rn << 56) | (Rn << 48) | (Rn << 40) | (Rn << 32)
687 | (Rn << 24) | (Rn << 16) | (Rn << 8) | Rn;
692 wR [wRd] = (Rn << 48) | (Rn << 32) | (Rn << 16) | Rn;
697 wR [wRd] = (Rn << 32) | Rn;
701 ARMul_UndefInstr (state, instr);
705 wC [wCon] |= WCON_MUP;
710 TEXTRC (ARMul_State * state, ARMword instr)
715 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
719 fprintf (stderr, "textrc\n");
722 /* The Rd field must be r15. */
723 if (BITS (12, 15) != 15)
726 /* The CRn field must be r3. */
727 if (BITS (16, 19) != 3)
730 /* The CRm field must be 0xxx. */
734 selector = BITS (0, 2);
735 cpsr = ARMul_GetCPSR (state) & 0x0fffffff;
737 switch (BITS (22, 23))
739 case Bqual: selector *= 4; break;
740 case Hqual: selector = ((selector & 3) * 8) + 4; break;
741 case Wqual: selector = ((selector & 1) * 16) + 12; break;
744 ARMul_UndefInstr (state, instr);
748 cpsr |= wCBITS (wCASF, selector, selector + 3) << 28;
749 ARMul_SetCPSR (state, cpsr);
755 TEXTRM (ARMul_State * state, ARMword instr)
762 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
766 fprintf (stderr, "textrm\n");
771 offset = BITS (0, 2);
773 switch (BITS (22, 23))
777 Rd = wRBITS (wRn, offset, offset + 7);
783 offset = (offset & 3) * 16;
784 Rd = wRBITS (wRn, offset, offset + 15);
790 offset = (offset & 1) * 32;
791 Rd = wRBITS (wRn, offset, offset + 31);
795 ARMul_UndefInstr (state, instr);
799 if (BITS (12, 15) == 15)
800 ARMul_UndefInstr (state, instr);
802 state->Reg [BITS (12, 15)] = Rd;
808 TINSR (ARMul_State * state, ARMword instr)
814 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
818 fprintf (stderr, "tinsr\n");
822 data = state->Reg [BITS (12, 15)];
823 offset = BITS (0, 2);
831 case 0: wR [wRd] = data | (wRBITS (wRd, 8, 63) << 8); break;
832 case 1: wR [wRd] = wRBITS (wRd, 0, 7) | (data << 8) | (wRBITS (wRd, 16, 63) << 16); break;
833 case 2: wR [wRd] = wRBITS (wRd, 0, 15) | (data << 16) | (wRBITS (wRd, 24, 63) << 24); break;
834 case 3: wR [wRd] = wRBITS (wRd, 0, 23) | (data << 24) | (wRBITS (wRd, 32, 63) << 32); break;
835 case 4: wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32) | (wRBITS (wRd, 40, 63) << 40); break;
836 case 5: wR [wRd] = wRBITS (wRd, 0, 39) | (data << 40) | (wRBITS (wRd, 48, 63) << 48); break;
837 case 6: wR [wRd] = wRBITS (wRd, 0, 47) | (data << 48) | (wRBITS (wRd, 56, 63) << 56); break;
838 case 7: wR [wRd] = wRBITS (wRd, 0, 55) | (data << 56); break;
847 case 0: wR [wRd] = data | (wRBITS (wRd, 16, 63) << 16); break;
848 case 1: wR [wRd] = wRBITS (wRd, 0, 15) | (data << 16) | (wRBITS (wRd, 32, 63) << 32); break;
849 case 2: wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32) | (wRBITS (wRd, 48, 63) << 48); break;
850 case 3: wR [wRd] = wRBITS (wRd, 0, 47) | (data << 48); break;
856 wR [wRd] = wRBITS (wRd, 0, 31) | (data << 32);
858 wR [wRd] = (wRBITS (wRd, 32, 63) << 32) | data;
862 ARMul_UndefInstr (state, instr);
866 wC [wCon] |= WCON_MUP;
871 TMCR (ARMul_State * state, ARMword instr)
876 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
880 fprintf (stderr, "tmcr\n");
883 if (BITS (0, 3) != 0)
886 val = state->Reg [BITS (12, 15)];
887 if (BITS (12, 15) == 15)
890 wCreg = BITS (16, 19);
895 /* The wCID register is read only. */
899 /* Writing to the MUP or CUP bits clears them. */
900 wC [wCon] &= ~ (val & 0x3);
904 /* Only the bottom 8 bits can be written to.
905 The higher bits write as zero. */
906 wC [wCSSF] = (val & 0xff);
907 wC [wCon] |= WCON_CUP;
912 wC [wCon] |= WCON_CUP;
920 TMCRR (ARMul_State * state, ARMword instr)
922 ARMdword RdHi = state->Reg [BITS (16, 19)];
923 ARMword RdLo = state->Reg [BITS (12, 15)];
925 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
929 fprintf (stderr, "tmcrr\n");
932 if ((BITS (16, 19) == 15) || (BITS (12, 15) == 15))
935 wR [BITS (0, 3)] = (RdHi << 32) | RdLo;
937 wC [wCon] |= WCON_MUP;
943 TMIA (ARMul_State * state, ARMword instr)
945 signed long long a, b;
947 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
951 fprintf (stderr, "tmia\n");
954 if ((BITS (0, 3) == 15) || (BITS (12, 15) == 15))
956 ARMul_UndefInstr (state, instr);
960 a = state->Reg [BITS (0, 3)];
961 b = state->Reg [BITS (12, 15)];
966 wR [BITS (5, 8)] += a * b;
967 wC [wCon] |= WCON_MUP;
973 TMIAPH (ARMul_State * state, ARMword instr)
975 signed long a, b, result;
977 ARMword Rm = state->Reg [BITS (0, 3)];
978 ARMword Rs = state->Reg [BITS (12, 15)];
980 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
984 fprintf (stderr, "tmiaph\n");
987 if (BITS (0, 3) == 15 || BITS (12, 15) == 15)
989 ARMul_UndefInstr (state, instr);
993 a = SUBSTR (Rs, ARMword, 16, 31);
994 b = SUBSTR (Rm, ARMword, 16, 31);
1004 wR [BITS (5, 8)] += r;
1006 a = SUBSTR (Rs, ARMword, 0, 15);
1007 b = SUBSTR (Rm, ARMword, 0, 15);
1017 wR [BITS (5, 8)] += r;
1018 wC [wCon] |= WCON_MUP;
1024 TMIAxy (ARMul_State * state, ARMword instr)
1030 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1034 fprintf (stderr, "tmiaxy\n");
1037 if (BITS (0, 3) == 15 || BITS (12, 15) == 15)
1039 ARMul_UndefInstr (state, instr);
1043 Rm = state->Reg [BITS (0, 3)];
1049 Rs = state->Reg [BITS (12, 15)];
1064 if (temp & (1 << 31))
1067 wR [BITS (5, 8)] += temp;
1068 wC [wCon] |= WCON_MUP;
1074 TMOVMSK (ARMul_State * state, ARMword instr)
1079 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1083 fprintf (stderr, "tmovmsk\n");
1086 /* The CRm field must be r0. */
1087 if (BITS (0, 3) != 0)
1090 wRn = BITS (16, 19);
1092 switch (BITS (22, 23))
1095 result = ( (wRBITS (wRn, 63, 63) << 7)
1096 | (wRBITS (wRn, 55, 55) << 6)
1097 | (wRBITS (wRn, 47, 47) << 5)
1098 | (wRBITS (wRn, 39, 39) << 4)
1099 | (wRBITS (wRn, 31, 31) << 3)
1100 | (wRBITS (wRn, 23, 23) << 2)
1101 | (wRBITS (wRn, 15, 15) << 1)
1102 | (wRBITS (wRn, 7, 7) << 0));
1106 result = ( (wRBITS (wRn, 63, 63) << 3)
1107 | (wRBITS (wRn, 47, 47) << 2)
1108 | (wRBITS (wRn, 31, 31) << 1)
1109 | (wRBITS (wRn, 15, 15) << 0));
1113 result = (wRBITS (wRn, 63, 63) << 1) | wRBITS (wRn, 31, 31);
1117 ARMul_UndefInstr (state, instr);
1121 state->Reg [BITS (12, 15)] = result;
1127 TMRC (ARMul_State * state, ARMword instr)
1129 int reg = BITS (12, 15);
1131 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1135 fprintf (stderr, "tmrc\n");
1138 if (BITS (0, 3) != 0)
1142 ARMul_UndefInstr (state, instr);
1144 state->Reg [reg] = wC [BITS (16, 19)];
1150 TMRRC (ARMul_State * state, ARMword instr)
1152 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1156 fprintf (stderr, "tmrrc\n");
1159 if ((BITS (16, 19) == 15) || (BITS (12, 15) == 15) || (BITS (4, 11) != 0))
1160 ARMul_UndefInstr (state, instr);
1163 state->Reg [BITS (16, 19)] = wRBITS (BITS (0, 3), 32, 63);
1164 state->Reg [BITS (12, 15)] = wRBITS (BITS (0, 3), 0, 31);
1171 TORC (ARMul_State * state, ARMword instr)
1173 ARMword cpsr = ARMul_GetCPSR (state);
1175 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1179 fprintf (stderr, "torc\n");
1182 /* The Rd field must be r15. */
1183 if (BITS (12, 15) != 15)
1186 /* The CRn field must be r3. */
1187 if (BITS (16, 19) != 3)
1190 /* The CRm field must be r0. */
1191 if (BITS (0, 3) != 0)
1196 switch (BITS (22, 23))
1199 cpsr |= ( (wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 24, 27)
1200 | wCBITS (wCASF, 20, 23) | wCBITS (wCASF, 16, 19)
1201 | wCBITS (wCASF, 12, 15) | wCBITS (wCASF, 8, 11)
1202 | wCBITS (wCASF, 4, 7) | wCBITS (wCASF, 0, 3)) << 28);
1206 cpsr |= ( (wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 20, 23)
1207 | wCBITS (wCASF, 12, 15) | wCBITS (wCASF, 4, 7)) << 28);
1211 cpsr |= ((wCBITS (wCASF, 28, 31) | wCBITS (wCASF, 12, 15)) << 28);
1215 ARMul_UndefInstr (state, instr);
1219 ARMul_SetCPSR (state, cpsr);
1225 WACC (ARMul_State * state, ARMword instr)
1229 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1233 fprintf (stderr, "wacc\n");
1236 wRn = BITS (16, 19);
1238 switch (BITS (22, 23))
1241 wR [BITS (12, 15)] =
1242 wRBITS (wRn, 56, 63) + wRBITS (wRn, 48, 55)
1243 + wRBITS (wRn, 40, 47) + wRBITS (wRn, 32, 39)
1244 + wRBITS (wRn, 24, 31) + wRBITS (wRn, 16, 23)
1245 + wRBITS (wRn, 8, 15) + wRBITS (wRn, 0, 7);
1249 wR [BITS (12, 15)] =
1250 wRBITS (wRn, 48, 63) + wRBITS (wRn, 32, 47)
1251 + wRBITS (wRn, 16, 31) + wRBITS (wRn, 0, 15);
1255 wR [BITS (12, 15)] = wRBITS (wRn, 32, 63) + wRBITS (wRn, 0, 31);
1259 ARMul_UndefInstr (state, instr);
1263 wC [wCon] |= WCON_MUP;
1268 WADD (ARMul_State * state, ARMword instr)
1279 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1283 fprintf (stderr, "wadd\n");
1286 /* Add two numbers using the specified function,
1287 leaving setting the carry bit as required. */
1288 #define ADDx(x, y, m, f) \
1289 (*f) (wRBITS (BITS (16, 19), (x), (y)) & (m), \
1290 wRBITS (BITS ( 0, 3), (x), (y)) & (m), \
1291 & carry, & overflow)
1293 switch (BITS (22, 23))
1296 for (i = 0; i < 8; i++)
1298 switch (BITS (20, 21))
1301 s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddS8);
1302 satrv [BITIDX8 (i)] = 0;
1303 r |= (s & 0xff) << (i * 8);
1304 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
1305 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
1306 SIMD8_SET (psr, carry, SIMD_CBIT, i);
1307 SIMD8_SET (psr, overflow, SIMD_VBIT, i);
1310 case UnsignedSaturation:
1311 s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddU8);
1312 x = IwmmxtSaturateU8 (s, satrv + BITIDX8 (i));
1313 r |= (x & 0xff) << (i * 8);
1314 SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i);
1315 SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i);
1316 if (! satrv [BITIDX8 (i)])
1318 SIMD8_SET (psr, carry, SIMD_CBIT, i);
1319 SIMD8_SET (psr, overflow, SIMD_VBIT, i);
1323 case SignedSaturation:
1324 s = ADDx ((i * 8), (i * 8) + 7, 0xff, AddS8);
1325 x = IwmmxtSaturateS8 (s, satrv + BITIDX8 (i));
1326 r |= (x & 0xff) << (i * 8);
1327 SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i);
1328 SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i);
1329 if (! satrv [BITIDX8 (i)])
1331 SIMD8_SET (psr, carry, SIMD_CBIT, i);
1332 SIMD8_SET (psr, overflow, SIMD_VBIT, i);
1337 ARMul_UndefInstr (state, instr);
1344 satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0;
1346 for (i = 0; i < 4; i++)
1348 switch (BITS (20, 21))
1351 s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddS16);
1352 satrv [BITIDX16 (i)] = 0;
1353 r |= (s & 0xffff) << (i * 16);
1354 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
1355 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
1356 SIMD16_SET (psr, carry, SIMD_CBIT, i);
1357 SIMD16_SET (psr, overflow, SIMD_VBIT, i);
1360 case UnsignedSaturation:
1361 s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddU16);
1362 x = IwmmxtSaturateU16 (s, satrv + BITIDX16 (i));
1363 r |= (x & 0xffff) << (i * 16);
1364 SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i);
1365 SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i);
1366 if (! satrv [BITIDX16 (i)])
1368 SIMD16_SET (psr, carry, SIMD_CBIT, i);
1369 SIMD16_SET (psr, overflow, SIMD_VBIT, i);
1373 case SignedSaturation:
1374 s = ADDx ((i * 16), (i * 16) + 15, 0xffff, AddS16);
1375 x = IwmmxtSaturateS16 (s, satrv + BITIDX16 (i));
1376 r |= (x & 0xffff) << (i * 16);
1377 SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i);
1378 SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i);
1379 if (! satrv [BITIDX16 (i)])
1381 SIMD16_SET (psr, carry, SIMD_CBIT, i);
1382 SIMD16_SET (psr, overflow, SIMD_VBIT, i);
1387 ARMul_UndefInstr (state, instr);
1394 satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0;
1396 for (i = 0; i < 2; i++)
1398 switch (BITS (20, 21))
1401 s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddS32);
1402 satrv [BITIDX32 (i)] = 0;
1403 r |= (s & 0xffffffff) << (i * 32);
1404 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
1405 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
1406 SIMD32_SET (psr, carry, SIMD_CBIT, i);
1407 SIMD32_SET (psr, overflow, SIMD_VBIT, i);
1410 case UnsignedSaturation:
1411 s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddU32);
1412 x = IwmmxtSaturateU32 (s, satrv + BITIDX32 (i));
1413 r |= (x & 0xffffffff) << (i * 32);
1414 SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i);
1415 SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i);
1416 if (! satrv [BITIDX32 (i)])
1418 SIMD32_SET (psr, carry, SIMD_CBIT, i);
1419 SIMD32_SET (psr, overflow, SIMD_VBIT, i);
1423 case SignedSaturation:
1424 s = ADDx ((i * 32), (i * 32) + 31, 0xffffffff, AddS32);
1425 x = IwmmxtSaturateS32 (s, satrv + BITIDX32 (i));
1426 r |= (x & 0xffffffff) << (i * 32);
1427 SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i);
1428 SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i);
1429 if (! satrv [BITIDX32 (i)])
1431 SIMD32_SET (psr, carry, SIMD_CBIT, i);
1432 SIMD32_SET (psr, overflow, SIMD_VBIT, i);
1437 ARMul_UndefInstr (state, instr);
1444 ARMul_UndefInstr (state, instr);
1449 wR [BITS (12, 15)] = r;
1450 wC [wCon] |= (WCON_MUP | WCON_CUP);
1452 SET_wCSSFvec (satrv);
1460 WALIGNI (ARMword instr)
1462 int shift = BITS (20, 22) * 8;
1464 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1468 fprintf (stderr, "waligni\n");
1472 wR [BITS (12, 15)] =
1473 wRBITS (BITS (16, 19), shift, 63)
1474 | (wRBITS (BITS (0, 3), 0, shift) << ((64 - shift)));
1476 wR [BITS (12, 15)] = wR [BITS (16, 19)];
1478 wC [wCon] |= WCON_MUP;
1483 WALIGNR (ARMul_State * state, ARMword instr)
1485 int shift = (wC [BITS (20, 21) + 8] & 0x7) * 8;
1487 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1491 fprintf (stderr, "walignr\n");
1495 wR [BITS (12, 15)] =
1496 wRBITS (BITS (16, 19), shift, 63)
1497 | (wRBITS (BITS (0, 3), 0, shift) << ((64 - shift)));
1499 wR [BITS (12, 15)] = wR [BITS (16, 19)];
1501 wC [wCon] |= WCON_MUP;
1506 WAND (ARMword instr)
1511 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1515 fprintf (stderr, "wand\n");
1518 result = wR [BITS (16, 19)] & wR [BITS (0, 3)];
1519 wR [BITS (12, 15)] = result;
1521 SIMD64_SET (psr, (result == 0), SIMD_ZBIT);
1522 SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT);
1525 wC [wCon] |= (WCON_CUP | WCON_MUP);
1531 WANDN (ARMword instr)
1536 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1540 fprintf (stderr, "wandn\n");
1543 result = wR [BITS (16, 19)] & ~ wR [BITS (0, 3)];
1544 wR [BITS (12, 15)] = result;
1546 SIMD64_SET (psr, (result == 0), SIMD_ZBIT);
1547 SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT);
1550 wC [wCon] |= (WCON_CUP | WCON_MUP);
1556 WAVG2 (ARMword instr)
1562 int round = BIT (20) ? 1 : 0;
1564 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1568 fprintf (stderr, "wavg2\n");
1571 #define AVG2x(x, y, m) (((wRBITS (BITS (16, 19), (x), (y)) & (m)) \
1572 + (wRBITS (BITS ( 0, 3), (x), (y)) & (m)) \
1577 for (i = 0; i < 4; i++)
1579 s = AVG2x ((i * 16), (i * 16) + 15, 0xffff) & 0xffff;
1580 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
1586 for (i = 0; i < 8; i++)
1588 s = AVG2x ((i * 8), (i * 8) + 7, 0xff) & 0xff;
1589 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
1594 wR [BITS (12, 15)] = r;
1596 wC [wCon] |= (WCON_CUP | WCON_MUP);
1602 WCMPEQ (ARMul_State * state, ARMword instr)
1609 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1613 fprintf (stderr, "wcmpeq\n");
1616 switch (BITS (22, 23))
1619 for (i = 0; i < 8; i++)
1621 s = wRBYTE (BITS (16, 19), i) == wRBYTE (BITS (0, 3), i) ? 0xff : 0;
1623 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
1624 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
1629 for (i = 0; i < 4; i++)
1631 s = wRHALF (BITS (16, 19), i) == wRHALF (BITS (0, 3), i) ? 0xffff : 0;
1633 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
1634 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
1639 for (i = 0; i < 2; i++)
1641 s = wRWORD (BITS (16, 19), i) == wRWORD (BITS (0, 3), i) ? 0xffffffff : 0;
1643 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
1644 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
1649 ARMul_UndefInstr (state, instr);
1654 wR [BITS (12, 15)] = r;
1655 wC [wCon] |= (WCON_CUP | WCON_MUP);
1661 WCMPGT (ARMul_State * state, ARMword instr)
1668 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
1672 fprintf (stderr, "wcmpgt\n");
1675 switch (BITS (22, 23))
1680 /* Use a signed comparison. */
1681 for (i = 0; i < 8; i++)
1685 a = wRBYTE (BITS (16, 19), i);
1686 b = wRBYTE (BITS (0, 3), i);
1688 s = (a > b) ? 0xff : 0;
1690 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
1691 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
1696 for (i = 0; i < 8; i++)
1698 s = (wRBYTE (BITS (16, 19), i) > wRBYTE (BITS (0, 3), i))
1701 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
1702 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
1710 for (i = 0; i < 4; i++)
1714 a = wRHALF (BITS (16, 19), i);
1717 b = wRHALF (BITS (0, 3), i);
1720 s = (a > b) ? 0xffff : 0;
1722 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
1723 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
1728 for (i = 0; i < 4; i++)
1730 s = (wRHALF (BITS (16, 19), i) > wRHALF (BITS (0, 3), i))
1733 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
1734 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
1742 for (i = 0; i < 2; i++)
1746 a = EXTEND32 (wRWORD (BITS (16, 19), i));
1747 b = EXTEND32 (wRWORD (BITS (0, 3), i));
1749 s = (a > b) ? 0xffffffff : 0;
1752 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
1753 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
1758 for (i = 0; i < 2; i++)
1760 s = (wRWORD (BITS (16, 19), i) > wRWORD (BITS (0, 3), i))
1763 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
1764 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
1770 ARMul_UndefInstr (state, instr);
1775 wR [BITS (12, 15)] = r;
1776 wC [wCon] |= (WCON_CUP | WCON_MUP);
1782 Compute_Iwmmxt_Address (ARMul_State * state, ARMword instr, int * pFailed)
1791 addr = state->Reg [Rn];
1792 offset = BITS (0, 7);
1793 multiplier = BIT (8) ? 4 : 1;
1795 if (BIT (24)) /* P */
1797 /* Pre Indexed Addressing. */
1799 addr += offset * multiplier;
1801 addr -= offset * multiplier;
1803 /* Immediate Pre-Indexed. */
1804 if (BIT (21)) /* W */
1808 /* Writeback into R15 is UNPREDICTABLE. */
1810 fprintf (stderr, "iWMMXt: writeback into r15\n");
1815 state->Reg [Rn] = addr;
1820 /* Post Indexed Addressing. */
1821 if (BIT (21)) /* W */
1823 /* Handle the write back of the final address. */
1826 /* Writeback into R15 is UNPREDICTABLE. */
1828 fprintf (stderr, "iWMMXt: writeback into r15\n");
1837 increment = offset * multiplier;
1839 increment = - (offset * multiplier);
1841 state->Reg [Rn] = addr + increment;
1846 /* P == 0, W == 0, U == 0 is UNPREDICTABLE. */
1850 fprintf (stderr, "iWMMXt: undefined addressing mode\n");
1861 Iwmmxt_Load_Double_Word (ARMul_State * state, ARMword address)
1865 /* The address must be aligned on a 8 byte boundary. */
1868 fprintf (stderr, "iWMMXt: At addr 0x%x: Unaligned double word load from 0x%x\n",
1869 (state->Reg[15] - 8) & ~0x3, address);
1872 /* No need to check for alignment traps. An unaligned
1873 double word load with alignment trapping disabled is
1875 ARMul_Abort (state, ARMul_DataAbortV);
1878 /* Load the words. */
1879 if (! state->bigendSig)
1881 value = ARMul_LoadWordN (state, address + 4);
1883 value |= ARMul_LoadWordN (state, address);
1887 value = ARMul_LoadWordN (state, address);
1889 value |= ARMul_LoadWordN (state, address + 4);
1892 /* Check for data aborts. */
1894 ARMul_Abort (state, ARMul_DataAbortV);
1896 ARMul_Icycles (state, 2, 0L);
1902 Iwmmxt_Load_Word (ARMul_State * state, ARMword address)
1906 /* Check for a misaligned address. */
1909 if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN))
1910 ARMul_Abort (state, ARMul_DataAbortV);
1915 value = ARMul_LoadWordN (state, address);
1918 ARMul_Abort (state, ARMul_DataAbortV);
1920 ARMul_Icycles (state, 1, 0L);
1926 Iwmmxt_Load_Half_Word (ARMul_State * state, ARMword address)
1930 /* Check for a misaligned address. */
1933 if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN))
1934 ARMul_Abort (state, ARMul_DataAbortV);
1939 value = ARMul_LoadHalfWord (state, address);
1942 ARMul_Abort (state, ARMul_DataAbortV);
1944 ARMul_Icycles (state, 1, 0L);
1950 Iwmmxt_Load_Byte (ARMul_State * state, ARMword address)
1954 value = ARMul_LoadByte (state, address);
1957 ARMul_Abort (state, ARMul_DataAbortV);
1959 ARMul_Icycles (state, 1, 0L);
1965 Iwmmxt_Store_Double_Word (ARMul_State * state, ARMword address, ARMdword value)
1967 /* The address must be aligned on a 8 byte boundary. */
1970 fprintf (stderr, "iWMMXt: At addr 0x%x: Unaligned double word store to 0x%x\n",
1971 (state->Reg[15] - 8) & ~0x3, address);
1974 /* No need to check for alignment traps. An unaligned
1975 double word store with alignment trapping disabled is
1977 ARMul_Abort (state, ARMul_DataAbortV);
1980 /* Store the words. */
1981 if (! state->bigendSig)
1983 ARMul_StoreWordN (state, address, value);
1984 ARMul_StoreWordN (state, address + 4, value >> 32);
1988 ARMul_StoreWordN (state, address + 4, value);
1989 ARMul_StoreWordN (state, address, value >> 32);
1992 /* Check for data aborts. */
1994 ARMul_Abort (state, ARMul_DataAbortV);
1996 ARMul_Icycles (state, 2, 0L);
2000 Iwmmxt_Store_Word (ARMul_State * state, ARMword address, ARMword value)
2002 /* Check for a misaligned address. */
2005 if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN))
2006 ARMul_Abort (state, ARMul_DataAbortV);
2011 ARMul_StoreWordN (state, address, value);
2014 ARMul_Abort (state, ARMul_DataAbortV);
2018 Iwmmxt_Store_Half_Word (ARMul_State * state, ARMword address, ARMword value)
2020 /* Check for a misaligned address. */
2023 if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN))
2024 ARMul_Abort (state, ARMul_DataAbortV);
2029 ARMul_StoreHalfWord (state, address, value);
2032 ARMul_Abort (state, ARMul_DataAbortV);
2036 Iwmmxt_Store_Byte (ARMul_State * state, ARMword address, ARMword value)
2038 ARMul_StoreByte (state, address, value);
2041 ARMul_Abort (state, ARMul_DataAbortV);
2045 WLDR (ARMul_State * state, ARMword instr)
2050 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2054 fprintf (stderr, "wldr\n");
2057 address = Compute_Iwmmxt_Address (state, instr, & failed);
2061 if (BITS (28, 31) == 0xf)
2064 wC [BITS (12, 15)] = Iwmmxt_Load_Word (state, address);
2066 else if (BIT (8) == 0)
2070 wR [BITS (12, 15)] = Iwmmxt_Load_Byte (state, address);
2073 wR [BITS (12, 15)] = Iwmmxt_Load_Half_Word (state, address);
2079 wR [BITS (12, 15)] = Iwmmxt_Load_Word (state, address);
2082 wR [BITS (12, 15)] = Iwmmxt_Load_Double_Word (state, address);
2085 wC [wCon] |= WCON_MUP;
2091 WMAC (ARMword instr)
2097 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2101 fprintf (stderr, "wmac\n");
2104 for (i = 0; i < 4; i++)
2111 a = wRHALF (BITS (16, 19), i);
2114 b = wRHALF (BITS (0, 3), i);
2117 s = (signed long) a * (signed long) b;
2119 t = t + (ARMdword) s;
2124 a = wRHALF (BITS (16, 19), i);
2125 b = wRHALF (BITS ( 0, 3), i);
2137 wR [BITS (12, 15)] = t;
2139 wR[BITS (12, 15)] += t;
2141 wC [wCon] |= WCON_MUP;
2147 WMADD (ARMword instr)
2152 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2156 fprintf (stderr, "wmadd\n");
2159 for (i = 0; i < 2; i++)
2163 if (BIT (21)) /* Signed. */
2167 a = wRHALF (BITS (16, 19), i * 2);
2170 b = wRHALF (BITS (0, 3), i * 2);
2173 s1 = (ARMdword) (a * b);
2175 a = wRHALF (BITS (16, 19), i * 2 + 1);
2178 b = wRHALF (BITS (0, 3), i * 2 + 1);
2181 s2 = (ARMdword) (a * b);
2183 else /* Unsigned. */
2187 a = wRHALF (BITS (16, 19), i * 2);
2188 b = wRHALF (BITS ( 0, 3), i * 2);
2190 s1 = (ARMdword) (a * b);
2192 a = wRHALF (BITS (16, 19), i * 2 + 1);
2193 b = wRHALF (BITS ( 0, 3), i * 2 + 1);
2195 s2 = (ARMdword) a * b;
2198 r |= (ARMdword) ((s1 + s2) & 0xffffffff) << (i ? 32 : 0);
2201 wR [BITS (12, 15)] = r;
2202 wC [wCon] |= WCON_MUP;
2208 WMAX (ARMul_State * state, ARMword instr)
2214 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2218 fprintf (stderr, "wmax\n");
2221 switch (BITS (22, 23))
2224 for (i = 0; i < 8; i++)
2225 if (BIT (21)) /* Signed. */
2229 a = wRBYTE (BITS (16, 19), i);
2232 b = wRBYTE (BITS (0, 3), i);
2240 r |= (s & 0xff) << (i * 8);
2242 else /* Unsigned. */
2246 a = wRBYTE (BITS (16, 19), i);
2247 b = wRBYTE (BITS (0, 3), i);
2254 r |= (s & 0xff) << (i * 8);
2259 for (i = 0; i < 4; i++)
2260 if (BIT (21)) /* Signed. */
2264 a = wRHALF (BITS (16, 19), i);
2267 b = wRHALF (BITS (0, 3), i);
2275 r |= (s & 0xffff) << (i * 16);
2277 else /* Unsigned. */
2281 a = wRHALF (BITS (16, 19), i);
2282 b = wRHALF (BITS (0, 3), i);
2289 r |= (s & 0xffff) << (i * 16);
2294 for (i = 0; i < 2; i++)
2295 if (BIT (21)) /* Signed. */
2299 a = wRWORD (BITS (16, 19), i);
2300 b = wRWORD (BITS (0, 3), i);
2307 r |= (s & 0xffffffff) << (i * 32);
2313 a = wRWORD (BITS (16, 19), i);
2314 b = wRWORD (BITS (0, 3), i);
2321 r |= (s & 0xffffffff) << (i * 32);
2326 ARMul_UndefInstr (state, instr);
2330 wR [BITS (12, 15)] = r;
2331 wC [wCon] |= WCON_MUP;
2337 WMIN (ARMul_State * state, ARMword instr)
2343 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2347 fprintf (stderr, "wmin\n");
2350 switch (BITS (22, 23))
2353 for (i = 0; i < 8; i++)
2354 if (BIT (21)) /* Signed. */
2358 a = wRBYTE (BITS (16, 19), i);
2361 b = wRBYTE (BITS (0, 3), i);
2369 r |= (s & 0xff) << (i * 8);
2371 else /* Unsigned. */
2375 a = wRBYTE (BITS (16, 19), i);
2376 b = wRBYTE (BITS (0, 3), i);
2383 r |= (s & 0xff) << (i * 8);
2388 for (i = 0; i < 4; i++)
2389 if (BIT (21)) /* Signed. */
2393 a = wRHALF (BITS (16, 19), i);
2396 b = wRHALF (BITS (0, 3), i);
2404 r |= (s & 0xffff) << (i * 16);
2411 a = wRHALF (BITS (16, 19), i);
2412 b = wRHALF (BITS ( 0, 3), i);
2419 r |= (s & 0xffff) << (i * 16);
2424 for (i = 0; i < 2; i++)
2425 if (BIT (21)) /* Signed. */
2429 a = wRWORD (BITS (16, 19), i);
2430 b = wRWORD (BITS ( 0, 3), i);
2437 r |= (s & 0xffffffff) << (i * 32);
2443 a = wRWORD (BITS (16, 19), i);
2444 b = wRWORD (BITS (0, 3), i);
2451 r |= (s & 0xffffffff) << (i * 32);
2456 ARMul_UndefInstr (state, instr);
2460 wR [BITS (12, 15)] = r;
2461 wC [wCon] |= WCON_MUP;
2467 WMUL (ARMword instr)
2473 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2477 fprintf (stderr, "wmul\n");
2480 for (i = 0; i < 4; i++)
2481 if (BIT (21)) /* Signed. */
2485 a = wRHALF (BITS (16, 19), i);
2488 b = wRHALF (BITS (0, 3), i);
2494 r |= ((s >> 16) & 0xffff) << (i * 16);
2496 r |= (s & 0xffff) << (i * 16);
2498 else /* Unsigned. */
2502 a = wRHALF (BITS (16, 19), i);
2503 b = wRHALF (BITS (0, 3), i);
2508 r |= ((s >> 16) & 0xffff) << (i * 16);
2510 r |= (s & 0xffff) << (i * 16);
2513 wR [BITS (12, 15)] = r;
2514 wC [wCon] |= WCON_MUP;
2525 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2529 fprintf (stderr, "wor\n");
2532 result = wR [BITS (16, 19)] | wR [BITS (0, 3)];
2533 wR [BITS (12, 15)] = result;
2535 SIMD64_SET (psr, (result == 0), SIMD_ZBIT);
2536 SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT);
2539 wC [wCon] |= (WCON_CUP | WCON_MUP);
2545 WPACK (ARMul_State * state, ARMword instr)
2554 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2558 fprintf (stderr, "wpack\n");
2561 switch (BITS (22, 23))
2564 for (i = 0; i < 8; i++)
2566 x = wRHALF (i < 4 ? BITS (16, 19) : BITS (0, 3), i & 3);
2568 switch (BITS (20, 21))
2570 case UnsignedSaturation:
2571 s = IwmmxtSaturateU8 (x, satrv + BITIDX8 (i));
2574 case SignedSaturation:
2575 s = IwmmxtSaturateS8 (x, satrv + BITIDX8 (i));
2579 ARMul_UndefInstr (state, instr);
2583 r |= (s & 0xff) << (i * 8);
2584 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
2585 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
2590 satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0;
2592 for (i = 0; i < 4; i++)
2594 x = wRWORD (i < 2 ? BITS (16, 19) : BITS (0, 3), i & 1);
2596 switch (BITS (20, 21))
2598 case UnsignedSaturation:
2599 s = IwmmxtSaturateU16 (x, satrv + BITIDX16 (i));
2602 case SignedSaturation:
2603 s = IwmmxtSaturateS16 (x, satrv + BITIDX16 (i));
2607 ARMul_UndefInstr (state, instr);
2611 r |= (s & 0xffff) << (i * 16);
2612 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
2613 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
2618 satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0;
2620 for (i = 0; i < 2; i++)
2622 x = wR [i ? BITS (0, 3) : BITS (16, 19)];
2624 switch (BITS (20, 21))
2626 case UnsignedSaturation:
2627 s = IwmmxtSaturateU32 (x, satrv + BITIDX32 (i));
2630 case SignedSaturation:
2631 s = IwmmxtSaturateS32 (x, satrv + BITIDX32 (i));
2635 ARMul_UndefInstr (state, instr);
2639 r |= (s & 0xffffffff) << (i * 32);
2640 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
2641 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
2646 ARMul_UndefInstr (state, instr);
2651 wR [BITS (12, 15)] = r;
2652 SET_wCSSFvec (satrv);
2653 wC [wCon] |= (WCON_CUP | WCON_MUP);
2659 WROR (ARMul_State * state, ARMword instr)
2667 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2671 fprintf (stderr, "wror\n");
2674 DECODE_G_BIT (state, instr, shift);
2676 switch (BITS (22, 23))
2680 for (i = 0; i < 4; i++)
2682 s = ((wRHALF (BITS (16, 19), i) & 0xffff) << (16 - shift))
2683 | ((wRHALF (BITS (16, 19), i) & 0xffff) >> shift);
2684 r |= (s & 0xffff) << (i * 16);
2685 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
2686 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
2692 for (i = 0; i < 2; i++)
2694 s = ((wRWORD (BITS (16, 19), i) & 0xffffffff) << (32 - shift))
2695 | ((wRWORD (BITS (16, 19), i) & 0xffffffff) >> shift);
2696 r |= (s & 0xffffffff) << (i * 32);
2697 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
2698 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
2704 r = (wR [BITS (16, 19)] >> shift)
2705 | (wR [BITS (16, 19)] << (64 - shift));
2707 SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
2708 SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
2712 ARMul_UndefInstr (state, instr);
2717 wR [BITS (12, 15)] = r;
2718 wC [wCon] |= (WCON_CUP | WCON_MUP);
2724 WSAD (ARMword instr)
2730 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2734 fprintf (stderr, "wsad\n");
2738 r = BIT (20) ? 0 : (wR [BITS (12, 15)] & 0xffffffff);
2742 for (i = 0; i < 4; i++)
2744 s = (wRHALF (BITS (16, 19), i) - wRHALF (BITS (0, 3), i));
2749 for (i = 0; i < 8; i++)
2751 s = (wRBYTE (BITS (16, 19), i) - wRBYTE (BITS (0, 3), i));
2755 wR [BITS (12, 15)] = r;
2756 wC [wCon] |= WCON_MUP;
2762 WSHUFH (ARMword instr)
2770 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2774 fprintf (stderr, "wshufh\n");
2777 imm8 = (BITS (20, 23) << 4) | BITS (0, 3);
2779 for (i = 0; i < 4; i++)
2781 s = wRHALF (BITS (16, 19), ((imm8 >> (i * 2) & 3)) & 0xff);
2782 r |= (s & 0xffff) << (i * 16);
2783 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
2784 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
2788 wR [BITS (12, 15)] = r;
2789 wC [wCon] |= (WCON_CUP | WCON_MUP);
2795 WSLL (ARMul_State * state, ARMword instr)
2803 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2807 fprintf (stderr, "wsll\n");
2810 DECODE_G_BIT (state, instr, shift);
2812 switch (BITS (22, 23))
2815 for (i = 0; i < 4; i++)
2820 s = ((wRHALF (BITS (16, 19), i) & 0xffff) << shift);
2821 r |= (s & 0xffff) << (i * 16);
2822 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
2823 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
2828 for (i = 0; i < 2; i++)
2833 s = ((wRWORD (BITS (16, 19), i) & 0xffffffff) << shift);
2834 r |= (s & 0xffffffff) << (i * 32);
2835 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
2836 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
2844 r = ((wR[BITS (16, 19)] & 0xffffffffffffffffULL) << shift);
2846 SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
2847 SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
2851 ARMul_UndefInstr (state, instr);
2856 wR [BITS (12, 15)] = r;
2857 wC [wCon] |= (WCON_CUP | WCON_MUP);
2863 WSRA (ARMul_State * state, ARMword instr)
2872 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2876 fprintf (stderr, "wsra\n");
2879 DECODE_G_BIT (state, instr, shift);
2881 switch (BITS (22, 23))
2884 for (i = 0; i < 4; i++)
2887 t = (wRHALF (BITS (16, 19), i) & 0x8000) ? 0xffff : 0;
2890 t = wRHALF (BITS (16, 19), i);
2896 r |= (s & 0xffff) << (i * 16);
2897 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
2898 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
2903 for (i = 0; i < 2; i++)
2906 t = (wRWORD (BITS (16, 19), i) & 0x80000000) ? 0xffffffff : 0;
2909 t = EXTEND32 (wRWORD (BITS (16, 19), i));
2913 r |= (s & 0xffffffff) << (i * 32);
2914 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
2915 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
2921 r = (wR [BITS (16, 19)] & 0x8000000000000000ULL) ? 0xffffffffffffffffULL : 0;
2923 r = ((signed long long) (wR[BITS (16, 19)] & 0xffffffffffffffffULL) >> shift);
2924 SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
2925 SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
2929 ARMul_UndefInstr (state, instr);
2934 wR [BITS (12, 15)] = r;
2935 wC [wCon] |= (WCON_CUP | WCON_MUP);
2941 WSRL (ARMul_State * state, ARMword instr)
2949 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
2953 fprintf (stderr, "wsrl\n");
2956 DECODE_G_BIT (state, instr, shift);
2958 switch (BITS (22, 23))
2961 for (i = 0; i < 4; i++)
2966 s = ((unsigned) (wRHALF (BITS (16, 19), i) & 0xffff) >> shift);
2968 r |= (s & 0xffff) << (i * 16);
2969 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
2970 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
2975 for (i = 0; i < 2; i++)
2980 s = ((unsigned long) (wRWORD (BITS (16, 19), i) & 0xffffffff) >> shift);
2982 r |= (s & 0xffffffff) << (i * 32);
2983 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
2984 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
2992 r = (wR [BITS (16, 19)] & 0xffffffffffffffffULL) >> shift;
2994 SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
2995 SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
2999 ARMul_UndefInstr (state, instr);
3004 wR [BITS (12, 15)] = r;
3005 wC [wCon] |= (WCON_CUP | WCON_MUP);
3011 WSTR (ARMul_State * state, ARMword instr)
3017 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3021 fprintf (stderr, "wstr\n");
3024 address = Compute_Iwmmxt_Address (state, instr, & failed);
3028 if (BITS (28, 31) == 0xf)
3031 Iwmmxt_Store_Word (state, address, wC [BITS (12, 15)]);
3033 else if (BIT (8) == 0)
3037 Iwmmxt_Store_Byte (state, address, wR [BITS (12, 15)]);
3040 Iwmmxt_Store_Half_Word (state, address, wR [BITS (12, 15)]);
3046 Iwmmxt_Store_Word (state, address, wR [BITS (12, 15)]);
3049 Iwmmxt_Store_Double_Word (state, address, wR [BITS (12, 15)]);
3056 WSUB (ARMul_State * state, ARMword instr)
3067 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3071 fprintf (stderr, "wsub\n");
3074 /* Subtract two numbers using the specified function,
3075 leaving setting the carry bit as required. */
3076 #define SUBx(x, y, m, f) \
3077 (*f) (wRBITS (BITS (16, 19), (x), (y)) & (m), \
3078 wRBITS (BITS ( 0, 3), (x), (y)) & (m), & carry, & overflow)
3080 switch (BITS (22, 23))
3083 for (i = 0; i < 8; i++)
3085 switch (BITS (20, 21))
3088 s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubS8);
3089 satrv [BITIDX8 (i)] = 0;
3090 r |= (s & 0xff) << (i * 8);
3091 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i);
3092 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i);
3093 SIMD8_SET (psr, carry, SIMD_CBIT, i);
3094 SIMD8_SET (psr, overflow, SIMD_VBIT, i);
3097 case UnsignedSaturation:
3098 s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubU8);
3099 x = IwmmxtSaturateU8 (s, satrv + BITIDX8 (i));
3100 r |= (x & 0xff) << (i * 8);
3101 SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i);
3102 SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i);
3103 if (! satrv [BITIDX8 (i)])
3105 SIMD8_SET (psr, carry, SIMD_CBIT, i);
3106 SIMD8_SET (psr, overflow, SIMD_VBIT, i);
3110 case SignedSaturation:
3111 s = SUBx ((i * 8), (i * 8) + 7, 0xff, SubS8);
3112 x = IwmmxtSaturateS8 (s, satrv + BITIDX8 (i));
3113 r |= (x & 0xff) << (i * 8);
3114 SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i);
3115 SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i);
3116 if (! satrv [BITIDX8 (i)])
3118 SIMD8_SET (psr, carry, SIMD_CBIT, i);
3119 SIMD8_SET (psr, overflow, SIMD_VBIT, i);
3124 ARMul_UndefInstr (state, instr);
3131 satrv[0] = satrv[2] = satrv[4] = satrv[6] = 0;
3133 for (i = 0; i < 4; i++)
3135 switch (BITS (20, 21))
3138 s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubU16);
3139 satrv [BITIDX16 (i)] = 0;
3140 r |= (s & 0xffff) << (i * 16);
3141 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
3142 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
3143 SIMD16_SET (psr, carry, SIMD_CBIT, i);
3144 SIMD16_SET (psr, overflow, SIMD_VBIT, i);
3147 case UnsignedSaturation:
3148 s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubU16);
3149 x = IwmmxtSaturateU16 (s, satrv + BITIDX16 (i));
3150 r |= (x & 0xffff) << (i * 16);
3151 SIMD16_SET (psr, NBIT16 (x & 0xffff), SIMD_NBIT, i);
3152 SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i);
3153 if (! satrv [BITIDX16 (i)])
3155 SIMD16_SET (psr, carry, SIMD_CBIT, i);
3156 SIMD16_SET (psr, overflow, SIMD_VBIT, i);
3160 case SignedSaturation:
3161 s = SUBx ((i * 16), (i * 16) + 15, 0xffff, SubS16);
3162 x = IwmmxtSaturateS16 (s, satrv + BITIDX16 (i));
3163 r |= (x & 0xffff) << (i * 16);
3164 SIMD16_SET (psr, NBIT16 (x), SIMD_NBIT, i);
3165 SIMD16_SET (psr, ZBIT16 (x), SIMD_ZBIT, i);
3166 if (! satrv [BITIDX16 (i)])
3168 SIMD16_SET (psr, carry, SIMD_CBIT, i);
3169 SIMD16_SET (psr, overflow, SIMD_VBIT, i);
3174 ARMul_UndefInstr (state, instr);
3181 satrv[0] = satrv[1] = satrv[2] = satrv[4] = satrv[5] = satrv[6] = 0;
3183 for (i = 0; i < 2; i++)
3185 switch (BITS (20, 21))
3188 s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubU32);
3189 satrv[BITIDX32 (i)] = 0;
3190 r |= (s & 0xffffffff) << (i * 32);
3191 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
3192 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
3193 SIMD32_SET (psr, carry, SIMD_CBIT, i);
3194 SIMD32_SET (psr, overflow, SIMD_VBIT, i);
3197 case UnsignedSaturation:
3198 s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubU32);
3199 x = IwmmxtSaturateU32 (s, satrv + BITIDX32 (i));
3200 r |= (x & 0xffffffff) << (i * 32);
3201 SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i);
3202 SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i);
3203 if (! satrv [BITIDX32 (i)])
3205 SIMD32_SET (psr, carry, SIMD_CBIT, i);
3206 SIMD32_SET (psr, overflow, SIMD_VBIT, i);
3210 case SignedSaturation:
3211 s = SUBx ((i * 32), (i * 32) + 31, 0xffffffff, SubS32);
3212 x = IwmmxtSaturateS32 (s, satrv + BITIDX32 (i));
3213 r |= (x & 0xffffffff) << (i * 32);
3214 SIMD32_SET (psr, NBIT32 (x), SIMD_NBIT, i);
3215 SIMD32_SET (psr, ZBIT32 (x), SIMD_ZBIT, i);
3216 if (! satrv [BITIDX32 (i)])
3218 SIMD32_SET (psr, carry, SIMD_CBIT, i);
3219 SIMD32_SET (psr, overflow, SIMD_VBIT, i);
3224 ARMul_UndefInstr (state, instr);
3231 ARMul_UndefInstr (state, instr);
3235 wR [BITS (12, 15)] = r;
3237 SET_wCSSFvec (satrv);
3238 wC [wCon] |= (WCON_CUP | WCON_MUP);
3246 WUNPCKEH (ARMul_State * state, ARMword instr)
3253 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3257 fprintf (stderr, "wunpckeh\n");
3260 switch (BITS (22, 23))
3263 for (i = 0; i < 4; i++)
3265 s = wRBYTE (BITS (16, 19), i + 4);
3267 if (BIT (21) && NBIT8 (s))
3270 r |= (s & 0xffff) << (i * 16);
3271 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
3272 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
3277 for (i = 0; i < 2; i++)
3279 s = wRHALF (BITS (16, 19), i + 2);
3281 if (BIT (21) && NBIT16 (s))
3284 r |= (s & 0xffffffff) << (i * 32);
3285 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
3286 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
3291 r = wRWORD (BITS (16, 19), 1);
3293 if (BIT (21) && NBIT32 (r))
3294 r |= 0xffffffff00000000ULL;
3296 SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
3297 SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
3301 ARMul_UndefInstr (state, instr);
3306 wR [BITS (12, 15)] = r;
3307 wC [wCon] |= (WCON_CUP | WCON_MUP);
3313 WUNPCKEL (ARMul_State * state, ARMword instr)
3320 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3324 fprintf (stderr, "wunpckel\n");
3327 switch (BITS (22, 23))
3330 for (i = 0; i < 4; i++)
3332 s = wRBYTE (BITS (16, 19), i);
3334 if (BIT (21) && NBIT8 (s))
3337 r |= (s & 0xffff) << (i * 16);
3338 SIMD16_SET (psr, NBIT16 (s), SIMD_NBIT, i);
3339 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i);
3344 for (i = 0; i < 2; i++)
3346 s = wRHALF (BITS (16, 19), i);
3348 if (BIT (21) && NBIT16 (s))
3351 r |= (s & 0xffffffff) << (i * 32);
3352 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, i);
3353 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, i);
3358 r = wRWORD (BITS (16, 19), 0);
3360 if (BIT (21) && NBIT32 (r))
3361 r |= 0xffffffff00000000ULL;
3363 SIMD64_SET (psr, NBIT64 (r), SIMD_NBIT);
3364 SIMD64_SET (psr, ZBIT64 (r), SIMD_ZBIT);
3368 ARMul_UndefInstr (state, instr);
3373 wR [BITS (12, 15)] = r;
3374 wC [wCon] |= (WCON_CUP | WCON_MUP);
3380 WUNPCKIH (ARMul_State * state, ARMword instr)
3388 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3392 fprintf (stderr, "wunpckih\n");
3395 switch (BITS (22, 23))
3398 for (i = 0; i < 4; i++)
3400 a = wRBYTE (BITS (16, 19), i + 4);
3401 b = wRBYTE (BITS ( 0, 3), i + 4);
3403 r |= (s & 0xffff) << (i * 16);
3404 SIMD8_SET (psr, NBIT8 (a), SIMD_NBIT, i * 2);
3405 SIMD8_SET (psr, ZBIT8 (a), SIMD_ZBIT, i * 2);
3406 SIMD8_SET (psr, NBIT8 (b), SIMD_NBIT, (i * 2) + 1);
3407 SIMD8_SET (psr, ZBIT8 (b), SIMD_ZBIT, (i * 2) + 1);
3412 for (i = 0; i < 2; i++)
3414 a = wRHALF (BITS (16, 19), i + 2);
3415 b = wRHALF (BITS ( 0, 3), i + 2);
3417 r |= (s & 0xffffffff) << (i * 32);
3418 SIMD16_SET (psr, NBIT16 (a), SIMD_NBIT, (i * 2));
3419 SIMD16_SET (psr, ZBIT16 (a), SIMD_ZBIT, (i * 2));
3420 SIMD16_SET (psr, NBIT16 (b), SIMD_NBIT, (i * 2) + 1);
3421 SIMD16_SET (psr, ZBIT16 (b), SIMD_ZBIT, (i * 2) + 1);
3426 a = wRWORD (BITS (16, 19), 1);
3427 s = wRWORD (BITS ( 0, 3), 1);
3430 SIMD32_SET (psr, NBIT32 (a), SIMD_NBIT, 0);
3431 SIMD32_SET (psr, ZBIT32 (a), SIMD_ZBIT, 0);
3432 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, 1);
3433 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, 1);
3437 ARMul_UndefInstr (state, instr);
3442 wR [BITS (12, 15)] = r;
3443 wC [wCon] |= (WCON_CUP | WCON_MUP);
3449 WUNPCKIL (ARMul_State * state, ARMword instr)
3457 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3461 fprintf (stderr, "wunpckil\n");
3464 switch (BITS (22, 23))
3467 for (i = 0; i < 4; i++)
3469 a = wRBYTE (BITS (16, 19), i);
3470 b = wRBYTE (BITS ( 0, 3), i);
3472 r |= (s & 0xffff) << (i * 16);
3473 SIMD8_SET (psr, NBIT8 (a), SIMD_NBIT, i * 2);
3474 SIMD8_SET (psr, ZBIT8 (a), SIMD_ZBIT, i * 2);
3475 SIMD8_SET (psr, NBIT8 (b), SIMD_NBIT, (i * 2) + 1);
3476 SIMD8_SET (psr, ZBIT8 (b), SIMD_ZBIT, (i * 2) + 1);
3481 for (i = 0; i < 2; i++)
3483 a = wRHALF (BITS (16, 19), i);
3484 b = wRHALF (BITS ( 0, 3), i);
3486 r |= (s & 0xffffffff) << (i * 32);
3487 SIMD16_SET (psr, NBIT16 (a), SIMD_NBIT, (i * 2));
3488 SIMD16_SET (psr, ZBIT16 (a), SIMD_ZBIT, (i * 2));
3489 SIMD16_SET (psr, NBIT16 (b), SIMD_NBIT, (i * 2) + 1);
3490 SIMD16_SET (psr, ZBIT16 (b), SIMD_ZBIT, (i * 2) + 1);
3495 a = wRWORD (BITS (16, 19), 0);
3496 s = wRWORD (BITS ( 0, 3), 0);
3499 SIMD32_SET (psr, NBIT32 (a), SIMD_NBIT, 0);
3500 SIMD32_SET (psr, ZBIT32 (a), SIMD_ZBIT, 0);
3501 SIMD32_SET (psr, NBIT32 (s), SIMD_NBIT, 1);
3502 SIMD32_SET (psr, ZBIT32 (s), SIMD_ZBIT, 1);
3506 ARMul_UndefInstr (state, instr);
3511 wR [BITS (12, 15)] = r;
3512 wC [wCon] |= (WCON_CUP | WCON_MUP);
3518 WXOR (ARMword instr)
3523 if ((read_cp15_reg (15, 0, 1) & 3) != 3)
3527 fprintf (stderr, "wxor\n");
3530 result = wR [BITS (16, 19)] ^ wR [BITS (0, 3)];
3531 wR [BITS (12, 15)] = result;
3533 SIMD64_SET (psr, (result == 0), SIMD_ZBIT);
3534 SIMD64_SET (psr, (result & (1ULL << 63)), SIMD_NBIT);
3537 wC [wCon] |= (WCON_CUP | WCON_MUP);
3542 /* This switch table is moved to a seperate function in order
3543 to work around a compiler bug in the host compiler... */
3546 Process_Instruction (ARMul_State * state, ARMword instr)
3548 int status = ARMul_BUSY;
3550 switch ((BITS (20, 23) << 8) | BITS (4, 11))
3552 case 0x000: status = WOR (instr); break;
3553 case 0x011: status = TMCR (state, instr); break;
3554 case 0x100: status = WXOR (instr); break;
3555 case 0x111: status = TMRC (state, instr); break;
3556 case 0x300: status = WANDN (instr); break;
3557 case 0x200: status = WAND (instr); break;
3559 case 0x810: case 0xa10:
3560 status = WMADD (instr); break;
3562 case 0x10e: case 0x50e: case 0x90e: case 0xd0e:
3563 status = WUNPCKIL (state, instr); break;
3564 case 0x10c: case 0x50c: case 0x90c: case 0xd0c:
3565 status = WUNPCKIH (state, instr); break;
3566 case 0x012: case 0x112: case 0x412: case 0x512:
3567 status = WSAD (instr); break;
3568 case 0x010: case 0x110: case 0x210: case 0x310:
3569 status = WMUL (instr); break;
3570 case 0x410: case 0x510: case 0x610: case 0x710:
3571 status = WMAC (instr); break;
3572 case 0x006: case 0x406: case 0x806: case 0xc06:
3573 status = WCMPEQ (state, instr); break;
3574 case 0x800: case 0x900: case 0xc00: case 0xd00:
3575 status = WAVG2 (instr); break;
3576 case 0x802: case 0x902: case 0xa02: case 0xb02:
3577 status = WALIGNR (state, instr); break;
3578 case 0x601: case 0x605: case 0x609: case 0x60d:
3579 status = TINSR (state, instr); break;
3580 case 0x107: case 0x507: case 0x907: case 0xd07:
3581 status = TEXTRM (state, instr); break;
3582 case 0x117: case 0x517: case 0x917: case 0xd17:
3583 status = TEXTRC (state, instr); break;
3584 case 0x401: case 0x405: case 0x409: case 0x40d:
3585 status = TBCST (state, instr); break;
3586 case 0x113: case 0x513: case 0x913: case 0xd13:
3587 status = TANDC (state, instr); break;
3588 case 0x01c: case 0x41c: case 0x81c: case 0xc1c:
3589 status = WACC (state, instr); break;
3590 case 0x115: case 0x515: case 0x915: case 0xd15:
3591 status = TORC (state, instr); break;
3592 case 0x103: case 0x503: case 0x903: case 0xd03:
3593 status = TMOVMSK (state, instr); break;
3594 case 0x106: case 0x306: case 0x506: case 0x706:
3595 case 0x906: case 0xb06: case 0xd06: case 0xf06:
3596 status = WCMPGT (state, instr); break;
3597 case 0x00e: case 0x20e: case 0x40e: case 0x60e:
3598 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
3599 status = WUNPCKEL (state, instr); break;
3600 case 0x00c: case 0x20c: case 0x40c: case 0x60c:
3601 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
3602 status = WUNPCKEH (state, instr); break;
3603 case 0x204: case 0x604: case 0xa04: case 0xe04:
3604 case 0x214: case 0x614: case 0xa14: case 0xe14:
3605 status = WSRL (state, instr); break;
3606 case 0x004: case 0x404: case 0x804: case 0xc04:
3607 case 0x014: case 0x414: case 0x814: case 0xc14:
3608 status = WSRA (state, instr); break;
3609 case 0x104: case 0x504: case 0x904: case 0xd04:
3610 case 0x114: case 0x514: case 0x914: case 0xd14:
3611 status = WSLL (state, instr); break;
3612 case 0x304: case 0x704: case 0xb04: case 0xf04:
3613 case 0x314: case 0x714: case 0xb14: case 0xf14:
3614 status = WROR (state, instr); break;
3615 case 0x116: case 0x316: case 0x516: case 0x716:
3616 case 0x916: case 0xb16: case 0xd16: case 0xf16:
3617 status = WMIN (state, instr); break;
3618 case 0x016: case 0x216: case 0x416: case 0x616:
3619 case 0x816: case 0xa16: case 0xc16: case 0xe16:
3620 status = WMAX (state, instr); break;
3621 case 0x002: case 0x102: case 0x202: case 0x302:
3622 case 0x402: case 0x502: case 0x602: case 0x702:
3623 status = WALIGNI (instr); break;
3624 case 0x01a: case 0x11a: case 0x21a: case 0x31a:
3625 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
3626 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
3627 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
3628 status = WSUB (state, instr); break;
3629 case 0x01e: case 0x11e: case 0x21e: case 0x31e:
3630 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
3631 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
3632 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
3633 status = WSHUFH (instr); break;
3634 case 0x018: case 0x118: case 0x218: case 0x318:
3635 case 0x418: case 0x518: case 0x618: case 0x718:
3636 case 0x818: case 0x918: case 0xa18: case 0xb18:
3637 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
3638 status = WADD (state, instr); break;
3639 case 0x008: case 0x108: case 0x208: case 0x308:
3640 case 0x408: case 0x508: case 0x608: case 0x708:
3641 case 0x808: case 0x908: case 0xa08: case 0xb08:
3642 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
3643 status = WPACK (state, instr); break;
3644 case 0x201: case 0x203: case 0x205: case 0x207:
3645 case 0x209: case 0x20b: case 0x20d: case 0x20f:
3646 case 0x211: case 0x213: case 0x215: case 0x217:
3647 case 0x219: case 0x21b: case 0x21d: case 0x21f:
3648 switch (BITS (16, 19))
3650 case 0x0: status = TMIA (state, instr); break;
3651 case 0x8: status = TMIAPH (state, instr); break;
3655 case 0xf: status = TMIAxy (state, instr); break;
3665 /* Process a possibly Intel(r) Wireless MMX(tm) technology instruction.
3666 Return true if the instruction was handled. */
3669 ARMul_HandleIwmmxt (ARMul_State * state, ARMword instr)
3671 int status = ARMul_BUSY;
3673 if (BITS (24, 27) == 0xe)
3675 status = Process_Instruction (state, instr);
3677 else if (BITS (25, 27) == 0x6)
3679 if (BITS (4, 11) == 0x0 && BITS (20, 24) == 0x4)
3680 status = TMCRR (state, instr);
3681 else if (BITS (9, 11) == 0x0)
3683 if (BIT (20) == 0x0)
3684 status = WSTR (state, instr);
3685 else if (BITS (20, 24) == 0x5)
3686 status = TMRRC (state, instr);
3688 status = WLDR (state, instr);
3692 if (status == ARMul_CANT)
3694 /* If the instruction was a recognised but illegal,
3695 perform the abort here rather than returning false.
3696 If we return false then ARMul_MRC may be called which
3697 will still abort, but which also perform the register
3699 ARMul_Abort (state, ARMul_UndefinedInstrV);
3700 status = ARMul_DONE;
3703 return status == ARMul_DONE;
3707 Fetch_Iwmmxt_Register (unsigned int regnum, unsigned char * memory)
3711 memcpy (memory, wC + (regnum - 16), sizeof wC [0]);
3712 return sizeof wC [0];
3716 memcpy (memory, wR + regnum, sizeof wR [0]);
3717 return sizeof wR [0];
3722 Store_Iwmmxt_Register (unsigned int regnum, unsigned char * memory)
3726 memcpy (wC + (regnum - 16), memory, sizeof wC [0]);
3727 return sizeof wC [0];
3731 memcpy (wR + regnum, memory, sizeof wR [0]);
3732 return sizeof wR [0];