1 /* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 /***************************************************************************\
23 * Definitions for the support routines *
24 \***************************************************************************/
26 ARMword ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg);
27 void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
29 ARMword ARMul_GetPC (ARMul_State * state);
30 ARMword ARMul_GetNextPC (ARMul_State * state);
31 void ARMul_SetPC (ARMul_State * state, ARMword value);
32 ARMword ARMul_GetR15 (ARMul_State * state);
33 void ARMul_SetR15 (ARMul_State * state, ARMword value);
35 ARMword ARMul_GetCPSR (ARMul_State * state);
36 void ARMul_SetCPSR (ARMul_State * state, ARMword value);
37 ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
38 void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
40 void ARMul_CPSRAltered (ARMul_State * state);
41 void ARMul_R15Altered (ARMul_State * state);
43 ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode,
45 static ARMword ModeToBank (ARMword mode);
47 unsigned ARMul_NthReg (ARMword instr, unsigned number);
49 void ARMul_NegZero (ARMul_State * state, ARMword result);
50 void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b,
52 void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b,
54 void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b,
56 void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b,
59 void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address);
60 void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address);
61 void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source);
62 ARMword ARMul_MRC (ARMul_State * state, ARMword instr);
63 void ARMul_CDP (ARMul_State * state, ARMword instr);
64 unsigned IntPending (ARMul_State * state);
66 ARMword ARMul_Align (ARMul_State * state, ARMword address, ARMword data);
68 void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
70 void ARMul_EnvokeEvent (ARMul_State * state);
71 unsigned long ARMul_Time (ARMul_State * state);
72 static void EnvokeList (ARMul_State * state, unsigned long from,
76 { /* An event list node */
77 unsigned (*func) (); /* The function to call */
78 struct EventNode *next;
81 /***************************************************************************\
82 * This routine returns the value of a register from a mode. *
83 \***************************************************************************/
86 ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg)
89 if (mode != state->Mode)
90 return (state->RegBank[ModeToBank ((ARMword) mode)][reg]);
92 return (state->Reg[reg]);
95 /***************************************************************************\
96 * This routine sets the value of a register for a mode. *
97 \***************************************************************************/
100 ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value)
103 if (mode != state->Mode)
104 state->RegBank[ModeToBank ((ARMword) mode)][reg] = value;
106 state->Reg[reg] = value;
109 /***************************************************************************\
110 * This routine returns the value of the PC, mode independently. *
111 \***************************************************************************/
114 ARMul_GetPC (ARMul_State * state)
116 if (state->Mode > SVC26MODE)
117 return (state->Reg[15]);
122 /***************************************************************************\
123 * This routine returns the value of the PC, mode independently. *
124 \***************************************************************************/
127 ARMul_GetNextPC (ARMul_State * state)
129 if (state->Mode > SVC26MODE)
130 return (state->Reg[15] + isize);
132 return ((state->Reg[15] + isize) & R15PCBITS);
135 /***************************************************************************\
136 * This routine sets the value of the PC. *
137 \***************************************************************************/
140 ARMul_SetPC (ARMul_State * state, ARMword value)
143 state->Reg[15] = value & PCBITS;
145 state->Reg[15] = R15CCINTMODE | (value & R15PCBITS);
149 /***************************************************************************\
150 * This routine returns the value of register 15, mode independently. *
151 \***************************************************************************/
154 ARMul_GetR15 (ARMul_State * state)
156 if (state->Mode > SVC26MODE)
157 return (state->Reg[15]);
159 return (R15PC | ECC | ER15INT | EMODE);
162 /***************************************************************************\
163 * This routine sets the value of Register 15. *
164 \***************************************************************************/
167 ARMul_SetR15 (ARMul_State * state, ARMword value)
170 state->Reg[15] = value & PCBITS;
173 state->Reg[15] = value;
174 ARMul_R15Altered (state);
179 /***************************************************************************\
180 * This routine returns the value of the CPSR *
181 \***************************************************************************/
184 ARMul_GetCPSR (ARMul_State * state)
189 /***************************************************************************\
190 * This routine sets the value of the CPSR *
191 \***************************************************************************/
194 ARMul_SetCPSR (ARMul_State * state, ARMword value)
197 SETPSR (state->Cpsr, value);
198 ARMul_CPSRAltered (state);
201 /***************************************************************************\
202 * This routine does all the nasty bits involved in a write to the CPSR, *
203 * including updating the register bank, given a MSR instruction. *
204 \***************************************************************************/
207 ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs)
210 if (state->Bank == USERBANK)
211 { /* Only write flags in user mode */
214 SETCC (state->Cpsr, rhs);
218 { /* Not a user mode */
219 if (BITS (16, 19) == 9)
220 SETPSR (state->Cpsr, rhs);
222 SETINTMODE (state->Cpsr, rhs);
224 SETCC (state->Cpsr, rhs);
226 ARMul_CPSRAltered (state);
229 /***************************************************************************\
230 * Get an SPSR from the specified mode *
231 \***************************************************************************/
234 ARMul_GetSPSR (ARMul_State * state, ARMword mode)
236 ARMword bank = ModeToBank (mode & MODEBITS);
238 if (! BANK_CAN_ACCESS_SPSR (bank))
241 return state->Spsr[bank];
244 /***************************************************************************\
245 * This routine does a write to an SPSR *
246 \***************************************************************************/
249 ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value)
251 ARMword bank = ModeToBank (mode & MODEBITS);
253 if (BANK_CAN_ACCESS_SPSR (bank))
254 state->Spsr[bank] = value;
257 /***************************************************************************\
258 * This routine does a write to the current SPSR, given an MSR instruction *
259 \***************************************************************************/
262 ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs)
264 if (BANK_CAN_ACCESS_SPSR (state->Bank))
266 if (BITS (16, 19) == 9)
267 SETPSR (state->Spsr[state->Bank], rhs);
269 SETINTMODE (state->Spsr[state->Bank], rhs);
271 SETCC (state->Spsr[state->Bank], rhs);
275 /***************************************************************************\
276 * This routine updates the state of the emulator after the Cpsr has been *
277 * changed. Both the processor flags and register bank are updated. *
278 \***************************************************************************/
281 ARMul_CPSRAltered (ARMul_State * state)
285 if (state->prog32Sig == LOW)
286 state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS);
288 oldmode = state->Mode;
290 if (state->Mode != (state->Cpsr & MODEBITS))
293 ARMul_SwitchMode (state, state->Mode, state->Cpsr & MODEBITS);
295 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
298 ASSIGNINT (state->Cpsr & INTBITS);
299 ASSIGNN ((state->Cpsr & NBIT) != 0);
300 ASSIGNZ ((state->Cpsr & ZBIT) != 0);
301 ASSIGNC ((state->Cpsr & CBIT) != 0);
302 ASSIGNV ((state->Cpsr & VBIT) != 0);
304 ASSIGNT ((state->Cpsr & TBIT) != 0);
307 if (oldmode > SVC26MODE)
309 if (state->Mode <= SVC26MODE)
311 state->Emulate = CHANGEMODE;
312 state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
317 if (state->Mode > SVC26MODE)
319 state->Emulate = CHANGEMODE;
320 state->Reg[15] = R15PC;
323 state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
327 /***************************************************************************\
328 * This routine updates the state of the emulator after register 15 has *
329 * been changed. Both the processor flags and register bank are updated. *
330 * This routine should only be called from a 26 bit mode. *
331 \***************************************************************************/
334 ARMul_R15Altered (ARMul_State * state)
336 if (state->Mode != R15MODE)
338 state->Mode = ARMul_SwitchMode (state, state->Mode, R15MODE);
339 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
341 if (state->Mode > SVC26MODE)
342 state->Emulate = CHANGEMODE;
343 ASSIGNR15INT (R15INT);
344 ASSIGNN ((state->Reg[15] & NBIT) != 0);
345 ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
346 ASSIGNC ((state->Reg[15] & CBIT) != 0);
347 ASSIGNV ((state->Reg[15] & VBIT) != 0);
350 /***************************************************************************\
351 * This routine controls the saving and restoring of registers across mode *
352 * changes. The regbank matrix is largely unused, only rows 13 and 14 are *
353 * used across all modes, 8 to 14 are used for FIQ, all others use the USER *
354 * column. It's easier this way. old and new parameter are modes numbers. *
355 * Notice the side effect of changing the Bank variable. *
356 \***************************************************************************/
359 ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode)
365 oldbank = ModeToBank (oldmode);
366 newbank = state->Bank = ModeToBank (newmode);
368 if (oldbank != newbank)
369 { /* really need to do it */
371 { /* save away the old registers */
377 if (newbank == FIQBANK)
378 for (i = 8; i < 13; i++)
379 state->RegBank[USERBANK][i] = state->Reg[i];
380 state->RegBank[oldbank][13] = state->Reg[13];
381 state->RegBank[oldbank][14] = state->Reg[14];
384 for (i = 8; i < 15; i++)
385 state->RegBank[FIQBANK][i] = state->Reg[i];
388 for (i = 8; i < 15; i++)
389 state->RegBank[DUMMYBANK][i] = 0;
396 { /* restore the new registers */
402 if (oldbank == FIQBANK)
403 for (i = 8; i < 13; i++)
404 state->Reg[i] = state->RegBank[USERBANK][i];
405 state->Reg[13] = state->RegBank[newbank][13];
406 state->Reg[14] = state->RegBank[newbank][14];
409 for (i = 8; i < 15; i++)
410 state->Reg[i] = state->RegBank[FIQBANK][i];
413 for (i = 8; i < 15; i++)
424 /***************************************************************************\
425 * Given a processor mode, this routine returns the register bank that *
426 * will be accessed in that mode. *
427 \***************************************************************************/
430 ModeToBank (ARMword mode)
432 static ARMword bankofmode[] =
434 USERBANK, FIQBANK, IRQBANK, SVCBANK,
435 DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
436 DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
437 DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
438 USERBANK, FIQBANK, IRQBANK, SVCBANK,
439 DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK,
440 DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK,
441 DUMMYBANK, DUMMYBANK, DUMMYBANK, SYSTEMBANK
444 if (mode >= (sizeof (bankofmode) / sizeof (bankofmode[0])))
447 return bankofmode[mode];
450 /***************************************************************************\
451 * Returns the register number of the nth register in a reg list. *
452 \***************************************************************************/
455 ARMul_NthReg (ARMword instr, unsigned number)
459 for (bit = 0, upto = 0; upto <= number; bit++)
465 /***************************************************************************\
466 * Assigns the N and Z flags depending on the value of result *
467 \***************************************************************************/
470 ARMul_NegZero (ARMul_State * state, ARMword result)
477 else if (result == 0)
489 /* Compute whether an addition of A and B, giving RESULT, overflowed. */
491 AddOverflow (ARMword a, ARMword b, ARMword result)
493 return ((NEG (a) && NEG (b) && POS (result))
494 || (POS (a) && POS (b) && NEG (result)));
497 /* Compute whether a subtraction of A and B, giving RESULT, overflowed. */
499 SubOverflow (ARMword a, ARMword b, ARMword result)
501 return ((NEG (a) && POS (b) && POS (result))
502 || (POS (a) && NEG (b) && NEG (result)));
505 /***************************************************************************\
506 * Assigns the C flag after an addition of a and b to give result *
507 \***************************************************************************/
510 ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
512 ASSIGNC ((NEG (a) && NEG (b)) ||
513 (NEG (a) && POS (result)) || (NEG (b) && POS (result)));
516 /***************************************************************************\
517 * Assigns the V flag after an addition of a and b to give result *
518 \***************************************************************************/
521 ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
523 ASSIGNV (AddOverflow (a, b, result));
526 /***************************************************************************\
527 * Assigns the C flag after an subtraction of a and b to give result *
528 \***************************************************************************/
531 ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
533 ASSIGNC ((NEG (a) && POS (b)) ||
534 (NEG (a) && POS (result)) || (POS (b) && POS (result)));
537 /***************************************************************************\
538 * Assigns the V flag after an subtraction of a and b to give result *
539 \***************************************************************************/
542 ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
544 ASSIGNV (SubOverflow (a, b, result));
547 /***************************************************************************\
548 * This function does the work of generating the addresses used in an *
549 * LDC instruction. The code here is always post-indexed, it's up to the *
550 * caller to get the input address correct and to handle base register *
551 * modification. It also handles the Busy-Waiting. *
552 \***************************************************************************/
555 ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address)
561 if (ADDREXCEPT (address))
563 INTERNALABORT (address);
565 cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0);
566 while (cpab == ARMul_BUSY)
568 ARMul_Icycles (state, 1, 0);
569 if (IntPending (state))
571 cpab = (state->LDC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
575 cpab = (state->LDC[CPNum]) (state, ARMul_BUSY, instr, 0);
577 if (cpab == ARMul_CANT)
582 cpab = (state->LDC[CPNum]) (state, ARMul_TRANSFER, instr, 0);
583 data = ARMul_LoadWordN (state, address);
586 LSBase = state->Base;
587 cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
588 while (cpab == ARMul_INC)
591 data = ARMul_LoadWordN (state, address);
592 cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
594 if (state->abortSig || state->Aborted)
600 /***************************************************************************\
601 * This function does the work of generating the addresses used in an *
602 * STC instruction. The code here is always post-indexed, it's up to the *
603 * caller to get the input address correct and to handle base register *
604 * modification. It also handles the Busy-Waiting. *
605 \***************************************************************************/
608 ARMul_STC (ARMul_State * state, ARMword instr, ARMword address)
614 if (ADDREXCEPT (address) || VECTORACCESS (address))
616 INTERNALABORT (address);
618 cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data);
619 while (cpab == ARMul_BUSY)
621 ARMul_Icycles (state, 1, 0);
622 if (IntPending (state))
624 cpab = (state->STC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
628 cpab = (state->STC[CPNum]) (state, ARMul_BUSY, instr, &data);
630 if (cpab == ARMul_CANT)
636 if (ADDREXCEPT (address) || VECTORACCESS (address))
638 INTERNALABORT (address);
643 LSBase = state->Base;
644 cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
645 ARMul_StoreWordN (state, address, data);
646 while (cpab == ARMul_INC)
649 cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
650 ARMul_StoreWordN (state, address, data);
652 if (state->abortSig || state->Aborted)
658 /***************************************************************************\
659 * This function does the Busy-Waiting for an MCR instruction. *
660 \***************************************************************************/
663 ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source)
667 cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source);
669 while (cpab == ARMul_BUSY)
671 ARMul_Icycles (state, 1, 0);
673 if (IntPending (state))
675 cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
679 cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, source);
682 if (cpab == ARMul_CANT)
683 ARMul_Abort (state, ARMul_UndefinedInstrV);
687 ARMul_Ccycles (state, 1, 0);
691 /***************************************************************************\
692 * This function does the Busy-Waiting for an MRC instruction. *
693 \***************************************************************************/
696 ARMul_MRC (ARMul_State * state, ARMword instr)
701 cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result);
702 while (cpab == ARMul_BUSY)
704 ARMul_Icycles (state, 1, 0);
705 if (IntPending (state))
707 cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
711 cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr, &result);
713 if (cpab == ARMul_CANT)
715 ARMul_Abort (state, ARMul_UndefinedInstrV);
716 result = ECC; /* Parent will destroy the flags otherwise */
721 ARMul_Ccycles (state, 1, 0);
722 ARMul_Icycles (state, 1, 0);
727 /***************************************************************************\
728 * This function does the Busy-Waiting for an CDP instruction. *
729 \***************************************************************************/
732 ARMul_CDP (ARMul_State * state, ARMword instr)
736 cpab = (state->CDP[CPNum]) (state, ARMul_FIRST, instr);
737 while (cpab == ARMul_BUSY)
739 ARMul_Icycles (state, 1, 0);
740 if (IntPending (state))
742 cpab = (state->CDP[CPNum]) (state, ARMul_INTERRUPT, instr);
746 cpab = (state->CDP[CPNum]) (state, ARMul_BUSY, instr);
748 if (cpab == ARMul_CANT)
749 ARMul_Abort (state, ARMul_UndefinedInstrV);
754 /***************************************************************************\
755 * This function handles Undefined instructions, as CP isntruction *
756 \***************************************************************************/
759 ARMul_UndefInstr (ARMul_State * state, ARMword instr ATTRIBUTE_UNUSED)
761 ARMul_Abort (state, ARMul_UndefinedInstrV);
764 /***************************************************************************\
765 * Return TRUE if an interrupt is pending, FALSE otherwise. *
766 \***************************************************************************/
769 IntPending (ARMul_State * state)
771 if (state->Exception)
772 { /* Any exceptions */
773 if (state->NresetSig == LOW)
775 ARMul_Abort (state, ARMul_ResetV);
778 else if (!state->NfiqSig && !FFLAG)
780 ARMul_Abort (state, ARMul_FIQV);
783 else if (!state->NirqSig && !IFLAG)
785 ARMul_Abort (state, ARMul_IRQV);
792 /***************************************************************************\
793 * Align a word access to a non word boundary *
794 \***************************************************************************/
797 ARMul_Align (state, address, data)
798 ARMul_State * state ATTRIBUTE_UNUSED;
802 /* This code assumes the address is really unaligned,
803 as a shift by 32 is undefined in C. */
805 address = (address & 3) << 3; /* get the word address */
806 return ((data >> address) | (data << (32 - address))); /* rot right */
809 /***************************************************************************\
810 * This routine is used to call another routine after a certain number of *
811 * cycles have been executed. The first parameter is the number of cycles *
812 * delay before the function is called, the second argument is a pointer *
813 * to the function. A delay of zero doesn't work, just call the function. *
814 \***************************************************************************/
817 ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
821 struct EventNode *event;
823 if (state->EventSet++ == 0)
824 state->Now = ARMul_Time (state);
825 when = (state->Now + delay) % EVENTLISTSIZE;
826 event = (struct EventNode *) malloc (sizeof (struct EventNode));
828 event->next = *(state->EventPtr + when);
829 *(state->EventPtr + when) = event;
832 /***************************************************************************\
833 * This routine is called at the beginning of every cycle, to envoke *
834 * scheduled events. *
835 \***************************************************************************/
838 ARMul_EnvokeEvent (ARMul_State * state)
840 static unsigned long then;
843 state->Now = ARMul_Time (state) % EVENTLISTSIZE;
844 if (then < state->Now) /* schedule events */
845 EnvokeList (state, then, state->Now);
846 else if (then > state->Now)
847 { /* need to wrap around the list */
848 EnvokeList (state, then, EVENTLISTSIZE - 1L);
849 EnvokeList (state, 0L, state->Now);
854 EnvokeList (ARMul_State * state, unsigned long from, unsigned long to)
855 /* envokes all the entries in a range */
857 struct EventNode *anevent;
859 for (; from <= to; from++)
861 anevent = *(state->EventPtr + from);
864 (anevent->func) (state);
866 anevent = anevent->next;
868 *(state->EventPtr + from) = NULL;
872 /***************************************************************************\
873 * This routine is returns the number of clock ticks since the last reset. *
874 \***************************************************************************/
877 ARMul_Time (ARMul_State * state)
879 return (state->NumScycles + state->NumNcycles +
880 state->NumIcycles + state->NumCcycles + state->NumFcycles);