1 /* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 /* Definitions for the support routines. */
24 static ARMword ModeToBank (ARMword);
25 static void EnvokeList (ARMul_State *, unsigned long, unsigned long);
28 { /* An event list node. */
29 unsigned (*func) (ARMul_State *); /* The function to call. */
30 struct EventNode *next;
33 /* This routine returns the value of a register from a mode. */
36 ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg)
39 if (mode != state->Mode)
40 return (state->RegBank[ModeToBank ((ARMword) mode)][reg]);
42 return (state->Reg[reg]);
45 /* This routine sets the value of a register for a mode. */
48 ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value)
51 if (mode != state->Mode)
52 state->RegBank[ModeToBank ((ARMword) mode)][reg] = value;
54 state->Reg[reg] = value;
57 /* This routine returns the value of the PC, mode independently. */
60 ARMul_GetPC (ARMul_State * state)
62 if (state->Mode > SVC26MODE)
63 return state->Reg[15];
68 /* This routine returns the value of the PC, mode independently. */
71 ARMul_GetNextPC (ARMul_State * state)
73 if (state->Mode > SVC26MODE)
74 return state->Reg[15] + isize;
76 return (state->Reg[15] + isize) & R15PCBITS;
79 /* This routine sets the value of the PC. */
82 ARMul_SetPC (ARMul_State * state, ARMword value)
85 state->Reg[15] = value & PCBITS;
87 state->Reg[15] = R15CCINTMODE | (value & R15PCBITS);
91 /* This routine returns the value of register 15, mode independently. */
94 ARMul_GetR15 (ARMul_State * state)
96 if (state->Mode > SVC26MODE)
97 return (state->Reg[15]);
99 return (R15PC | ECC | ER15INT | EMODE);
102 /* This routine sets the value of Register 15. */
105 ARMul_SetR15 (ARMul_State * state, ARMword value)
108 state->Reg[15] = value & PCBITS;
111 state->Reg[15] = value;
112 ARMul_R15Altered (state);
117 /* This routine returns the value of the CPSR. */
120 ARMul_GetCPSR (ARMul_State * state)
122 return (CPSR | state->Cpsr);
125 /* This routine sets the value of the CPSR. */
128 ARMul_SetCPSR (ARMul_State * state, ARMword value)
131 ARMul_CPSRAltered (state);
134 /* This routine does all the nasty bits involved in a write to the CPSR,
135 including updating the register bank, given a MSR instruction. */
138 ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs)
140 state->Cpsr = ARMul_GetCPSR (state);
141 if (state->Mode != USER26MODE
142 && state->Mode != USER32MODE)
144 /* In user mode, only write flags. */
146 SETPSR_C (state->Cpsr, rhs);
148 SETPSR_X (state->Cpsr, rhs);
150 SETPSR_S (state->Cpsr, rhs);
153 SETPSR_F (state->Cpsr, rhs);
154 ARMul_CPSRAltered (state);
157 /* Get an SPSR from the specified mode. */
160 ARMul_GetSPSR (ARMul_State * state, ARMword mode)
162 ARMword bank = ModeToBank (mode & MODEBITS);
164 if (! BANK_CAN_ACCESS_SPSR (bank))
165 return ARMul_GetCPSR (state);
167 return state->Spsr[bank];
170 /* This routine does a write to an SPSR. */
173 ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value)
175 ARMword bank = ModeToBank (mode & MODEBITS);
177 if (BANK_CAN_ACCESS_SPSR (bank))
178 state->Spsr[bank] = value;
181 /* This routine does a write to the current SPSR, given an MSR instruction. */
184 ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs)
186 if (BANK_CAN_ACCESS_SPSR (state->Bank))
189 SETPSR_C (state->Spsr[state->Bank], rhs);
191 SETPSR_X (state->Spsr[state->Bank], rhs);
193 SETPSR_S (state->Spsr[state->Bank], rhs);
195 SETPSR_F (state->Spsr[state->Bank], rhs);
199 /* This routine updates the state of the emulator after the Cpsr has been
200 changed. Both the processor flags and register bank are updated. */
203 ARMul_CPSRAltered (ARMul_State * state)
207 if (state->prog32Sig == LOW)
208 state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS);
210 oldmode = state->Mode;
212 if (state->Mode != (state->Cpsr & MODEBITS))
215 ARMul_SwitchMode (state, state->Mode, state->Cpsr & MODEBITS);
217 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
219 state->Cpsr &= ~MODEBITS;
221 ASSIGNINT (state->Cpsr & INTBITS);
222 state->Cpsr &= ~INTBITS;
223 ASSIGNN ((state->Cpsr & NBIT) != 0);
224 state->Cpsr &= ~NBIT;
225 ASSIGNZ ((state->Cpsr & ZBIT) != 0);
226 state->Cpsr &= ~ZBIT;
227 ASSIGNC ((state->Cpsr & CBIT) != 0);
228 state->Cpsr &= ~CBIT;
229 ASSIGNV ((state->Cpsr & VBIT) != 0);
230 state->Cpsr &= ~VBIT;
231 ASSIGNS ((state->Cpsr & SBIT) != 0);
232 state->Cpsr &= ~SBIT;
234 ASSIGNT ((state->Cpsr & TBIT) != 0);
235 state->Cpsr &= ~TBIT;
238 if (oldmode > SVC26MODE)
240 if (state->Mode <= SVC26MODE)
242 state->Emulate = CHANGEMODE;
243 state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
248 if (state->Mode > SVC26MODE)
250 state->Emulate = CHANGEMODE;
251 state->Reg[15] = R15PC;
254 state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
258 /* This routine updates the state of the emulator after register 15 has
259 been changed. Both the processor flags and register bank are updated.
260 This routine should only be called from a 26 bit mode. */
263 ARMul_R15Altered (ARMul_State * state)
265 if (state->Mode != R15MODE)
267 state->Mode = ARMul_SwitchMode (state, state->Mode, R15MODE);
268 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
271 if (state->Mode > SVC26MODE)
272 state->Emulate = CHANGEMODE;
274 ASSIGNR15INT (R15INT);
276 ASSIGNN ((state->Reg[15] & NBIT) != 0);
277 ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
278 ASSIGNC ((state->Reg[15] & CBIT) != 0);
279 ASSIGNV ((state->Reg[15] & VBIT) != 0);
282 /* This routine controls the saving and restoring of registers across mode
283 changes. The regbank matrix is largely unused, only rows 13 and 14 are
284 used across all modes, 8 to 14 are used for FIQ, all others use the USER
285 column. It's easier this way. old and new parameter are modes numbers.
286 Notice the side effect of changing the Bank variable. */
289 ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode)
295 oldbank = ModeToBank (oldmode);
296 newbank = state->Bank = ModeToBank (newmode);
298 /* Do we really need to do it? */
299 if (oldbank != newbank)
301 /* Save away the old registers. */
309 if (newbank == FIQBANK)
310 for (i = 8; i < 13; i++)
311 state->RegBank[USERBANK][i] = state->Reg[i];
312 state->RegBank[oldbank][13] = state->Reg[13];
313 state->RegBank[oldbank][14] = state->Reg[14];
316 for (i = 8; i < 15; i++)
317 state->RegBank[FIQBANK][i] = state->Reg[i];
320 for (i = 8; i < 15; i++)
321 state->RegBank[DUMMYBANK][i] = 0;
327 /* Restore the new registers. */
335 if (oldbank == FIQBANK)
336 for (i = 8; i < 13; i++)
337 state->Reg[i] = state->RegBank[USERBANK][i];
338 state->Reg[13] = state->RegBank[newbank][13];
339 state->Reg[14] = state->RegBank[newbank][14];
342 for (i = 8; i < 15; i++)
343 state->Reg[i] = state->RegBank[FIQBANK][i];
346 for (i = 8; i < 15; i++)
357 /* Given a processor mode, this routine returns the
358 register bank that will be accessed in that mode. */
361 ModeToBank (ARMword mode)
363 static ARMword bankofmode[] =
365 USERBANK, FIQBANK, IRQBANK, SVCBANK,
366 DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
367 DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
368 DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
369 USERBANK, FIQBANK, IRQBANK, SVCBANK,
370 DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK,
371 DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK,
372 DUMMYBANK, DUMMYBANK, DUMMYBANK, SYSTEMBANK
375 if (mode >= (sizeof (bankofmode) / sizeof (bankofmode[0])))
378 return bankofmode[mode];
381 /* Returns the register number of the nth register in a reg list. */
384 ARMul_NthReg (ARMword instr, unsigned number)
388 for (bit = 0, upto = 0; upto <= number; bit ++)
395 /* Assigns the N and Z flags depending on the value of result. */
398 ARMul_NegZero (ARMul_State * state, ARMword result)
405 else if (result == 0)
417 /* Compute whether an addition of A and B, giving RESULT, overflowed. */
420 AddOverflow (ARMword a, ARMword b, ARMword result)
422 return ((NEG (a) && NEG (b) && POS (result))
423 || (POS (a) && POS (b) && NEG (result)));
426 /* Compute whether a subtraction of A and B, giving RESULT, overflowed. */
429 SubOverflow (ARMword a, ARMword b, ARMword result)
431 return ((NEG (a) && POS (b) && POS (result))
432 || (POS (a) && NEG (b) && NEG (result)));
435 /* Assigns the C flag after an addition of a and b to give result. */
438 ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
440 ASSIGNC ((NEG (a) && NEG (b)) ||
441 (NEG (a) && POS (result)) || (NEG (b) && POS (result)));
444 /* Assigns the V flag after an addition of a and b to give result. */
447 ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
449 ASSIGNV (AddOverflow (a, b, result));
452 /* Assigns the C flag after an subtraction of a and b to give result. */
455 ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
457 ASSIGNC ((NEG (a) && POS (b)) ||
458 (NEG (a) && POS (result)) || (POS (b) && POS (result)));
461 /* Assigns the V flag after an subtraction of a and b to give result. */
464 ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
466 ASSIGNV (SubOverflow (a, b, result));
469 /* This function does the work of generating the addresses used in an
470 LDC instruction. The code here is always post-indexed, it's up to the
471 caller to get the input address correct and to handle base register
472 modification. It also handles the Busy-Waiting. */
475 ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address)
482 if (! CP_ACCESS_ALLOWED (state, CPNum))
484 ARMul_UndefInstr (state, instr);
488 if (ADDREXCEPT (address))
489 INTERNALABORT (address);
491 cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0);
492 while (cpab == ARMul_BUSY)
494 ARMul_Icycles (state, 1, 0);
496 if (IntPending (state))
498 cpab = (state->LDC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
502 cpab = (state->LDC[CPNum]) (state, ARMul_BUSY, instr, 0);
504 if (cpab == ARMul_CANT)
510 cpab = (state->LDC[CPNum]) (state, ARMul_TRANSFER, instr, 0);
511 data = ARMul_LoadWordN (state, address);
515 LSBase = state->Base;
516 cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
518 while (cpab == ARMul_INC)
521 data = ARMul_LoadWordN (state, address);
522 cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
525 if (state->abortSig || state->Aborted)
529 /* This function does the work of generating the addresses used in an
530 STC instruction. The code here is always post-indexed, it's up to the
531 caller to get the input address correct and to handle base register
532 modification. It also handles the Busy-Waiting. */
535 ARMul_STC (ARMul_State * state, ARMword instr, ARMword address)
542 if (! CP_ACCESS_ALLOWED (state, CPNum))
544 ARMul_UndefInstr (state, instr);
548 if (ADDREXCEPT (address) || VECTORACCESS (address))
549 INTERNALABORT (address);
551 cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data);
552 while (cpab == ARMul_BUSY)
554 ARMul_Icycles (state, 1, 0);
555 if (IntPending (state))
557 cpab = (state->STC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
561 cpab = (state->STC[CPNum]) (state, ARMul_BUSY, instr, &data);
564 if (cpab == ARMul_CANT)
570 if (ADDREXCEPT (address) || VECTORACCESS (address))
571 INTERNALABORT (address);
576 LSBase = state->Base;
577 cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
578 ARMul_StoreWordN (state, address, data);
580 while (cpab == ARMul_INC)
583 cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
584 ARMul_StoreWordN (state, address, data);
587 if (state->abortSig || state->Aborted)
591 /* This function does the Busy-Waiting for an MCR instruction. */
594 ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source)
598 if (! CP_ACCESS_ALLOWED (state, CPNum))
600 ARMul_UndefInstr (state, instr);
604 cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source);
606 while (cpab == ARMul_BUSY)
608 ARMul_Icycles (state, 1, 0);
610 if (IntPending (state))
612 cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
616 cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, source);
619 if (cpab == ARMul_CANT)
620 ARMul_Abort (state, ARMul_UndefinedInstrV);
624 ARMul_Ccycles (state, 1, 0);
628 /* This function does the Busy-Waiting for an MRC instruction. */
631 ARMul_MRC (ARMul_State * state, ARMword instr)
636 if (! CP_ACCESS_ALLOWED (state, CPNum))
638 ARMul_UndefInstr (state, instr);
642 cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result);
643 while (cpab == ARMul_BUSY)
645 ARMul_Icycles (state, 1, 0);
646 if (IntPending (state))
648 cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT, instr, 0);
652 cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr, &result);
654 if (cpab == ARMul_CANT)
656 ARMul_Abort (state, ARMul_UndefinedInstrV);
657 /* Parent will destroy the flags otherwise. */
663 ARMul_Ccycles (state, 1, 0);
664 ARMul_Icycles (state, 1, 0);
670 /* This function does the Busy-Waiting for an CDP instruction. */
673 ARMul_CDP (ARMul_State * state, ARMword instr)
677 if (! CP_ACCESS_ALLOWED (state, CPNum))
679 ARMul_UndefInstr (state, instr);
683 cpab = (state->CDP[CPNum]) (state, ARMul_FIRST, instr);
684 while (cpab == ARMul_BUSY)
686 ARMul_Icycles (state, 1, 0);
687 if (IntPending (state))
689 cpab = (state->CDP[CPNum]) (state, ARMul_INTERRUPT, instr);
693 cpab = (state->CDP[CPNum]) (state, ARMul_BUSY, instr);
695 if (cpab == ARMul_CANT)
696 ARMul_Abort (state, ARMul_UndefinedInstrV);
701 /* This function handles Undefined instructions, as CP isntruction. */
704 ARMul_UndefInstr (ARMul_State * state, ARMword instr ATTRIBUTE_UNUSED)
706 ARMul_Abort (state, ARMul_UndefinedInstrV);
709 /* Return TRUE if an interrupt is pending, FALSE otherwise. */
712 IntPending (ARMul_State * state)
714 if (state->Exception)
716 /* Any exceptions. */
717 if (state->NresetSig == LOW)
719 ARMul_Abort (state, ARMul_ResetV);
722 else if (!state->NfiqSig && !FFLAG)
724 ARMul_Abort (state, ARMul_FIQV);
727 else if (!state->NirqSig && !IFLAG)
729 ARMul_Abort (state, ARMul_IRQV);
737 /* Align a word access to a non word boundary. */
740 ARMul_Align (state, address, data)
741 ARMul_State * state ATTRIBUTE_UNUSED;
745 /* This code assumes the address is really unaligned,
746 as a shift by 32 is undefined in C. */
748 address = (address & 3) << 3; /* Get the word address. */
749 return ((data >> address) | (data << (32 - address))); /* rot right */
752 /* This routine is used to call another routine after a certain number of
753 cycles have been executed. The first parameter is the number of cycles
754 delay before the function is called, the second argument is a pointer
755 to the function. A delay of zero doesn't work, just call the function. */
758 ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
759 unsigned (*what) (ARMul_State *))
762 struct EventNode *event;
764 if (state->EventSet++ == 0)
765 state->Now = ARMul_Time (state);
766 when = (state->Now + delay) % EVENTLISTSIZE;
767 event = (struct EventNode *) malloc (sizeof (struct EventNode));
769 event->next = *(state->EventPtr + when);
770 *(state->EventPtr + when) = event;
773 /* This routine is called at the beginning of
774 every cycle, to envoke scheduled events. */
777 ARMul_EnvokeEvent (ARMul_State * state)
779 static unsigned long then;
782 state->Now = ARMul_Time (state) % EVENTLISTSIZE;
783 if (then < state->Now)
784 /* Schedule events. */
785 EnvokeList (state, then, state->Now);
786 else if (then > state->Now)
788 /* Need to wrap around the list. */
789 EnvokeList (state, then, EVENTLISTSIZE - 1L);
790 EnvokeList (state, 0L, state->Now);
794 /* Envokes all the entries in a range. */
797 EnvokeList (ARMul_State * state, unsigned long from, unsigned long to)
799 for (; from <= to; from++)
801 struct EventNode *anevent;
803 anevent = *(state->EventPtr + from);
806 (anevent->func) (state);
808 anevent = anevent->next;
810 *(state->EventPtr + from) = NULL;
814 /* This routine is returns the number of clock ticks since the last reset. */
817 ARMul_Time (ARMul_State * state)
819 return (state->NumScycles + state->NumNcycles +
820 state->NumIcycles + state->NumCcycles + state->NumFcycles);