1 /* armos.c -- ARMulator OS interface: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 3 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, see <http://www.gnu.org/licenses/>. */
17 /* This file contains a model of Demon, ARM Ltd's Debug Monitor,
18 including all the SWI's required to support the C library. The code in
19 it is not really for the faint-hearted (especially the abort handling
20 code), but it is a complete example. Defining NOOS will disable all the
21 fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI
22 0x11 to halt the emulator. */
31 #include "targ-vals.h"
33 #ifndef TARGET_O_BINARY
34 #define TARGET_O_BINARY 0
38 #include <unistd.h> /* For SEEK_SET etc. */
53 /* For RDIError_BreakpointReached. */
56 #include "gdb/callback.h"
57 extern host_callback *sim_callback;
59 extern unsigned ARMul_OSInit (ARMul_State *);
60 extern unsigned ARMul_OSHandleSWI (ARMul_State *, ARMword);
69 /* OS private Information. */
76 /* Bit mask of enabled SWI implementations. */
77 unsigned int swi_mask = -1;
80 static ARMword softvectorcode[] =
82 /* Installed instructions:
83 swi tidyexception + event;
86 swi generateexception + event. */
87 0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /* Reset */
88 0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /* Undef */
89 0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /* SWI */
90 0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /* Prefetch abort */
91 0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /* Data abort */
92 0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /* Address exception */
93 0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /* IRQ */
94 0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /* FIQ */
95 0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /* Error */
96 0xe1a0f00e /* Default handler */
99 /* Time for the Operating System to initialise itself. */
102 ARMul_OSInit (ARMul_State * state)
107 struct OSblock *OSptr = (struct OSblock *) state->OSptr;
109 if (state->OSptr == NULL)
111 state->OSptr = (unsigned char *) malloc (sizeof (struct OSblock));
112 if (state->OSptr == NULL)
114 perror ("OS Memory");
119 OSptr = (struct OSblock *) state->OSptr;
120 state->Reg[13] = ADDRSUPERSTACK; /* Set up a stack for the current mode... */
121 ARMul_SetReg (state, SVC32MODE, 13, ADDRSUPERSTACK);/* ...and for supervisor mode... */
122 ARMul_SetReg (state, ABORT32MODE, 13, ADDRSUPERSTACK);/* ...and for abort 32 mode... */
123 ARMul_SetReg (state, UNDEF32MODE, 13, ADDRSUPERSTACK);/* ...and for undef 32 mode... */
124 ARMul_SetReg (state, SYSTEMMODE, 13, ADDRSUPERSTACK);/* ...and for system mode. */
125 instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* Load pc from soft vector */
127 for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
128 /* Write hardware vectors. */
129 ARMul_WriteWord (state, i, instr);
131 SWI_vector_installed = 0;
133 for (i = ARMul_ResetV; i <= ARMFIQV + 4; i += 4)
135 ARMul_WriteWord (state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4);
136 ARMul_WriteWord (state, ADDRSOFHANDLERS + 2 * i + 4L,
137 SOFTVECTORCODE + sizeof (softvectorcode) - 4L);
140 for (i = 0; i < sizeof (softvectorcode); i += 4)
141 ARMul_WriteWord (state, SOFTVECTORCODE + i, softvectorcode[i / 4]);
143 ARMul_ConsolePrint (state, ", Demon 1.01");
148 for (i = 0; i < fpesize; i += 4)
150 ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]);
152 /* Scan backwards from the end of the code. */
153 for (i = FPESTART + fpesize;; i -= 4)
155 /* When we reach the marker value, break out of
156 the loop, leaving i pointing at the maker. */
157 if ((j = ARMul_ReadWord (state, i)) == 0xffffffff)
160 /* If necessary, reverse the error strings. */
161 if (state->bigendSig && j < 0x80000000)
163 /* It's part of the string so swap it. */
164 j = ((j >> 0x18) & 0x000000ff) |
165 ((j >> 0x08) & 0x0000ff00) |
166 ((j << 0x08) & 0x00ff0000) | ((j << 0x18) & 0xff000000);
167 ARMul_WriteWord (state, i, j);
171 /* Copy old illegal instr vector. */
172 ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, ARMUndefinedInstrV));
173 /* Install new vector. */
174 ARMul_WriteWord (state, ARMUndefinedInstrV, FPENEWVECT (ARMul_ReadWord (state, i - 4)));
175 ARMul_ConsolePrint (state, ", FPE");
178 #endif /* VALIDATE */
181 /* Intel do not want DEMON SWI support. */
182 if (state->is_XScale)
183 swi_mask = SWI_MASK_ANGEL;
188 static int translate_open_mode[] =
190 TARGET_O_RDONLY, /* "r" */
191 TARGET_O_RDONLY + TARGET_O_BINARY, /* "rb" */
192 TARGET_O_RDWR, /* "r+" */
193 TARGET_O_RDWR + TARGET_O_BINARY, /* "r+b" */
194 TARGET_O_WRONLY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w" */
195 TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "wb" */
196 TARGET_O_RDWR + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+" */
197 TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+b" */
198 TARGET_O_WRONLY + TARGET_O_APPEND + TARGET_O_CREAT, /* "a" */
199 TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT, /* "ab" */
200 TARGET_O_RDWR + TARGET_O_APPEND + TARGET_O_CREAT, /* "a+" */
201 TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT /* "a+b" */
205 SWIWrite0 (ARMul_State * state, ARMword addr)
208 struct OSblock *OSptr = (struct OSblock *) state->OSptr;
210 while ((temp = ARMul_SafeReadByte (state, addr++)) != 0)
213 /* Note - we cannot just cast 'temp' to a (char *) here,
214 since on a big-endian host the byte value will end
215 up in the wrong place and a nul character will be printed. */
216 (void) sim_callback->write_stdout (sim_callback, & buffer, 1);
219 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
223 WriteCommandLineTo (ARMul_State * state, ARMword addr)
226 char *cptr = state->CommandLine;
232 temp = (ARMword) * cptr++;
233 ARMul_SafeWriteByte (state, addr++, temp);
239 ReadFileName (ARMul_State * state, char *buf, ARMword src, size_t n)
241 struct OSblock *OSptr = (struct OSblock *) state->OSptr;
245 if ((*p++ = ARMul_SafeReadByte (state, src++)) == '\0')
247 OSptr->ErrorNo = cb_host_to_target_errno (sim_callback, ENAMETOOLONG);
253 SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags)
255 struct OSblock *OSptr = (struct OSblock *) state->OSptr;
259 if (ReadFileName (state, buf, name, sizeof buf) == -1)
262 /* Now we need to decode the Demon open mode. */
263 flags = translate_open_mode[SWIflags];
265 /* Filename ":tt" is special: it denotes stdin/out. */
266 if (strcmp (buf, ":tt") == 0)
268 if (flags == TARGET_O_RDONLY) /* opening tty "r" */
269 state->Reg[0] = 0; /* stdin */
271 state->Reg[0] = 1; /* stdout */
275 state->Reg[0] = sim_callback->open (sim_callback, buf, flags);
276 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
281 SWIread (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
283 struct OSblock *OSptr = (struct OSblock *) state->OSptr;
286 char *local = malloc (len);
290 sim_callback->printf_filtered
292 "sim: Unable to read 0x%ulx bytes - out of memory\n",
297 res = sim_callback->read (sim_callback, f, local, len);
299 for (i = 0; i < res; i++)
300 ARMul_SafeWriteByte (state, ptr + i, local[i]);
303 state->Reg[0] = res == -1 ? -1 : len - res;
304 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
308 SWIwrite (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
310 struct OSblock *OSptr = (struct OSblock *) state->OSptr;
313 char *local = malloc (len);
317 sim_callback->printf_filtered
319 "sim: Unable to write 0x%lx bytes - out of memory\n",
324 for (i = 0; i < len; i++)
325 local[i] = ARMul_SafeReadByte (state, ptr + i);
327 res = sim_callback->write (sim_callback, f, local, len);
328 state->Reg[0] = res == -1 ? -1 : len - res;
331 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
335 SWIflen (ARMul_State * state, ARMword fh)
337 struct OSblock *OSptr = (struct OSblock *) state->OSptr;
342 OSptr->ErrorNo = EBADF;
347 addr = sim_callback->lseek (sim_callback, fh, 0, SEEK_CUR);
349 state->Reg[0] = sim_callback->lseek (sim_callback, fh, 0L, SEEK_END);
350 (void) sim_callback->lseek (sim_callback, fh, addr, SEEK_SET);
352 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
356 SWIremove (ARMul_State * state, ARMword path)
360 if (ReadFileName (state, buf, path, sizeof buf) != -1)
362 struct OSblock *OSptr = (struct OSblock *) state->OSptr;
363 state->Reg[0] = sim_callback->unlink (sim_callback, buf);
364 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
369 SWIrename (ARMul_State * state, ARMword old, ARMword new)
371 char oldbuf[PATH_MAX], newbuf[PATH_MAX];
373 if (ReadFileName (state, oldbuf, old, sizeof oldbuf) != -1
374 && ReadFileName (state, newbuf, new, sizeof newbuf) != -1)
376 struct OSblock *OSptr = (struct OSblock *) state->OSptr;
377 state->Reg[0] = sim_callback->rename (sim_callback, oldbuf, newbuf);
378 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
382 /* The emulator calls this routine when a SWI instruction is encuntered.
383 The parameter passed is the SWI number (lower 24 bits of the instruction). */
386 ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
388 struct OSblock * OSptr = (struct OSblock *) state->OSptr;
389 int unhandled = FALSE;
394 if (swi_mask & SWI_MASK_DEMON)
395 SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]);
401 if (swi_mask & SWI_MASK_DEMON)
402 SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]);
408 if (swi_mask & SWI_MASK_DEMON)
409 SWIopen (state, state->Reg[0], state->Reg[1]);
415 if (swi_mask & SWI_MASK_DEMON)
417 /* Return number of centi-seconds. */
419 #ifdef CLOCKS_PER_SEC
420 (CLOCKS_PER_SEC >= 100)
421 ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
422 : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
424 /* Presume unix... clock() returns microseconds. */
425 (ARMword) (clock () / 10000);
427 OSptr->ErrorNo = errno;
434 if (swi_mask & SWI_MASK_DEMON)
436 state->Reg[0] = (ARMword) sim_callback->time (sim_callback, NULL);
437 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
444 if (swi_mask & SWI_MASK_DEMON)
446 state->Reg[0] = sim_callback->close (sim_callback, state->Reg[0]);
447 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
454 if (swi_mask & SWI_MASK_DEMON)
455 SWIflen (state, state->Reg[0]);
461 if (swi_mask & SWI_MASK_DEMON)
462 state->Emulate = FALSE;
468 if (swi_mask & SWI_MASK_DEMON)
470 /* We must return non-zero for failure. */
471 state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, state->Reg[0], state->Reg[1], SEEK_SET);
472 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
479 if (swi_mask & SWI_MASK_DEMON)
481 char tmp = state->Reg[0];
482 (void) sim_callback->write_stdout (sim_callback, &tmp, 1);
483 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
490 if (swi_mask & SWI_MASK_DEMON)
491 SWIWrite0 (state, state->Reg[0]);
497 if (swi_mask & SWI_MASK_DEMON)
498 state->Reg[0] = OSptr->ErrorNo;
504 if (swi_mask & SWI_MASK_DEMON)
506 state->Reg[0] = ADDRCMDLINE;
508 state->Reg[1] = state->MemSize;
510 state->Reg[1] = ADDRUSERSTACK;
512 WriteCommandLineTo (state, state->Reg[0]);
519 state->EndCondition = RDIError_BreakpointReached;
520 state->Emulate = FALSE;
524 if (swi_mask & SWI_MASK_DEMON)
525 SWIremove (state, state->Reg[0]);
531 if (swi_mask & SWI_MASK_DEMON)
532 SWIrename (state, state->Reg[0], state->Reg[1]);
538 if (swi_mask & SWI_MASK_DEMON)
540 state->Reg[0] = sim_callback->isatty (sim_callback, state->Reg[0]);
541 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
547 /* Handle Angel SWIs as well as Demon ones. */
550 if (swi_mask & SWI_MASK_ANGEL)
555 /* R1 is almost always a parameter block. */
556 addr = state->Reg[1];
557 /* R0 is a reason code. */
558 switch (state->Reg[0])
561 /* This can happen when a SWI is interrupted (eg receiving a
562 ctrl-C whilst processing SWIRead()). The SWI will complete
563 returning -1 in r0 to the caller. If GDB is then used to
564 resume the system call the reason code will now be -1. */
567 /* Unimplemented reason codes. */
568 case AngelSWI_Reason_ReadC:
569 case AngelSWI_Reason_TmpNam:
570 case AngelSWI_Reason_System:
571 case AngelSWI_Reason_EnterSVC:
573 state->Emulate = FALSE;
576 case AngelSWI_Reason_Clock:
577 /* Return number of centi-seconds. */
579 #ifdef CLOCKS_PER_SEC
580 (CLOCKS_PER_SEC >= 100)
581 ? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
582 : (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
584 /* Presume unix... clock() returns microseconds. */
585 (ARMword) (clock () / 10000);
587 OSptr->ErrorNo = errno;
590 case AngelSWI_Reason_Time:
591 state->Reg[0] = (ARMword) sim_callback->time (sim_callback, NULL);
592 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
595 case AngelSWI_Reason_WriteC:
597 char tmp = ARMul_SafeReadByte (state, addr);
598 (void) sim_callback->write_stdout (sim_callback, &tmp, 1);
599 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
603 case AngelSWI_Reason_Write0:
604 SWIWrite0 (state, addr);
607 case AngelSWI_Reason_Close:
608 state->Reg[0] = sim_callback->close (sim_callback, ARMul_ReadWord (state, addr));
609 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
612 case AngelSWI_Reason_Seek:
613 state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, ARMul_ReadWord (state, addr),
614 ARMul_ReadWord (state, addr + 4),
616 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
619 case AngelSWI_Reason_FLen:
620 SWIflen (state, ARMul_ReadWord (state, addr));
623 case AngelSWI_Reason_GetCmdLine:
624 WriteCommandLineTo (state, ARMul_ReadWord (state, addr));
627 case AngelSWI_Reason_HeapInfo:
628 /* R1 is a pointer to a pointer. */
629 addr = ARMul_ReadWord (state, addr);
631 /* Pick up the right memory limit. */
633 temp = state->MemSize;
635 temp = ADDRUSERSTACK;
637 ARMul_WriteWord (state, addr, 0); /* Heap base. */
638 ARMul_WriteWord (state, addr + 4, temp); /* Heap limit. */
639 ARMul_WriteWord (state, addr + 8, temp); /* Stack base. */
640 ARMul_WriteWord (state, addr + 12, temp); /* Stack limit. */
643 case AngelSWI_Reason_ReportException:
644 if (state->Reg[1] == ADP_Stopped_ApplicationExit)
648 state->Emulate = FALSE;
651 case ADP_Stopped_ApplicationExit:
653 state->Emulate = FALSE;
656 case ADP_Stopped_RunTimeError:
658 state->Emulate = FALSE;
661 case AngelSWI_Reason_Errno:
662 state->Reg[0] = OSptr->ErrorNo;
665 case AngelSWI_Reason_Open:
667 ARMul_ReadWord (state, addr),
668 ARMul_ReadWord (state, addr + 4));
671 case AngelSWI_Reason_Read:
673 ARMul_ReadWord (state, addr),
674 ARMul_ReadWord (state, addr + 4),
675 ARMul_ReadWord (state, addr + 8));
678 case AngelSWI_Reason_Write:
680 ARMul_ReadWord (state, addr),
681 ARMul_ReadWord (state, addr + 4),
682 ARMul_ReadWord (state, addr + 8));
685 case AngelSWI_Reason_IsTTY:
686 state->Reg[0] = sim_callback->isatty (sim_callback,
687 ARMul_ReadWord (state, addr));
688 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
691 case AngelSWI_Reason_Remove:
693 ARMul_ReadWord (state, addr));
695 case AngelSWI_Reason_Rename:
697 ARMul_ReadWord (state, addr),
698 ARMul_ReadWord (state, addr + 4));
705 /* The following SWIs are generated by the softvectorcode[]
706 installed by default by the simulator. */
707 case 0x91: /* Undefined Instruction. */
709 ARMword addr = state->RegBank[UNDEFBANK][14] - 4;
711 sim_callback->printf_filtered
712 (sim_callback, "sim: exception: Unhandled Instruction '0x%08x' at 0x%08x. Stopping.\n",
713 ARMul_ReadWord (state, addr), addr);
714 state->EndCondition = RDIError_SoftwareInterrupt;
715 state->Emulate = FALSE;
719 case 0x90: /* Reset. */
720 case 0x92: /* SWI. */
721 /* These two can be safely ignored. */
724 case 0x93: /* Prefetch Abort. */
725 case 0x94: /* Data Abort. */
726 case 0x95: /* Address Exception. */
727 case 0x96: /* IRQ. */
728 case 0x97: /* FIQ. */
729 case 0x98: /* Error. */
734 /* This can happen when a SWI is interrupted (eg receiving a
735 ctrl-C whilst processing SWIRead()). The SWI will complete
736 returning -1 in r0 to the caller. If GDB is then used to
737 resume the system call the reason code will now be -1. */
740 case 0x180001: /* RedBoot's Syscall SWI in ARM mode. */
741 if (swi_mask & SWI_MASK_REDBOOT)
743 switch (state->Reg[0])
745 /* These numbers are defined in libgloss/syscall.h
746 but the simulator should not be dependend upon
747 libgloss being installed. */
749 state->Emulate = FALSE;
750 /* Copy exit code into r0. */
751 state->Reg[0] = state->Reg[1];
755 SWIopen (state, state->Reg[1], state->Reg[2]);
759 state->Reg[0] = sim_callback->close (sim_callback, state->Reg[1]);
760 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
764 SWIread (state, state->Reg[1], state->Reg[2], state->Reg[3]);
768 SWIwrite (state, state->Reg[1], state->Reg[2], state->Reg[3]);
772 state->Reg[0] = sim_callback->lseek (sim_callback,
776 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
779 case 17: /* Utime. */
780 state->Reg[0] = state->Reg[1] = (ARMword) sim_callback->time (sim_callback, NULL);
781 OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
784 case 7: /* Unlink. */
785 case 8: /* Getpid. */
787 case 10: /* Fstat. */
789 case 12: /* Argvlen. */
791 case 14: /* ChDir. */
793 case 16: /* Chmod. */
795 sim_callback->printf_filtered
797 "sim: unhandled RedBoot syscall `%d' encountered - "
798 "returning ENOSYS\n",
801 OSptr->ErrorNo = cb_host_to_target_errno
802 (sim_callback, ENOSYS);
804 case 1001: /* Meminfo. */
806 ARMword totmem = state->Reg[1],
807 topmem = state->Reg[2];
808 ARMword stack = state->MemSize > 0
809 ? state->MemSize : ADDRUSERSTACK;
811 ARMul_WriteWord (state, totmem, stack);
813 ARMul_WriteWord (state, topmem, stack);
819 sim_callback->printf_filtered
821 "sim: unknown RedBoot syscall '%d' encountered - ignoring\n",
834 if (SWI_vector_installed)
839 cpsr = ARMul_GetCPSR (state);
842 ARMul_SetSPSR (state, SVC32MODE, cpsr);
845 cpsr |= SVC32MODE | 0x80;
846 ARMul_SetCPSR (state, cpsr);
848 state->RegBank[SVCBANK][14] = state->Reg[14] = state->Reg[15] - i_size;
849 state->NextInstr = RESUME;
850 state->Reg[15] = state->pc = ARMSWIV;
855 sim_callback->printf_filtered
857 "sim: unknown SWI encountered - %x - ignoring\n",